; -------------------------------------------------------------------------------- ; @Title: S6j330 On-Chip Peripherals ; @Props: Released ; @Author: ASK, SEB, STR, DOR, DAM, DLI, MJW ; @Changelog: 2016-06-30 ASK ; 2016-10-27 SEB ; 2016-10-27 STR ; 2019-04-01 MJW ; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation ; @Doc: Traveo_Family_Hardware_Manual_Platform_Part.pdf (Rev. *A) ; S6J3300_Series_32-bit_Microcontroller_Spansion_R_Traveo_TM_Family_Hardware_Manual.pdf (Rev. *A) ; 002-10634_S6J3350_Series_32-bit_Microcontroller_Spansion_R_Traveo_TM_Family.pdf (2016-03-04) ; 002-10635_S6J3310_S6J3320_S6J3330_S6J3340_Series_32-bit_Microcontroller_Spansion_R_Traveo_TM_Family.pdf (2016-03-04) ; 002-03359_S6J3360_Series_S6J3370_Series_32-bit_Arm_Cortex_-R5F_Traveo_Microcontroller_Datasheet.pdf (Rev. *G, 2018-08-21) ; 002-18302_32-BIT_MICROCONTROLLER_S6J3360_S6J3370_SERIES_HARDWARE_MANUAL_TRAVEO_TM_FAMILY.pdf (Rev. *E) ; 32-BIT_MICROCONTROLLER_TRAVEO_TM_FAMILY_HARDWARE_MANUAL_PLATFORM_PART.pdf (Rev. *D) ; Product Overview s6j336 s6j337 _MCU_FAMILY_CLASSICAL_CLUSTER_SOLUTIONS.pdf (Rev. *B) ; @Core: Cortex-R5F ; @Chip: S6J331AHA, S6J331BHA, S6J331BHB, S6J331BHC, S6J331BHD, S6J331BHS ; S6J331BHU, S6J331BJA, S6J331BJB, S6J331BJC, S6J331BJD, S6J331BJS ; S6J331BJU, S6J331BKA, S6J331BKB, S6J331BKC, S6J331BKD, S6J331BKS ; S6J331BKU, S6J331CHA, S6J331CHB, S6J331CHC, S6J331CHD, S6J331CHS ; S6J331CHU, S6J331CJA, S6J331CJB, S6J331CJC, S6J331CJD, S6J331CJS ; S6J331CJU, S6J331CKA, S6J331CKB, S6J331CKC, S6J331CKD, S6J331CKS ; S6J331CKU, S6J331DHA, S6J331DHB, S6J331DHC, S6J331DHD, S6J331DHS ; S6J331DHU, S6J331DJA, S6J331DJB, S6J331DJC, S6J331DJD, S6J331DJS ; S6J331DJU, S6J331DKA, S6J331DKB, S6J331DKC, S6J331DKD, S6J331DKS ; S6J331DKU, S6J331EHA, S6J331EHB, S6J331EHC, S6J331EHD, S6J331EHS ; S6J331EHU, S6J331EJA, S6J331EJB, S6J331EJC, S6J331EJD, S6J331EJS ; S6J331EJU, S6J331EKA, S6J331EKB, S6J331EKC, S6J331EKD, S6J331EKS ; S6J331EKU, S6J332BHA, S6J332BHB, S6J332BHC, S6J332BHD, S6J332BHS ; S6J332BHU, S6J332BJA, S6J332BJB, S6J332BJC, S6J332BJD, S6J332BJS ; S6J332BJU, S6J332BKA, S6J332BKB, S6J332BKC, S6J332BKD, S6J332BKS ; S6J332BKU, S6J332CHA, S6J332CHB, S6J332CHC, S6J332CHD, S6J332CHS ; S6J332CHU, S6J332CJA, S6J332CJB, S6J332CJC, S6J332CJD, S6J332CJS ; S6J332CJU, S6J332CKA, S6J332CKB, S6J332CKC, S6J332CKD, S6J332CKS ; S6J332CKU, S6J332DHA, S6J332DHB, S6J332DHC, S6J332DHD, S6J332DHS ; S6J332DHU, S6J332DJA, S6J332DJB, S6J332DJC, S6J332DJD, S6J332DJS ; S6J332DJU, S6J332DKA, S6J332DKB, S6J332DKC, S6J332DKD, S6J332DKS ; S6J332DKU, S6J332EHA, S6J332EHB, S6J332EHC, S6J332EHD, S6J332EHS ; S6J332EHU, S6J332EJA, S6J332EJB, S6J332EJC, S6J332EJD, S6J332EJS ; S6J332EJU, S6J332EKA, S6J332EKB, S6J332EKC, S6J332EKD, S6J332EKS ; S6J332EKU, S6J333BHA, S6J333BHB, S6J333BHC, S6J333BHD, S6J333BHS ; S6J333BHU, S6J333BJA, S6J333BJB, S6J333BJC, S6J333BJD, S6J333BJS ; S6J333BJU, S6J333BKA, S6J333BKB, S6J333BKC, S6J333BKD, S6J333BKS ; S6J333BKU, S6J333CHA, S6J333CHB, S6J333CHC, S6J333CHD, S6J333CHS ; S6J333CHU, S6J333CJA, S6J333CJB, S6J333CJC, S6J333CJD, S6J333CJS ; S6J333CJU, S6J333CKA, S6J333CKB, S6J333CKC, S6J333CKD, S6J333CKS ; S6J333CKU, S6J333DHA, S6J333DHB, S6J333DHC, S6J333DHD, S6J333DHS ; S6J333DHU, S6J333DJA, S6J333DJB, S6J333DJC, S6J333DJD, S6J333DJS ; S6J333DJU, S6J333DKA, S6J333DKB, S6J333DKC, S6J333DKD, S6J333DKS ; S6J333DKU, S6J333EHA, S6J333EHB, S6J333EHC, S6J333EHD, S6J333EHS ; S6J333EHU, S6J333EJA, S6J333EJB, S6J333EJC, S6J333EJD, S6J333EJS ; S6J333EJU, S6J333EKA, S6J333EKB, S6J333EKC, S6J333EKD, S6J333EKS ; S6J333EKU, S6J334BHA, S6J334BHB, S6J334BHC, S6J334BHD, S6J334BHS ; S6J334BHU, S6J334BJA, S6J334BJB, S6J334BJC, S6J334BJD, S6J334BJS ; S6J334BJU, S6J334BKA, S6J334BKB, S6J334BKC, S6J334BKD, S6J334BKS ; S6J334BKU, S6J334CHA, S6J334CHB, S6J334CHC, S6J334CHD, S6J334CHS ; S6J334CHU, S6J334CJA, S6J334CJB, S6J334CJC, S6J334CJD, S6J334CJS ; S6J334CJU, S6J334CKA, S6J334CKB, S6J334CKC, S6J334CKD, S6J334CKS ; S6J334CKU, S6J334DHA, S6J334DHB, S6J334DHC, S6J334DHD, S6J334DHS ; S6J334DHU, S6J334DJA, S6J334DJB, S6J334DJC, S6J334DJD, S6J334DJS ; S6J334DJU, S6J334DKA, S6J334DKB, S6J334DKC, S6J334DKD, S6J334DKS ; S6J334DKU, S6J334EHA, S6J334EHB, S6J334EHC, S6J334EHD, S6J334EHS ; S6J334EHU, S6J334EJA, S6J334EJB, S6J334EJC, S6J334EJD, S6J334EJS ; S6J334EJU, S6J334EKA, S6J334EKB, S6J334EKC, S6J334EKD, S6J334EKS ; S6J334EKU, S6J335DHA, S6J335DHB, S6J335DHC, S6J335DHD, S6J335DHS ; S6J335DHU, S6J335DJA, S6J335DJB, S6J335DJC, S6J335DJD, S6J335DJS ; S6J335DJU, S6J335DKA, S6J335DKB, S6J335DKC, S6J335DKD, S6J335DKS ; S6J335DKU, S6J335EHA, S6J335EHB, S6J335EHC, S6J335EHD, S6J335EHS ; S6J335EHU, S6J335EJA, S6J335EJB, S6J335EJC, S6J335EJD, S6J335EJS ; S6J335EJU, S6J335EKA, S6J335EKB, S6J335EKC, S6J335EKD, S6J335EKS ; S6J335EKU, S6J336AHA, S6J336AHE, S6J336AHS, S6J336AHT, S6J336AJA ; S6J336AJE, S6J336AJS, S6J336AJT, S6J336CHA, S6J336CHS, S6J336CHT ; S6J336CJA, S6J336CJE, S6J336CJS, S6J336CJT, S6J337AHT, S6J337AHU ; S6J337BJS, S6J337CJS ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pers6j330.per 10412 2019-04-04 12:46:01Z mkolodziejczyk $ config 16. 8. tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end tree "MODEC (Operation Mode)" base ad:0xB0600800 width 7. rgroup.long 0x00++0x03 line.long 0x00 "MODER,Mode Register" bitfld.long 0x00 31. " USERMODE ,User mode bit" "Board,User" bitfld.long 0x00 12. " MD ,Mode bit" "0,1" width 0x0B tree.end tree "RESET" base ad:0xB0600380 width 17. wgroup.long 0x00++0x03 line.long 0x00 "RSTCNTR,Reset Control Register" hexmask.long.byte 0x00 24.--31. 1. " DBGR ,Software debugger reset register bit" hexmask.long.byte 0x00 16.--23. 1. " SWHRST ,Software trigger hard reset register bit" hexmask.long.byte 0x00 0.--7. 1. " SWRST ,Software reset register bit" group.long 0x10++0x0B line.long 0x00 "RSTCAUSEUR,User Factor Register" bitfld.long 0x00 31. " LVDL2R ,Extended internal power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 30. " LVDL1R ,Internal power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 29. " CSVSCRR ,Slow CR clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 28. " CSVFCRR ,Fast CR clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 27. " CSVSR0 ,SSCG0 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 26. " CSVPR0 ,PLL0 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 25. " CSVSOR ,Sub clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 24. " CSVMOR ,Main clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 20. " SHRST ,Software trigger hard reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " SRST ,Software reset detection bit" "Not detected,Detected" bitfld.long 0x00 12. " SWDR ,Software watchdog reset detection bit" "Not detected,Detected" bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected" newline sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 9. " SRSTX ,NSRST pin input reset detection bit" "Not detected,Detected" bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected" newline else bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected" newline endif bitfld.long 0x00 7. " LVDH2R ,Extended external power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 6. " LVDH1R ,External external power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected" bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected" newline sif (!cpuis("S6J33*")) bitfld.long 0x00 2. " INITX ,XX detection bit" "Not detected,Detected" bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected" else bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected" endif line.long 0x04 "EXCSVRSTCAUSEUR,User Extended CSV Reset Factor Register" bitfld.long 0x04 7. " CSVSR3 ,SSCG3 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 6. " CSVSR2 ,SSCG2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 5. " CSVSR1 ,SSCG1 clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x04 3. " CSVPR3 ,PLL3 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 2. " CSVPR2 ,PLL2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 1. " CSVPR1 ,PLL1 clock supervisor reset detection bit" "Not detected,Detected" line.long 0x08 "PDRSTCAUSEUR,User PowerDomain Reset Factor Register" bitfld.long 0x08 17. " PD6R1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 16. " PD6R0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 15. " PD5R3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x08 14. " PD5R2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 13. " PD5R1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 12. " PD5R0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 9. " PD4R1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 8. " PD4R0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 4. " PD3R0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 0. " PD2R0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" group.long 0x20++0x0B line.long 0x00 "RSTCAUSEBT,BootROM Reset Factor Register" bitfld.long 0x00 31. " LVDL2R ,Extended internal power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 30. " LVDL1R ,Internal power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 29. " CSVSCRR ,Slow CR clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 28. " CSVFCRR ,Fast CR clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 27. " CSVSR0 ,SSCG0 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 26. " CSVPR0 ,PLL0 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 25. " CSVSOR ,Sub clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 24. " CSVMOR ,Main clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 20. " SHRST ,Software trigger hard reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " SRST ,Software reset detection bit" "Not detected,Detected" bitfld.long 0x00 12. " SWDR ,Software watchdog reset detection bit" "Not detected,Detected" bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected" newline sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 9. " SRSTX ,NSRST pin input reset detection bit" "Not detected,Detected" bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected" newline else bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected" newline endif bitfld.long 0x00 7. " LVDH2R ,Extended external power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 6. " LVDH1R ,External power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected" bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected" newline sif !cpuis("S6J33*") bitfld.long 0x00 2. " INITX ,XX reset detection bit" "Not detected,Detected" bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected" else bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected" endif line.long 0x04 "EXCSVRSTCAUSEBT,BootROM Extended CSV Reset Factor Register" bitfld.long 0x04 7. " CSVSR3 ,SSCG3 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 6. " CSVSR2 ,SSCG2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 5. " CSVSR1 ,SSCG1 clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x04 3. " CSVPR3 ,PLL3 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 2. " CSVPR2 ,PLL2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 1. " CSVPR1 ,PLL1 clock supervisor reset detection bit" "Not detected,Detected" line.long 0x08 "PDRSTCAUSEBT,BootROM PowerDomain Reset Factor Register" bitfld.long 0x08 17. " PD6R1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 16. " PD6R0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 15. " PD5R3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x08 14. " PD5R2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 13. " PD5R1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 12. " PD5R0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 9. " PD4R1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 8. " PD4R0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 4. " PD3R0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 0. " PD2R0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" sif cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x34++0x03 line.long 0x00 "PDRSTSTATUS,PowerDomain Reset Status Register" bitfld.long 0x00 17. " PD6RS1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " PD6RS0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 15. " PD5RS3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x00 14. " PD5RS2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 13. " PD5RS1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 12. " PD5RS0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 9. " PD4RS1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 8. " PD4RS0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 4. " PD3RS0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PD2RS0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" else group.long 0x34++0x03 line.long 0x00 "PDRSTATUS,PowerDomain Reset Status Register" bitfld.long 0x00 17. " PD6RS1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " PD6RS0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 15. " PD5RS3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x00 14. " PD5RS2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 13. " PD5RS1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 12. " PD5RS0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 9. " PD4RS1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 8. " PD4RS0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 4. " PD3RS0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PD2RS0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" endif width 0x0B tree.end tree "CLOCK SYSTEM" base ad:0xB0600600 width 15. group.long 0x00++0x03 line.long 0x00 "CRCNTR,CR Clock Control Register" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 24. " CALIBCSEL ,CR calibration clock select bit (LP Type only)" "Fast-CR,Slow-CR" bitfld.long 0x00 16.--20. " TRV ,Voltage trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpuis("S6J33*")) bitfld.long 0x00 16.--20. " TRV ,Voltage trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--12. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("S6J33*")) group.long 0x34++0x03 line.long 0x00 "SCRCNTR,Slow-CR Clock Control Register" bitfld.long 0x00 8.--10. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x04++0x0B line.long 0x00 "MOSCCNTR,Main Oscillator Control Register" bitfld.long 0x00 31. " MCMODE ,Main clock amplifier oscillation mode bit" "Oscillation mode,Stop mode" bitfld.long 0x00 26.--27. " MCGAIN ,Main clock gain bit" "4(3.6)MHz,8MHz,16MHz,25MHz" bitfld.long 0x00 8. " DIV2SEL ,Select bit" "Main clock,Main clk/2" newline bitfld.long 0x00 0. " FCIMEN ,Fast main clock input enable control bit" "Disabled,Enabled" line.long 0x04 "SOSCCNTR,Sub Oscillator Control Register" bitfld.long 0x04 16. " SUBPORT ,This bit is used to set Port function for sub clock input" "Disabled,Enabled" line.long 0x08 "PLLSSCGSTCNTR,PLL/SSCG Stabilization Time Control Register" bitfld.long 0x08 4.--7. " SSCGSTABS ,Stabilization time for SSCG PLL0/1/2/3 clock" ",,,,,,,,2^9 cycle,2^10 cycle,2^11 cycle,2^12 cycle,2^13 cycle,2^14 cycle,2^15 cycle,2^16 cycle" bitfld.long 0x08 0.--3. " PLLSTABS ,Stabilization time for PLL0/1/2/3 clock" ",,,,,,,,2^9 cycle,2^10 cycle,2^11 cycle,2^12 cycle,2^13 cycle,2^14 cycle,2^15 cycle,2^16 cycle" group.long 0x10++0x03 line.long 0x00 "PLL0CGCNTR,PLL0 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "PLL1CGCNTR,PLL1 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "PLL2CGCNTR,PLL2 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "PLL3CGCNTR,PLL3 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "SSCG0CGCNTR,SSCG PPL0 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "SSCG1CGCNTR,SSCG PPL1 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "SSCG2CGCNTR,SSCG PPL2 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "SSCG3CGCNTR,SSCG PPL3 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 step,2 steps,3 steps,4 steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" else bitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" endif bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Start clk. operation" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "CKOTCNTR,Clock Output Function Control Register" bitfld.long 0x00 24. " ENCLKO ,Enable/Disable clock output function" "Disabled,Enabled" bitfld.long 0x00 8.--10. " CKOUTDIV ,Clock Division bits" "Not divided,/2,/4,/8,/16,/32,/64,/128" sif cpuis("S6J336*") bitfld.long 0x00 0.--3. " CKSEL ,Clock Select bits" "Fast-CR,Slow-CR,Main,Sub,PLL0,PLL1,PLL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Tied to low" else bitfld.long 0x00 0.--3. " CKSEL ,Clock Select bits" "Fast-CR,Slow-CR,Main,Sub,PLL0,PLL1,PLL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,Prohibit(Fast-CR),Prohibit(Fast-CR),Prohibit(Fast-CR),Tied to low" endif width 0x0B tree.end tree "LPC (LOW POWER CONSUMPTION)" tree "SYSC 0" base ad:0xB0600000 width 15. group.long 0x00++0x03 "Protection Register" line.long 0x00 "PROTKEYR,Protection Key Setting Register" group.long 0x80++0x0B "Run Profile Registers" line.long 0x00 "RUNPDCFGR,RUN Power Domain Setting Register" rbitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply" "Not supply,Supply" rbitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply" "Not supply,Supply" bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply" "Not supply,Supply" bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply" "Not supply,Supply" newline bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply" "Not supply,Supply" bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply" "Not supply,Supply" bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply" "Not supply,Supply" bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply" "Not supply,Supply" newline rbitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply" "Not supply,Supply" rbitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply" "Not supply,Supply" line.long 0x04 "RUNCKSRER,RUN Clock Source Enable Register" bitfld.long 0x04 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x08 "RUNCKSELR,Run Clock Selection Register" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Clock fixed al 'L'" rgroup.long 0x8C++0x03 line.long 0x00 "RUNCKER,RUN Clock Enable Register" bitfld.long 0x00 1. " ENCLKMCUCP ,MCUconfig APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " ENCLKMCUCH ,MCUconfig AHB clock oscillation enable bit" "Disabled,Enabled" group.long 0x90++0x3B line.long 0x00 "RUNCKDIVR,RUN Clock Divider Register" bitfld.long 0x00 8.--11. " MCUCPDIV ,MCUconfig APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " MCUCHDIV ,MCUconfig AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x04 "RUNPLL0CNTR,Run PLL0 Control Register" bitfld.long 0x04 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x04 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x04 8.--11. " PLL0DIVM ,PLL0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x04 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x08 "RUNPLL1CNTR,RUN PLL1 Control Register" bitfld.long 0x08 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x08 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x08 8.--11. " PLL1DIVM ,PLL1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x08 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x0C "RUNPLL2CNTR,RUN PLL2 Control Register" bitfld.long 0x0C 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x0C 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x0C 8.--11. " PLL2DIVM ,PLL2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x0C 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x10 "RUNPLL3CNTR,RUN PLL3 Control Register" bitfld.long 0x10 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x10 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplier setting bits" bitfld.long 0x10 8.--11. " PLL3DIVM ,PLL3 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x10 0.--1. " PLL3DIVL ,PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x14 "RUNSSCG0CNTR0,RUN SSCG0 Control Register 0" bitfld.long 0x14 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x14 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x14 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x14 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x18 "RUNSSCG0CNTR1,RUN SSCG0 Control Register 1" bitfld.long 0x18 24. " SSCG0SSEN ,SSCG PLL0 enable setting bit" "Disabled,Enabled" bitfld.long 0x18 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x18 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x18 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" line.long 0x1C "RUNSSCG1CNTR0,RUN SSCG1 Control Register 0" bitfld.long 0x1C 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x1C 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x1C 8.--11. " SSCG1DIVM ,SSCG PLL1 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x1C 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x20 "RUNSSCG1CNTR1,RUN SSCG1 Control Register 1" bitfld.long 0x20 24. " SSCG1SSEN ,SSCG PLL1 enable setting bit" "Disabled,Enabled" bitfld.long 0x20 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x20 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x20 0.--9. 1. " SSCG1RATE ,SSCG PLL1 clock modulation ratio control bits" line.long 0x24 "RUNSSCG2CNTR0,RUN SSCG2 Control Register 0" bitfld.long 0x24 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x24 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x24 8.--11. " SSCG2DIVM ,SSCG PLL2 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x24 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x28 "RUNSSCG2CNTR1,RUN SSCG2 Control Register 1" bitfld.long 0x28 24. " SSCG2SSEN ,SSCG PLL2 enable setting bit" "Disabled,Enabled" bitfld.long 0x28 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x28 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x28 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" line.long 0x2C "RUNSSCG3CNTR0,RUN SSCG3 Control Register 0" bitfld.long 0x2C 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x2C 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x2C 8.--11. " SSCG3DIVM ,SSCG PLL3 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x2C 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x30 "RUNSSCG3CNTR1,RUN SSCG3 Control Register 1" bitfld.long 0x30 24. " SSCG3SSEN ,SSCG PLL3 enable setting bit" "Disabled,Enabled" bitfld.long 0x30 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x30 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x30 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" line.long 0x34 "RUNLVDCFGR,RUN Low-voltage Detection Setting Register" bitfld.long 0x34 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x34 25.--27. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0.875,0.950,?..." else bitfld.long 0x34 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" textfld " " endif bitfld.long 0x34 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled" bitfld.long 0x34 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,Interrupt" newline bitfld.long 0x34 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x34 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x34 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,?..." bitfld.long 0x34 9.--11. " LVDH1V ,Extended internal low-voltage detection voltage setting bits" "2.70,2.80,3.60,3.80,4.00,4.20,2.50,2.60" else bitfld.long 0x34 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x34 9.--12. " LVDH1V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x34 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" bitfld.long 0x34 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x34 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",2.80,3.60,3.80,4.00,4.20,?..." else bitfld.long 0x34 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " endif bitfld.long 0x34 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x38 "RUNCSVCFGR,Run Clock Supervisor Setting Register" bitfld.long 0x38 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x38 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x38 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 2. " FCRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x38 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" sif (!cpuis("S6J33*")) group.long 0xCC++0x3 line.long 0x00 "RUNREGCFGR,RUN Regular Setting Register" rbitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main mode,?..." bitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bits" "1.20V,1.25V" else group.long 0xCC++0x3 line.long 0x00 "RUNREGCFGR,RUN Regular Setting Register" rbitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main mode,?..." endif wgroup.long 0xFC++0x3 line.long 0x00 "TRGRUNCNTR,RUN Update Trigger Register" hexmask.long.byte 0x00 0.--7. 1. " APPLY_RUN ,RUN profile update trigger setting bit" group.long 0x100++0x4B "PSS Profile Group Registers" line.long 0x00 "PSSPDCFGR,PSS Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply control bit" "Not supply,Supply" bitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply control bit" "Not supply,Supply" bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply control bit" "Not supply,Supply" bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply control bit" "Not supply,Supply" newline bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply control bit" "Not supply,Supply" bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply control bit" "Not supply,Supply" bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply control bit" "Not supply,Supply" bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply control bit" "Not supply,Supply" newline bitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply control bit" "Not supply,Supply" bitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply control bit" "Not supply,Supply" line.long 0x04 "PSSCKSRER,PSS Clock Source Enable Register" bitfld.long 0x04 19. " SSCG3EN ,SSCG PPL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PPL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PPL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PPL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3EN ,PPL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PPL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PPL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PPL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x08 "PSSCKSELR,PSS Clock Selection Register" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PPL0,,Fixed at 'L'" line.long 0x0C "PSSCKER,PSS Clock Enable Register" bitfld.long 0x0C 1. " ENCLKMCUCP ,MCUconfig APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 0. " ENCLKMCUCH ,MCUconfig AHB clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "PSSCKDIVR,PSS Clock Divider Register" bitfld.long 0x10 8.--11. " MCUCPDIV ,MCUconfig APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " MCUCHDIV ,MCUconfig AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x14 "PSSPLL0CNTR,PSS PPL0 Control Register" bitfld.long 0x14 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x14 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x14 8.--11. " PLL0DIVM ,PLL0 M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x14 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x18 "PSSPLL1CNTR,PSS PPL1 Control Register" bitfld.long 0x18 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x18 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x18 8.--11. " PLL1DIVM ,PLL1 M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x18 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x1C "PSSPLL2CNTR,PSS PPL2 Control Register" bitfld.long 0x1C 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x1C 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x1C 8.--11. " PLL2DIVM ,PLL2 M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x1C 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x20 "PSSPLL3CNTR,PSS PPL3 Control Register" bitfld.long 0x20 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x20 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplier setting bits" bitfld.long 0x20 8.--11. " PLL3DIVM ,PLL3 M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x20 0.--1. " PLL3DIVL ,PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x24 "PSSSSCG0CNTR0,PSS SSCG0 Control Register 0" bitfld.long 0x24 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x24 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 N-multiplier setting bits" bitfld.long 0x24 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x24 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x28 "PSSSSCG0CNTR1,PSS SSCG0 Control Register 1" bitfld.long 0x28 24. " SSCG0SSEN ,SSCG PLL0 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x28 17.--18. " SSCG0FREQ ,SSCG PLL0 modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x28 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x28 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" line.long 0x2C "PSSSSCG1CNTR0,PSS SSCG1 Control Register 0" bitfld.long 0x2C 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x2C 16.--23. 1. " SSCG1DIVN ,SSCG PLL0 N-multiplier setting bits" bitfld.long 0x2C 8.--11. " SSCG1DIVM ,SSCG PLL1 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x2C 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x30 "PSSSSCG1CNTR1,PSS SSCG1 Control Register 1" bitfld.long 0x30 24. " SSCG1SSEN ,SSCG PLL1 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x30 17.--18. " SSCG1FREQ ,SSCG PLL1 modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x30 16. " SSCG1MODE ,SSCG PLL modulation mode setting bit" "Down,Center" hexmask.long.word 0x30 0.--9. 1. " SSCG0RATE ,SSCG PLL clock modulation ratio control bits" line.long 0x34 "PSSSSCG2CNTR0,PSS SSCG2 Control Register 0" bitfld.long 0x34 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x34 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 N-multiplier setting bits" bitfld.long 0x34 8.--11. " SSCG2DIVM ,SSCG PLL2 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x34 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x38 "PSSSSCG2CNTR1,PSS SSCG2 Control Register 1" bitfld.long 0x38 24. " SSCG2SSEN ,SSCG PLL2 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x38 17.--18. " SSCG2FREQ ,SSCG PLL2 modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x38 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x38 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" line.long 0x3C "PSSSSCG3CNTR0,PSS SSCG3 Control Register 0" bitfld.long 0x3C 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x3C 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 N-multiplier setting bits" bitfld.long 0x3C 8.--11. " SSCG3DIVM ,SSCG PLL3 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x3C 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x40 "PSSSSCG3CNTR1,PSS SSCG3 Control Register 1" bitfld.long 0x40 24. " SSCG3SSEN ,SSCG PLL3 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x40 17.--18. " SSCG3FREQ ,SSCG PLL3 modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x40 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x40 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" line.long 0x44 "PSSLVDCFGR,PSS Low-voltage Detection setting register" bitfld.long 0x44 30. " LVDL1S ,Internal Low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x44 25.--27. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0.875,0.950,?..." else bitfld.long 0x44 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" textfld " " endif bitfld.long 0x44 24. " LVDL1E ,Low-voltage detection operation enable bit" "Disabled,Enabled" bitfld.long 0x44 22. " LVDL2S ,Extended internal low-voltage operation selection bit" "Reset,Interrupt" newline bitfld.long 0x44 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x44 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x44 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,?..." bitfld.long 0x44 9.--11. " LVDH1V ,Extended internal low-voltage detection voltage setting bits" "2.70,2.80,3.60,3.80,4.00,4.20,2.50,2.60" else bitfld.long 0x44 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x44 9.--12. " LVDH1V ,External low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x44 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" bitfld.long 0x44 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x44 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",2.80,3.60,3.80,4.00,4.20,?..." else bitfld.long 0x44 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " endif bitfld.long 0x44 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x48 "PSSCSVCFGR,PSS Clock Supervisor Setting Register" bitfld.long 0x48 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x48 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x48 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 2. " CRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" sif (!cpuis("S6J33*")) group.long 0x14C++0x03 line.long 0x00 "PSSREGCFGR,PSS Regulator Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" rbitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bit" "1.20v,1.25v" else group.long 0x14C++0x03 line.long 0x00 "PSSREGCFGR,PSS Regulator Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" endif wgroup.byte 0x17C++0x00 line.byte 0x00 "PSSENR,PSS Profile Update Enable Register" hexmask.byte 0x00 0.--7. 1. " PSSEN0 ,PSS profile update enable setting bits" rgroup.long 0x180++0x4B "APP Profile Group Registers" line.long 0x00 "APPPDCFGR,APP Power Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Power control bit for power domain 6_1" "Off,On" bitfld.long 0x00 24. " PD6_0EN ,Power control bit for power domain 6_0" "Off,On" bitfld.long 0x00 23. " PD5_3EN ,Power control bit for power domain 5_3" "Off,On" bitfld.long 0x00 22. " PD5_2EN ,Power control bit for power domain 5_2" "Off,On" newline bitfld.long 0x00 21. " PD5_1EN ,Power control bit for power domain 5_1" "Off,On" bitfld.long 0x00 20. " PD5_0EN ,Power control bit for power domain 5_0" "Off,On" bitfld.long 0x00 17. " PD4_1EN ,Power control bit for power domain 4_1" "Off,On" bitfld.long 0x00 16. " PD4_0EN ,Power control bit for power domain 4_0" "Off,On" newline bitfld.long 0x00 12. " PD3EN ,Power control bit for power domain 3" "Off,On" bitfld.long 0x00 8. " PD2EN ,Power control bit for power domain 2" "Off,On" line.long 0x04 "APPCKSRER,APP Clock Source Enable Register" bitfld.long 0x04 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x08 "APPCKSELR,APP Clock Selection Register" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed CR,Low-speed CR,Main clock,Sub clock,PPL0,SSCG PPL0,,Fixed to 'L'" line.long 0x0C "APPCKER,APP Clock Enable Register" bitfld.long 0x0C 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "APPCKDIVR,APP Clock Divider Register" bitfld.long 0x10 8.--11. " MCUCPDIV ,MCU config APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " MCUCHDIV ,MCU config AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x14 "APPPLL0CNTR,APP PLL 0 Control Register" bitfld.long 0x14 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x14 16.--23. 1. " PLL0DIVN ,NPLL0 clock N-multiplier ratio setting bits" bitfld.long 0x14 8.--11. " PLL0DIVM ,PP0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x14 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x18 "APPPLL1CNTR,APP PLL 1 Control Register" bitfld.long 0x18 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x18 16.--23. 1. " PLL1DIVN ,NPLL1 clock N-multiplier ratio setting bits" bitfld.long 0x18 8.--11. " PLL1DIVM ,PP1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x18 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x1C "APPPLL2CNTR,APP PLL 2 Control Register" bitfld.long 0x1C 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x1C 16.--23. 1. " PLL2DIVN ,NPLL2 clock N-multiplier ratio setting bits" bitfld.long 0x1C 8.--11. " PLL2DIVM ,PP2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x1C 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x20 "APPPLL3CNTR,APP PLL 3 Control Register" bitfld.long 0x20 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x20 16.--23. 1. " PLL3DIVN ,NPLL3 clock N-multiplier ratio setting bits" bitfld.long 0x20 8.--11. " PLL3DIVM ,PP3 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x20 0.--1. " PLL3DIVL ,PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x24 "APPSSCG0CNTR0,APP SSCG0 Control Register 0" bitfld.long 0x24 31. " SSCG0ISEL ,SSCG PLL PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x24 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x24 8.--11. " SSCG0DIVM ,SSCG PLL0 Clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x24 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x28 "APPSSCG0CNTR1,APP SSCG0 Control Register 1" bitfld.long 0x28 24. " SSCG0SSEN ,SSCG PP0 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x28 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x28 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x28 0.--9. 1. " SSCG0RATE ,PLL0 clock modulation ratio control bits" line.long 0x2C "APPSSCG1CNTR0,APP SSCG1 Control Register 0" bitfld.long 0x2C 31. " SSCG1ISEL ,SSCG PLL PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x2C 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x2C 8.--11. " SSCG1DIVM ,SSCG PLL1 Clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x2C 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x30 "APPSSCG1CNTR1,APP SSCG1 Control Register 1" bitfld.long 0x30 24. " SSCG1SSEN ,SSCG PP1 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x30 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x30 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x30 0.--9. 1. " SSCG1RATE ,PLL1 clock modulation ratio control bits" line.long 0x34 "APPSSCG2CNTR0,APP SSCG2 Control Register 0" bitfld.long 0x34 31. " SSCG2ISEL ,SSCG PLL PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x34 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x34 8.--11. " SSCG2DIVM ,SSCG PLL2 Clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x34 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x38 "APPSSCG2CNTR1,APP SSCG2 Control Register 1" bitfld.long 0x38 24. " SSCG2SSEN ,SSCG PP2 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x38 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x38 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x38 0.--9. 1. " SSCG2RATE ,PLL2 clock modulation ratio control bits" line.long 0x3C "APPSSCG3CNTR0,APP SSCG3 Control Register 0" bitfld.long 0x3C 31. " SSCG3ISEL ,SSCG PLL PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x3C 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x3C 8.--11. " SSCG3DIVM ,SSCG PLL3 Clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x3C 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x40 "APPSSCG3CNTR1,APP SSCG3 Control Register 1" bitfld.long 0x40 24. " SSCG3SSEN ,SSCG PP3 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x40 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x40 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x40 0.--9. 1. " SSCG3RATE ,PLL3 clock modulation ratio control bits" line.long 0x44 "APLLVDCFGR,APP Low-voltage Detection Setting Register" bitfld.long 0x44 30. " LVDL1S ,Internal Low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x44 25.--27. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0.875,0.950,?..." else bitfld.long 0x44 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" textfld " " endif bitfld.long 0x44 24. " LVDL1E ,Internal Low-voltage detection operation enable bit" "Disabled,Enabled" bitfld.long 0x44 22. " LVDL2S ,Extended internal low-voltage operation selection bit" "Reset,Interrupt" newline bitfld.long 0x44 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x44 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x44 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,?..." bitfld.long 0x44 9.--11. " LVDH1V ,Extended internal low-voltage detection voltage setting bits" "2.70,2.80,3.60,3.80,4.00,4.20,2.50,2.60" else bitfld.long 0x44 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x44 9.--12. " LVDH1V ,External low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x44 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" bitfld.long 0x44 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x44 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",2.80,3.60,3.80,4.00,4.20,?..." else bitfld.long 0x44 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " endif bitfld.long 0x44 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x48 "APPCSVCFGR,APP Clock Supervisor Setting Register" bitfld.long 0x48 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x48 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x48 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 2. " CRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x48 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" sif (!cpuis("S6J33*")) rgroup.long 0x1CC++0x03 line.long 0x00 "APPREGCFGR,APP Regulator Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" bitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bit" "1.20v,1.25v" else rgroup.long 0x1CC++0x03 line.long 0x00 "APPREGCFGR,APP Regulator Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" endif sif cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x200++0x03 "STS Profile Group Registers" line.long 0x00 "STSPDCFGR,STS Power Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Domain 6_1 power suPLLy control bit" "Off,On" bitfld.long 0x00 24. " PD6_0EN ,Domain 6_0 power supply control bit" "Off,On" bitfld.long 0x00 23. " PD5_3EN ,Domain 5_3 power supply control bit" "Off,On" bitfld.long 0x00 22. " PD5_2EN ,Domain 5_2 power supply control bit" "Off,On" newline bitfld.long 0x00 21. " PD5_1EN ,Domain 5_1 power supply control bit" "Off,On" bitfld.long 0x00 20. " PD5_0EN ,Domain 5_0 power supply control bit" "Off,On" bitfld.long 0x00 17. " PD4_1EN ,Domain 4_1 power supply control bit" "Off,On" bitfld.long 0x00 16. " PD4_0EN ,Domain 4_0 power supply control bit" "Off,On" newline bitfld.long 0x00 12. " PD3EN ,Domain 3 power supply control bit" "Off,On" bitfld.long 0x00 8. " PD2EN ,Domain 2 power supply control bit" "Off,On" else group.long 0x200++0x3 "STS Profile Group Registers" line.long 0x00 "STSPDCFGR,STS Power Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Domain 6_1 power supply control bit" "Off,On" bitfld.long 0x00 24. " PD6_0EN ,Domain 6_0 power supply control bit" "Off,On" bitfld.long 0x00 23. " PD5_3EN ,Domain 5_3 power supply control bit" "Off,On" bitfld.long 0x00 22. " PD5_2EN ,Domain 5_2 power supply control bit" "Off,On" newline bitfld.long 0x00 21. " PD5_1EN ,Domain 5_1 power supply control bit" "Off,On" bitfld.long 0x00 20. " PD5_0EN ,Domain 5_0 power supply control bit" "Off,On" bitfld.long 0x00 17. " PD4_1EN ,Domain 4_1 power supply control bit" "Off,On" bitfld.long 0x00 16. " PD4_0EN ,Domain 4_0 power supply control bit" "Off,On" newline bitfld.long 0x00 12. " PD3EN ,Domain 3 power supply control bit" "Off,On" bitfld.long 0x00 8. " PD2EN ,Domain 2 power supply control bit" "Off,On" endif rgroup.long 0x204++0x47 line.long 0x00 "STSCKSRER,STS Source Enable Register" bitfld.long 0x00 23. " SSCG3RDY ,SSCG PLL3 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 22. " SSCG2RDY ,SSCG PLL2 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 21. " SSCG1RDY ,SSCG PLL1 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 20. " SSCG0RDY ,SSCG PLL0 clock oscillation stabilization bit" "Not stable,Stable" newline bitfld.long 0x00 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 15. " PLL3RDY ,PLL3 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 14. " PLL2RDY ,PLL2 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 13. " PLL1RDY ,PLL1 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 12. " PLL0RDY ,PLL0 clock oscillation stabilization bit" "Not stable,Stable" newline bitfld.long 0x00 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " SOSCRDY ,Sub clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 6. " MOSCRDY ,Main clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 5. " SCROSCRDY ,Low-speed CR clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x00 4. " CROSCRDY ,High-speed CR clock oscillation stabilization bit" "Not stable,Stable" newline bitfld.long 0x00 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x04 "STSCKSELR,STS Clock Selection Register" bitfld.long 0x04 4.--6. " CDMCUCCM ,Clock domain MCUC clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Fixed to 'L'" bitfld.long 0x04 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Fixed to 'L'" line.long 0x08 "STSCKER,STS Clock Enable Register" bitfld.long 0x08 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x08 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled" line.long 0x0C "STSCKDIVR,STS Division Register" bitfld.long 0x0C 8.--11. " MCUCPDIV ,MCU config APB clock division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 0.--4. " MCUCHDIV ,MCU config AHB clock division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x10 "STSPLL0CNTR,STS PLL0 Control Register" bitfld.long 0x10 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x10 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplication rate setting bits" bitfld.long 0x10 8.--11. " PLL0DIVM ,PLL0 output clock M-division ratio setting bits" "2,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30" bitfld.long 0x10 0.--1. " PLL0DIVL ,PLL0 clock L-division ratio setting bits" "No division,/2,/4,/6" line.long 0x14 "STSPLL1CNTR,STS PLL1 Control Register" bitfld.long 0x14 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x14 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplication rate setting bits" bitfld.long 0x14 8.--11. " PLL1DIVM ,PLL1 output clock M-division ratio setting bits" "2,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30" bitfld.long 0x14 0.--1. " PLL1DIVL ,PLL1 clock L-division ratio setting bits" "No division,/2,/4,/6" line.long 0x18 "STSPLL2CNTR,STS PLL2 Control Register" bitfld.long 0x18 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x18 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplication rate setting bits" bitfld.long 0x18 8.--11. " PLL2DIVM ,PLL2 output clock M-division ratio setting bits" "2,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30" bitfld.long 0x18 0.--1. " PLL2DIVL ,PLL2 clock L-division ratio setting bits" "No division,/2,/4,/6" line.long 0x1C "STSPLL3CNTR,STS PLL3 Control Register" bitfld.long 0x1C 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x1C 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplication rate setting bits" bitfld.long 0x1C 8.--11. " PLL3DIVM ,PLL3 output clock M-division ratio setting bits" "2,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30" bitfld.long 0x1C 0.--1. " PLL3DIVL ,PLL3 clock L-division ratio setting bits" "No division,/2,/4,/6" line.long 0x20 "STSSSCG0CNTR0,STS SSCG0 Control Register 0" bitfld.long 0x20 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x20 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x20 8.--11. " SSCG0DIVM ,SSCG PLL0 clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x20 0.--1. " SSCG0DIVL ,SSCG PLL0 input division setting bits" "No division,/2,/4,/6" line.long 0x24 "STSSSCG0CNTR1,STS SSCG0 control register 1" bitfld.long 0x24 24. " SSCG0SSEN ,SSCG PLL0 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x24 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x24 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x24 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" line.long 0x28 "STSSSCG1CNTR0,STS SSCG1 Control Register 0" bitfld.long 0x28 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x28 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x28 8.--11. " SSCG1DIVM ,SSCG PLL1 clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x28 0.--1. " SSCG1DIVL ,SSCG PLL1 input division setting bits" "No division,/2,/4,/6" line.long 0x2C "STSSSCG1CNTR1,STS SSCG1 control register 1" bitfld.long 0x2C 24. " SSCG1SSEN ,SSCG PLL1 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x2C 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x2C 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x2C 0.--9. 1. " SSCG1RATE ,SSCG PLL1 clock modulation ratio control bits" line.long 0x30 "STSSSCG2CNTR0,STS SSCG2 Control Register 0" bitfld.long 0x30 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x30 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x30 8.--11. " SSCG2DIVM ,SSCG PLL2 clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x30 0.--1. " SSCG2DIVL ,SSCG PLL2 input division setting bits" "No division,/2,/4,/6" line.long 0x34 "STSSSCG2CNTR1,STS SSCG2 control register 1" bitfld.long 0x34 24. " SSCG2SSEN ,SSCG PLL2 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x34 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x34 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x34 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" line.long 0x38 "STSSSCG3CNTR0,STS SSCG3 Control Register 0" bitfld.long 0x38 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main,High-speed" hexmask.long.byte 0x38 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x38 8.--11. " SSCG3DIVM ,SSCG PLL3 clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x38 0.--1. " SSCG3DIVL ,SSCG PLL3 input division setting bits" "No division,/2,/4,/6" line.long 0x3C "STSSSCG3CNTR1,STS SSCG3 control register 1" bitfld.long 0x3C 24. " SSCG3SSEN ,SSCG PLL3 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x3C 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x3C 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x3C 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" line.long 0x40 "STSLVDCFGR,STS Low-voltage Detection Setting Register" bitfld.long 0x40 31. " LVDL1R ,Internal Low-voltage detection operation status bit" "Stopped,Performed" bitfld.long 0x40 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x40 25.--27. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0.875,0.950,?..." else bitfld.long 0x40 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" textfld " " endif bitfld.long 0x40 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x40 23. " LVDL2R ,Extended internal low-voltage detection operation status bit" "Stopped,Performed" bitfld.long 0x40 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,interrupt" bitfld.long 0x40 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x40 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x40 15. " LVDH1R ,External low-voltage detection operation status bit" "Stopped,Performed" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x40 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,?..." bitfld.long 0x40 9.--11. " LVDH1V ,Extended internal low-voltage detection voltage setting bits" "2.70,2.80,3.60,3.80,4.00,4.20,2.50,2.60" else bitfld.long 0x40 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x40 9.--12. " LVDH1V ,External low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " endif bitfld.long 0x40 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x40 7. " LVDH2R ,Extended external low-voltage detection operation status bit" "Stopped,Performed" bitfld.long 0x40 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x40 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",2.80,3.60,3.80,4.00,4.20,?..." else bitfld.long 0x40 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textfld " " endif bitfld.long 0x40 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x44 "STSCSVCFGR,STS Clock Supervisor Setting Register" bitfld.long 0x44 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x44 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x44 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 2. " FCRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x44 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" sif (!cpuis("S6J33*")) rgroup.long 0x24C++0x3 line.long 0x00 "STSREGCFGR,APP Regulator Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" bitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bits" "1.20v,1.25v" else rgroup.long 0x24C++0x3 line.long 0x00 "STSREGCFGR,APP Regulator Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" endif sif cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x280++0x07 line.long 0x00 "SYSIDR,SYSIDR" line.long 0x04 "SYSPFIDR,SYSPFIDR" elif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") group.long 0x280++0x07 line.long 0x00 "SYSIDR,SYSIDR" line.long 0x04 "SYSPFIDR,SYSPFIDR" endif rgroup.long 0x288++0x03 "System Registers" line.long 0x00 "SYSSTSR,System Status Register" bitfld.long 0x00 7. " PSSSTS0 ,PSS profile update status bit" "Not updated,Updated" bitfld.long 0x00 6. " RUNSTS0 ,RUN profile update status bit" "Not updated,Updated" bitfld.long 0x00 5. " PSSDF0 ,PSS profile update completion flag bit" "Not updated,Updated" newline bitfld.long 0x00 4. " RUNDF0 ,RUN profile update completion (main status control)flag bit" "Not updated,Updated" bitfld.long 0x00 1. " CPUSTS0 ,CPU0 Device status bit" "Operation,WFI" bitfld.long 0x00 0. " DVSTS0 ,Device status bit" "PSS,RUN" group.long 0x28C++0x07 line.long 0x00 "SYSINTER,System Status Interrupt Enable Register" bitfld.long 0x00 4. " RUNDIE0 ,RUN profile update completion interrupt enable bit" "Disabled,Enabled" line.long 0x04 "SYSICLR,System Status Flag And Interrupt Clear Register" eventfld.long 0x04 5. " PSSDFCLR0 ,PSS profile update completion flag clear bit" "No effect,Clear" eventfld.long 0x04 4. " RUNDFCLR0 ,RUN profile update completion flag clear bit" "No effect,Clear" rgroup.long 0x294++0x07 line.long 0x00 "SYSERRIR0,System Interrupt Factor Register 0" bitfld.long 0x00 29. " LVDH2IF ,Extended external low-voltage detection interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " LVDH1IF ,External low-voltage detection interrupt" "No interrupt,Interrupt" bitfld.long 0x00 25. " LVDL2IF ,Extended internal low-voltage detection interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " LVDL1IF ,Internal low-voltage detection interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " SSCG3IF ,SSCG PLL3 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 18. " SSCG2IF ,SSCG PLL2 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 17. " SSCG1IF ,SSCG PLL1 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " SSCG0IF ,SSCG PLL0 abnormality detection error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " PLL3IF ,PLL3 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 10. " PLL2IF ,PLL2 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 9. " PLL1IF ,PLL1 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 8. " PLL0IF ,PLL0 abnormality detection error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " SOSCIF ,Sub oscillation abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 0. " MOSCIF ,Main oscillation abnormality detection error interrupt request bit" "No interrupt,Interrupt" line.long 0x04 "SYSERRIR1,System Error Interrupt Factor Register 1" bitfld.long 0x04 6. " PSSERRIF0 ,PSS profile error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 5. " RUNWKERRIF0 ,RUN profile (PSS recovery time) error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 4. " RUNERRIF0 ,RUN profile error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 3. " PSSENERRIF0 ,PSS profile update enable write error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x04 2. " PSSTRGCIF0 ,PSS trigger cancel interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 1. " RUNTRGERRIF ,RUN profile update enable write error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 0. " TRGERRIF ,Trigger error interrupt request bit" "No interrupt,Interrupt" wgroup.long 0x29C++0x07 line.long 0x00 "SYSERRICLR0,System Error Interrupt Factor Clear Register 0" bitfld.long 0x00 29. " LVDH2ICLR ,Extended external low-voltage detection interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 28. " LVDH1ICLR ,External external low-voltage detection interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 25. " LVDL2ICLR ,Extended internal low-voltage detection interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 24. " LVDL1ICLR ,Internal low-voltage detection interrupt factor clear bit" "No effect,Clear" newline bitfld.long 0x00 19. " SSCG3ICLR ,SSCG PLL3 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 18. " SSCG2ICLR ,SSCG PLL2 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 17. " SSCG1ICLR ,SSCG PLL1 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 16. " SSCG0ICLR ,SSCG PLL0 abnormality detection error interrupt factor clear bit" "No effect,Clear" newline bitfld.long 0x00 11. " PLL3ICLR ,PLL3 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 10. " PLL2ICLR ,PLL2 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 9. " PLL1ICLR ,PLL1 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 8. " PLL0ICLR ,PLL0 abnormality detection error interrupt factor clear bit" "No effect,Clear" newline sif !cpuis("S6J336*")&&!cpuis("S6J337*") bitfld.long 0x00 3. " SOAICLR ,Sub oscillation abnormal monitor detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 2. " MOAICLR ,Main oscillation abnormal monitor detection error interrupt factor clear" "No effect,Clear" endif newline bitfld.long 0x00 1. " SOSCICLR ,Sub oscillation abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 0. " MOSCICLR ,Main oscillation abnormality detection error interrupt detection error interrupt factor clear bit" "No effect,Clear" line.long 0x04 "SYSERRICLR1,System Error Interrupt Factor Clear Register 1" bitfld.long 0x04 6. " PSSERRICLR0 ,PSS profile error interrupt request bit" "No effect,Clear" bitfld.long 0x04 5. " RUNWKERRICLR0 ,RUN profile (PSS recovery time) error interrupt request bit" "No effect,Clear" bitfld.long 0x04 4. " RUNERRICLR0 ,Run profile error interrupt request bit" "No effect,Clear" bitfld.long 0x04 3. " PSSENERRICLR0 ,PSS profile update enable write error interrupt request bit" "No effect,Clear" newline bitfld.long 0x04 2. " PSSTRGCICLR0 ,PSS trigger cancel interrupt request bit" "No effect,Clear" bitfld.long 0x04 1. " RUNTRGERRICLR ,RUN profile update enable write error interrupt request bit" "No effect,Clear" bitfld.long 0x04 0. " TRGERRICLR ,Trigger error interrupt request bit" "No effect,Clear" rgroup.long 0x2A4++0x07 line.long 0x00 "SYSPROSTSR,Profile Status Register" bitfld.long 0x00 2. " PSSPSTS ,PSS profile setting status bit" "No error,Error" bitfld.long 0x00 1. " RUNWKPSTS ,RUN profile (PSS recovery tine)setting status bit" "No error,Error" bitfld.long 0x00 0. " RUNPSTS ,RUN profile setting status bit" "No error,Error" line.long 0x04 "SYSRUNPEFR,RUN Profile Error Flag Register" bitfld.long 0x04 6. " PEF6 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 5. " PEF5 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 4. " PEF4 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 3. " PEF3 ,Profile error flag bit" "No error,Error" newline bitfld.long 0x04 2. " PEF2 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 1. " PEF1 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 0. " PEF0 ,Profile error flag bit" "No error,Error" group.long 0x2AC++0x03 line.long 0x00 "SYSPSSPEFR,PSS Profile Error Flag Register" bitfld.long 0x00 10. " PEF10 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 9. " PEF9 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 8. " PEF8 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 7. " PEF7 ,Profile error flag bit" "No error,Error" newline bitfld.long 0x00 6. " PEF6 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 5. " PEF5 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 4. " PEF4 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 3. " PEF3 ,Profile error flag bit" "No error,Error" newline bitfld.long 0x00 1. " PEF1 ,Profile error flag bit" "No error,Error" bitfld.long 0x00 0. " PEF0 ,Profile error flag bit" "No error,Error" base ad:0xB0600680 width 18. group.long 0x00++0x03 "Special Setting Register" line.long 0x00 "SPECFGR,System Special Setting Register" bitfld.long 0x00 31. " HOLDIO_PD6_1 ,Setting bit for power domain 6_1 HOLD data latch" "No retain,Retain" bitfld.long 0x00 30. " HOLDIO_PD6_0 ,Setting bit for power domain 6_0 HOLD data latch" "No retain,Retain" bitfld.long 0x00 29. " HOLDIO_PD5_3 ,Setting bit for power domain 5_3 HOLD data latch" "No retain,Retain" bitfld.long 0x00 28. " HOLDIO_PD5_2 ,Setting bit for power domain 5_2 HOLD data latch" "No retain,Retain" newline bitfld.long 0x00 27. " HOLDIO_PD5_1 ,Setting bit for power domain 5_1 HOLD data latch" "No retain,Retain" bitfld.long 0x00 26. " HOLDIO_PD5_0 ,Setting bit for power domain 5_0 HOLD data latch" "No retain,Retain" bitfld.long 0x00 24. " HOLDIO_PD2 ,Power domain 2 HOLD data latch setting bit" "No retain,Retain" bitfld.long 0x00 23. " PSSPADCTRL ,PPS-time port configuring bit" "Not performed,Performed" newline bitfld.long 0x00 22. " IO3RSTC ,I/O3V reset configuring bit" "No reset,Reset" bitfld.long 0x00 21. " IO35RSTC ,I/O5/3V reset configuring bit" "No reset,Reset" bitfld.long 0x00 9. " EXVRSTCNT ,Reset level configuring bit for external power suPLLy control" "Reset,No reset" bitfld.long 0x00 8. " BRAMSC ,Backup RAM standby setting bit" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " EX5VRSTCNT ,5/3.3v External power supply stabilization time setting bits 4MHz/8MHz" "1.0/0.5,2.0/1.0,3.0/1.5,4.0/2.0,5.0/2.5,6.0/3.0,7.0/3.5,8.0/4.0,9.0/4.5,10.0/5.0,12.0/6.0,14.0/7.0,16.0/8.0,18.0/9.0,20.0/10.0,30.0/15.0" bitfld.long 0x00 0.--3. " EX12VRSTCNT ,1.2 External power supply stabilization time setting bits" "1.0/0.5,2.0/1.0,3.0/1.5,4.0/2.0,5.0/2.5,6.0/3.0,7.0/3.5,8.0/4.0,9.0/4.5,10.0/5.0,12.0/6.0,14.0/7.0,16.0/8.0,18.0/9.0,20.0/10.0,30.0/15.0" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") group.long 0x08++0x0F line.long 0x00 "SPESPSWCFGR0,SPESPSWCFGR0" line.long 0x04 "SPESPSWCFGR1,SPESPSWCFGR1" line.long 0x08 "SPEWPSWCFGR0,SPEWPSWCFGR0" line.long 0x0C "SPEWPSWCFGR1,SPEWPSWCFGR1" endif rgroup.long 0x80++0x03 "Debug Registers" line.long 0x00 "JTAGDETECT,JTAG Detection Register" bitfld.long 0x00 0. " DBGCON ,Debugger connection status bit" "Not connected,Connected" group.long 0x84++0x07 line.long 0x00 "JTAGCNFG,JTAG Setting Register" bitfld.long 0x00 0. " DBGDONE ,Debugger status bit" "Connected,Not connected" line.long 0x04 "JTAGWAKEUP,JTAG Recovery Register" bitfld.long 0x04 0. " DBGWKEN ,Debugger wakeup enable bit" "Disabled,Enabled" width 0x0B tree.end tree "MCU Config Group" base ad:0xB0688800 width 8. rgroup.long 0x00++0x0B line.long 0x00 "IRSR0,MCU Config Interrupt Request Status Register 0" bitfld.long 0x00 24. " IRQ_PW ,Partial wakeup interrupt " "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQ_SCT_SUB ,Sub source clock timer interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQ_SCT_MAIN ,Main source clock timer interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQ_SCT_SCR ,Low-speed source clock timer interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " IRQ_SCT_CR ,High-speed source clock timer interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQ_RTC ,RTC 0.5 seconds interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQ_SCU ,RUN profile update complete interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQ_HWDG ,Hardware watchdog timer advance warning interrupt status" "No interrupt,Interrupt" newline sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 4. " NMI_WAKE ,NMI_WAKE" "0,1" newline endif bitfld.long 0x00 3. " NMI_EXTINT ,NMI detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " NMI_HWDG ,Hardware watchdog timer detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 1. " NMI_SCU ,Profile error detection interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " NMI_LVD ,Low power detection interrupt status" "No interrupt,Interrupt" line.long 0x04 "IRSR1,MCU Config Interrupt Request Status Register 1" sif !cpuis("S6J336*")&&!cpuis("S6J337*") bitfld.long 0x04 31. " IRQ_EXTINT_[31] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 30. " [30] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 29. " [29] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 28. " [28] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " [27] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 26. " [26] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 25. " [25] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 24. " [24] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 23. " [23] ,External interrupt detection status" "No interrupt,Interrupt" else bitfld.long 0x04 23. " IRQ_EXTINT_[23] ,External interrupt detection status" "No interrupt,Interrupt" endif bitfld.long 0x04 22. " [22] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 21. " [21] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 20. " [20] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 19. " [19] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 18. " [18] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 17. " [17] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 16. " [16] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 15. " [15] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 14. " [14] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 13. " [13] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 12. " [12] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 11. " [11] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 10. " [10] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 9. " [9] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 8. " [8] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 7. " [7] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 6. " [6] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 5. " [5] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 4. " [4] ,External interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 3. " [3] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 2. " [2] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 1. " [1] ,External interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x04 0. " [0] ,External interrupt detection status" "No interrupt,Interrupt" line.long 0x08 "IRSR2,MCU Config Interrupt Request Register 2" bitfld.long 0x08 18. " IRQ_RLT2 ,Reload timer ch2 interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 17. " IRQ_RLT1 ,Reload timer ch1 interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 16. " IRQ_RLT0 ,Reload timer ch0 interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 9. " IRQ_CRCAL ,CR calibration complete interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x08 8. " IRQ_EICU ,EICU complete interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 4. " IRQ_RAMIC ,BackUP-RAM initialization end interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 3. " IRQ_RAMTE ,BackUP-RAM diagnosis error interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 2. " IRQ_RAMTC ,BackUP-RAM diagnosis end interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x08 1. " IRQ_RAMSE ,BackUP-RAM single-bit error interrupt status" "No interrupt,Interrupt" newline sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") bitfld.long 0x08 0. " NMI_RAMDE ,BackUP-RAM double-bit error interrupt status" "No interrupt,Interrupt" newline else bitfld.long 0x08 0. " IRQ_RAMDE ,BackUP-RAM double-bit error interrupt status" "No interrupt,Interrupt" endif sif (!cpuis("S6J311?JAA"))&&(!cpuis("S6J311?HAA"))&&(!cpuis("S6J312?HAA")) rgroup.long 0x0C++0x07 line.long 0x00 "IRSR3,MCU Config Interrupt Request Status Register 3" bitfld.long 0x00 30. " IRQ_MCAN2_INT1 ,CAN-FD ch2 interrupt 1 status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQ_MCAN1_INT1 ,CAN-FD ch1 interrupt 1 status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQ_MCAN0_INT1 ,CAN-FD ch0 interrupt 1 status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQ_MCAN2_INT0 ,CAN-FD ch2 interrupt 0 status" "No interrupt,Interrupt" newline bitfld.long 0x00 25. " IRQ_MCAN1_INT0 ,CAN-FD ch1 interrupt 0 status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQ_MCAN0_INT0 ,CAN-FD ch0 interrupt 0 status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQ_MCAN2_SE ,CAN-FB ch2 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQ_MCAN1_SE ,CAN-FB ch1 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 20. " IRQ_MCAN0_SE ,CAN-FD ch0 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt" newline sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 18. " IRQ_MCAN2_DE ,CAN-FD ch2 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQ_MCAN1_DE ,CAN-FD ch1 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQ_MCAN0_DE ,CAN-FD ch0 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" newline else bitfld.long 0x00 18. " NMI_MCAN2_DE ,CAN-FD ch2 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 17. " NMI_MCAN1_DE ,CAN-FD ch1 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 16. " NMI_MCAN0_DE ,CAN-FD ch0 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" newline endif bitfld.long 0x00 10. " IRQ_MFS2_SIRQ ,MFS ch2 sync field detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQ_MFS1_SIRQ ,MFS ch1 sync field detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQ_MFS0_SIRQ ,MFS ch0 sync field detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQ_MFS2_RIRQ ,MFS ch2 reception interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " IRQ_MFS1_RIRQ ,MFS ch1 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQ_MFS0_RIRQ ,MFS ch0 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQ_MFS2_TIRQ ,MFS ch2 transmission interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQ_MFS1_TIRQ ,MFS ch1 transmission interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " IRQ_MFS0_TIRQ ,MFS ch0 transmission interrupt status" "No interrupt,Interrupt" line.long 0x04 "IRSR4,MCU Config Interrupt Request Status Register 4" bitfld.long 0x04 6. " IRQ_MFS2_RIRQ ,MFS ch2 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 5. " IRQ_MFS1_RIRQ ,MFS ch1 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 4. " IRQ_MFS0_RIRQ ,MFS ch0 reception interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x04 2. " IRQ_MFS2_TIRQ ,MFS ch2 transmission interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 1. " IRQ_MFS1_TIRQ ,MFS ch1 transmission interrupt status" "No interrupt,Interrupt" bitfld.long 0x04 0. " IRQ_MFS0_TIRQ ,MFS ch0 transmission interrupt status" "No interrupt,Interrupt" endif width 0x0B tree.end tree "SYSC 1" base ad:0xB0300000 width 18. group.long 0x00++0x03 "Protection Register" line.long 0x00 "PROTKEYR,Protection Key Setting Register" group.long 0x80++0x0B "RUN Profile Registers" line.long 0x00 "SYSC1_RUNCKSELR0,RUN Clock Selection Register 0" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Fixed at 'L'" line.long 0x04 "SYSC1_RUNCKSELR1,RUN Clock Selection Register 1" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'" newline bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'" line.long 0x08 "SYSC1_RUNCKSELR2,RUN Clock Selection Register 2" sif cpuis("S6J311*")||cpuis("S6J312?HAA") bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed at'L'" newline else bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,PPL1,Fixed at'L'" newline endif bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'" sif cpuis("S6J311*")||cpuis("S6J312?HAA")||cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") group.long 0x8C++0x03 line.long 0x00 "SYSC1_RUNCKER0,RUN Clock Source Enable Register 0" rbitfld.long 0x00 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x00 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x00 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" elif cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x8C++0x03 line.long 0x00 "SYSC1_RUNCKER0,RUN Clock Source Enable Register 0" bitfld.long 0x00 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" ",Enabled" bitfld.long 0x00 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" ",Enabled" bitfld.long 0x00 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" ",Enabled" bitfld.long 0x00 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 23. " ENCLKLCP ,LCP clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" ",Enabled" bitfld.long 0x00 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 14. " ENCLKSYSC1 ,ENCLKSTSC1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" ",Enabled" bitfld.long 0x00 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" ",Enabled" bitfld.long 0x00 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" ",Enabled" bitfld.long 0x00 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" ",Enabled" bitfld.long 0x00 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" ",Enabled" else rgroup.long 0x8C++0x03 line.long 0x00 "SYSC1_RUNCKER0,RUN Clock Source Enable Register 0" bitfld.long 0x00 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 14. " ENCLKSYSC1 ,ENCLKSTSC1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" endif group.long 0x90++0x17 line.long 0x00 "SYSC1_RUNCKER1,RUN Clock Source Enable Register 1" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x00 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" ",Enabled" else bitfld.long 0x00 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x00 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" endif newline bitfld.long 0x00 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x04 "SYSC1_RUNCKER2,RUN Source Enable Register 2" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x04 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x04 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x04 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x04 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x04 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" ",Enabled" bitfld.long 0x04 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x04 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x04 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x04 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x04 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" ",Enabled" else bitfld.long 0x04 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" endif line.long 0x08 "SYSC1_RUNCKDIVR0,RUN Clock Divider Register 0" bitfld.long 0x08 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x08 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..." bitfld.long 0x08 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x08 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x08 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x0C "SYSC1_RUNCKDIVR1,RUN Clock Divider Register 1" bitfld.long 0x0C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x0C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 0.--2. " EXTBUSDIV ,EXTBUT clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x10 "SYSC1_RUNCKDIVR2,RUN Clock Divider Register 2" bitfld.long 0x10 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x10 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x14 "SYSC1_RUNCKDIVR3,RUN Clock Divider Register 3" bitfld.long 0x14 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x14 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x14 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x14 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA") group.long 0xA8++0x03 line.long 0x00 "SYSC1_RUNCKDIVR4,RUN Clock Divider Register 4" bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA") group.long 0xAC++0x13 line.long 0x00 "SYSC1_RUNCKDIVR5,RUN Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x04 "SYSC1_RUNCKDIVR6,RUN Clock Divider Register 6" bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x08 "SYSC1_RUNCKDIVR7,RUN Clock Divider Register 7" bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x0C "SYSC1_RUNCKDIVR8,RUN Clock Divider Register 8" bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x10 "SYSC1_RUNCKDIVR9,RUN Clock Divider Register 9" bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif sif (cpuis("S6J33*")) group.long 0xFC++0x03 line.long 0x00 "SYSC1_RUNENR,RUN Profile Update Enable Register" hexmask.long.byte 0x00 0.--7. 1. " RUNEN1 ,RUN profile update enable" else group.byte 0xFC++0x00 line.byte 0x00 "SYSC1_RUNENR,RUN Profile Update Enable Register" endif group.long 0x100++0x27 "PSS Profile Registers" line.long 0x00 "SYSC1_PSSCKSELR0,PSS Clock Selection Register 0" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,PPL1,PPL2,PPL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed to 'L'" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0 clock,,Fixed to 'L'" line.long 0x04 "SYSC1_PSSCKSELR1,PSS Clock Selection Register 1" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" newline bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" line.long 0x08 "SYSC1_PSSCKSELR2,PSS Clock Selection Register 2" sif cpuis("S6J311*")||cpuis("S6J312?HAA") bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,,Fixed to'L'" newline else bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Fixed to'L'" newline endif bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" line.long 0x0C "SYSC1_PSSCKER0,PSS Clock Source Enable Register 0" bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 6. " ENCLKTRC ,ECLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled," else bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" endif line.long 0x10 "SYSC1_PSSCKER1,PSS Clock Source Enable Register 1" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" ",Enabled" else bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" ",Enabled" endif newline bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "SYSC1_PSSCKER2,PSS Clock Source Enable Register 2" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" ",Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" ",Enabled" bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" ",Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" ",Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" ",Enabled" bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" ",Enabled" newline bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" ",Enabled" else bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" endif line.long 0x18 "SYSC1_PSSCKDIVR0,PSS Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" else bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..." endif bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "SYSC1_PSSCKDIVR1,PSS Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "SYSC1_PSSCKDIVR2,PSS Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "SYSC1_PSSCKDIVR3,PSS Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA") group.long 0x128++0x03 line.long 0x00 "SYSC1_PSSCKDIVR4,PSS Clock Divider Register 4" bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA") group.long 0x12C++0x13 line.long 0x00 "SYSC1_PSSCKDIVR5,PSS Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x04 "SYSC1_PSSCKDIVR6,PSS Clock Divider Register 6" bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x08 "SYSC1_PSSCKDIVR7,PSS Clock Divider Register 7" bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x0C "SYSC1_PSSCKDIVR8,PSS Clock Divider Register 8" bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x10 "SYSC1_PSSCKDIVR9,PSS Clock Divider Register 9" bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif sif (cpuis("S6J33*")) group.long 0x17C++0x03 line.long 0x00 "SYSC1_PSSENR,PSS Profile Update Enable Register" hexmask.long.byte 0x00 0.--7. 1. " PSSEN1 ,PSS profile update enable bits" else group.byte 0x17C++0x00 line.byte 0x00 "SYSC1_PSSENR,PSS Profile Update Enable Register" endif rgroup.long 0x180++0x27 "APP Profile Registers" line.long 0x00 "SYSC1_APPCKSELR0,APP Clock Selection Register 0" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PLL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PLL0" newline bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PLL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PLL0" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,SSCG0,,Fixed to 'L'" line.long 0x04 "SYSC1_APPCKSELR1,APP Clock Selection Register 1" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" newline bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" line.long 0x08 "SYSC1_APPCKSELR2,APP Clock Selection Register 2" sif cpuis("S6J311*")||cpuis("S6J312?HAA") bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,SSCG0,,Fixed to'L'" newline else bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,SSCG0,PPL1,Fixed to'L'" newline endif bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 section bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" line.long 0x0C "SYSC1_APPCKER0,APP clock source enable register 0" bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPMB2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 6. " ENCLKTRC ,CNCLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 4. " ENCLKATB ,CNCLKATB clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "SYSC1_APPCKER1,APP clock source enable register 1" bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "SYSC1_APPCKER2,APP clock source enable register 2" bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 3. " ENCLKCD4B0 ,CD4B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" line.long 0x18 "SYSC1_APPCKDIVR0,APP Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..." bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "SYSC1_APPCKDIVR1,APP Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "SYSC1_APPCKDIVR2,APP Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "SYSC1_APPCKDIVR3,APP Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA") rgroup.long 0x1A8++0x03 line.long 0x00 "SYSC1_APPCKDIVR4,APP Clock Divider Register 4" bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA") rgroup.long 0x1AC++0x13 line.long 0x00 "SYSC1_APPCKDIVR5,APP Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CB1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x04 "SYSC1_APPCKDIVR6,APP Clock Divider Register 6" bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x08 "SYSC1_APPCKDIVR7,APP Clock Divider Register 7" bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x0C "SYSC1_APPCKDIVR8,APP Clock Divider Register 8" bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x10 "SYSC1_APPCKDIVR9,APP Clock Divider Register 9" bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif rgroup.long 0x200++0x27 "STS Profile registers" line.long 0x00 "SYSC1_STSCKSELR0,STS Clock Selection Register 0" bitfld.long 0x00 28.--31. " HSSPICM ,HSSPI clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x00 21. " LAPP1ACM ,LAPP1A clock selection status bit" "CD0,PLL0" newline bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PLL0" bitfld.long 0x00 17. " LAPP0ACM ,LAPP0A clock selection status bit" "CD0,PLL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PLL0" newline bitfld.long 0x00 13. " LCP1ACM ,LCP1A clock selection status bit" "CD0,PLL0" bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PLL0" bitfld.long 0x00 9. " LCP0ACM ,LCP0A clock selection status bit" "CD0,PLL0" newline bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PLL0" bitfld.long 0x00 4.--6. " CD0CM ,Clock domain 0 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'" line.long 0x04 "SYSC1_STSCKSELR1,STS Clock Selection Register 1" bitfld.long 0x04 28.--31. " CD4CM ,Domain 4 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 24.--27. " CD4CSL ,Domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 20.--23. " CD3CM ,Domain 3 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" newline bitfld.long 0x04 16.--19. " CD3CSL ,Domain 3 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 12.--15. " CD2CM ,Domain 2 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 8.--11. " CD2CSL ,Domain 2 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" newline bitfld.long 0x04 4.--7. " CD1CM ,Domain 1 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" bitfld.long 0x04 0.--3. " CD1CSL ,Domain 1 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" line.long 0x08 "SYSC1_STSCKSELR2,STS Clock Selection Register 2" sif (cpu()=="S6J311*")||cpuis("S6J312?HAA") bitfld.long 0x08 12.--14. " TRCCM ,TRC clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'" newline else bitfld.long 0x08 12.--14. " TRCCM ,TRC clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,PPL1,Fixed to 'L'" newline endif bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'" bitfld.long 0x08 4.--7. " CD5CM ,Domain 5 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" newline bitfld.long 0x08 0.--3. " CD5CSL ,Domain 5 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'" line.long 0x0C "SYSC1_STSCKER0,STS Clock Source Enable Register 0" bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "SYSC1_STSCKER1,STS Clock Source Enable Register 1" bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "SYSC1_STSCKER2,STS Clock Source Enable Register 2" bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 3. " ENCLKCD4B0 ,CD4B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" line.long 0x18 "SYSC1_STSCKDIVR0,STS Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock frequency divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..." bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "SYSC1_STSCKDIVR1,STS Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "SYSC1_STSCKDIVR2,STS Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "SYSC1_STSCKDIVR3,STS Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA") rgroup.long 0x228++0x03 line.long 0x00 "SYSC1_STSCKDIVR4,STS Clock Divider Register 4" bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA") rgroup.long 0x22C++0x13 line.long 0x00 "SYSC1_STSCKDIVR5,STS Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x04 "SYSC1_STSCKDIVR6,STS Clock Divider Register 6" bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x08 "SYSC1_STSCKDIVR7,STS Clock Divider Register 7" bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x0C "SYSC1_STSCKDIVR8,STS Clock Divider Register 8" bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x10 "SYSC1_STSCKDIVR9,STS Clock Divider Register 9" bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" endif width 0x0B tree.end tree.end tree "CLOCK SUPERVISOR" base ad:0xB0600300 width 14. group.long 0x00++0x07 line.long 0x00 "CSVMOCFGR0,Main Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVMOCFGR1,Main Clock Supervisor Setting Register 1" sif (!cpuis("S6J311*")&&!cpuis("S6J312?HAA")) bitfld.long 0x04 24. " REFCLKSEL ,Reference lock selection bits" "Slow,Fast" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain" newline hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" newline else bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" endif sif !cpuis("S6J311*")&&!cpuis("S6J312?HAA") group.long 0x08++0x07 line.long 0x00 "CSVSOCFGR0,Sub Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSOCFGR1,Sub clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" endif group.long 0x10++0x07 line.long 0x00 "CSVPLL0CFGR0,PLL0 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL0CFGR1,PLL0 clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain,Domain" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" sif !cpuis("S6J311*")&&!cpuis("S6J312?HAA") group.long 0x18++0x07 line.long 0x00 "CSVPLL1CFGR0,PLL1 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL1CFGR1,PLL1 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x20++0x07 line.long 0x00 "CSVPLL2CFGR0,PLL2 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL2CFGR1,PLL2 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x28++0x07 line.long 0x00 "CSVPLL3CFGR0,PLL3 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL3CFGR1,PLL3 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" endif group.long 0x30++0x07 line.long 0x00 "CSVSP0CFGR0,SSCG PLL0 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP0CFGR1,SSCG PLL0 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain,Domain" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" sif !cpuis("S6J311*")&&!cpuis("S6J312?HAA") group.long 0x38++0x07 line.long 0x00 "CSVSP1CFGR0,SSCG PLL1 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP1CFGR1,SSCG PLL1 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x40++0x07 line.long 0x00 "CSVSP2CFGR0,SSCG PLL2 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP2CFGR1,SSCG PLL2 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x48++0x07 line.long 0x00 "CSVSP3CFGR0,SSCG PLL3 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP3CFGR1,SSCG PLL3 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" endif sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&!cpuis("S6J312?HAA") group.long 0x50++0x07 line.long 0x00 "CSVFCRCFGR,Fast CR Clock Supervisor Setting Register" bitfld.long 0x00 0.--2. " REFCLKDIV ,Reference clock division setting bits" "/4,/8,/16,/32,/64,/128,/128,/128" line.long 0x04 "CSVSCRCFGR,Slow CR Clock Supervisor Setting Register" bitfld.long 0x04 0.--2. " REFCLKDIV ,Reference clock division setting bits" "/4,/8,/16,/32,/64,/128,/128,/128" endif sif (!cpuis("S6J33*")) group.long 0x60++0x03 line.long 0x00 "CSVOUTER,Clock Supervisor Output Enable Register" bitfld.long 0x00 0. " OUTEN ,Clock supervisor output enable bit" "Disabled,Enabled" endif group.long 0x64++0x03 line.long 0x00 "CSVTESTR,Clock Supervisor Test Register" sif (cpu()!="S6J311*")&&!cpuis("S6J312?HAA") bitfld.long 0x00 25. " SCRCLKGATE ,SCR CR clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 24. " FCRCLKGATE ,FCR CR clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 19. " SP3CLKGATE ,SSCG PLL3 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 18. " SP2CLKGATE ,SSCG PLL2 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 17. " SP1CLKGATE ,SSCG PLL1 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 16. " SP0CLKGATE ,SSCG PLL0 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 11. " PLL3CLKGATE ,PLL3 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 10. " PLL2CLKGATE ,PLL2 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 9. " PLL1CLKGATE ,PLL1 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 8. " PLL0CLKGATE ,PLL0 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 3. " SO1CLKGATE ,Sub clock 1 supervisor test bit" "Normal,Gating" bitfld.long 0x00 2. " MO1CLKGATE ,Main clock 1 supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 1. " SO0CLKGATE ,Sub clock 0 supervisor test bit" "Normal,Gating" bitfld.long 0x00 0. " MO0CLKGATE ,Main clock 0 supervisor test bit" "Normal,Gating" newline else bitfld.long 0x00 19. " SP3CLKGATE ,SSCG PLL3 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 18. " SP2CLKGATE ,SSCG PLL2 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 17. " SP1CLKGATE ,SSCG PLL1 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 16. " SP0CLKGATE ,SSCG PLL0 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 11. " PLL3CLKGATE ,PLL3 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 10. " PLL2CLKGATE ,PLL2 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 9. " PLL1CLKGATE ,PLL1 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 8. " PLL0CLKGATE ,PLL0 clock supervisor test bit" "Normal,Gating" bitfld.long 0x00 3. " SO1CLKGATE ,Sub clock 1 supervisor test bit" "Normal,Gating" newline bitfld.long 0x00 2. " MO1CLKGATE ,Main clock 1 supervisor test bit" "Normal,Gating" bitfld.long 0x00 1. " SO0CLKGATE ,Sub clock 0 supervisor test bit" "Normal,Gating" bitfld.long 0x00 0. " MO0CLKGATE ,Main clock 0 supervisor test bit" "Normal,Gating" endif width 0x0B tree.end tree "SOURCE CLOCK TIMER" base ad:0xB0600400 width 12. group.long 0x00++0x0F "High-speed CR Clock Timer Registers" line.long 0x00 "FCRCTTRGR,High-speed CR Clock Timer Trigger Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "FCRCTCNTR,High-speed CR Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous" line.long 0x08 "FCRCTCPR,High-speed CR Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" line.long 0x0C "FCRCTSTR,High-speed CR Clock Timer Status Register" rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress" rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating" setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.long 0x80++0x0f "Low-speed CR Clock Timer Register" line.long 0x00 "SCRCTTRGR,Low-speed CR Clock Timer Trigger Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "SCRCTCNTR,Low-Speed CR Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous" line.long 0x08 "SCRCTCPR,Low-speed CR Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" line.long 0x0C "SCRCTSTR,Low-speed CR Clock Timer Status Register" rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress" rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating" setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.long 0x100++0x0F "Main Clock Timer Register" line.long 0x00 "MOCTTRGR,Main Clock Timer Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Chang/Start" line.long 0x04 "MOCTCNTR,Main Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous" line.long 0x08 "MOCTCPR,Main Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" line.long 0x0C "MOCTSTR,Main Clock Timer Status Register" rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress" rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating" setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA") group.long 0x180++0x0F "Sub Clock Timer Registers" line.long 0x00 "SOCTTRGR,Sub Clock Timer Trigger Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "SOCTCNTR,Sub Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous" line.long 0x08 "SOCTCPR,Sub Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" line.long 0x0C "SOCTSTR,Sub Clock Timer Status Register" rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress" rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating" setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" endif width 0x0B tree.end tree "RTC (REAL TIME CLOCK)" base ad:0xB0618000 width 14. if ((per.l(ad:0xB0618000)&0x100)==0x00) group.long 0x00++0x03 line.long 0x00 "WTCR,Timer Control Register" bitfld.long 0x00 15. " UPCAL ,Update calibration period counter" "Completed,Update" bitfld.long 0x00 12.--14. " SCAL ,Scale calibrated value" "No change,*2,*4,*8,*16,?..." bitfld.long 0x00 11. " CCKSEL ,Clock select for calibration" "Sub,Slow RC" bitfld.long 0x00 10. " ENUP ,Enable/Disable calibration value update" "Disabled,Enabled" newline bitfld.long 0x00 9. " MTRG ,Manual trigger for calibration" "No,Yes" bitfld.long 0x00 8. " ACAL ,Automatic calibration" "Disabled,Enabled" bitfld.long 0x00 4.--5. " RCKSEL ,Clock select for RTC" "Main,Sub,Slow RC,?..." bitfld.long 0x00 3. " CSM ,Clock switching mode" "Precise,Immediate" newline bitfld.long 0x00 2. " UPDT ,Update" "Completed,Update" bitfld.long 0x00 1. " OE ,Output enable" "General purpose,Sub-second counter" bitfld.long 0x00 0. " ST ,Start" "Stopped,Started" else group.long 0x00++0x03 line.long 0x00 "WTCR,Timer Control Register" bitfld.long 0x00 15. " UPCAL ,Update calibration period counter" "Completed,Update" bitfld.long 0x00 12.--14. " SCAL ,Scale calibrated value" "No change,*2,*4,*8,*16,?..." bitfld.long 0x00 11. " CCKSEL ,Clock select for calibration" "Sub,Slow RC" newline bitfld.long 0x00 8. " ACAL ,Automatic calibration" "Disabled,Enabled" bitfld.long 0x00 4.--5. " RCKSEL ,Clock select for RTC" "Main,Sub,Slow RC,?..." bitfld.long 0x00 3. " CSM ,Clock switching mode" "Precise,Immediate" newline bitfld.long 0x00 2. " UPDT ,Update" "Completed,Update" bitfld.long 0x00 1. " OE ,Output enable" "General purpose,Sub-second counter" bitfld.long 0x00 0. " ST ,Start" "Stopped,Started" endif sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA")) group.long 0x04++0x03 line.long 0x00 "WTSR,Timer Status Register" rbitfld.long 0x00 8. " RUNC ,Run calibration" "Inactive,In progress" rbitfld.long 0x00 7. " CLK_STS ,Clock switching status" "Inactive,In progress" bitfld.long 0x00 1. " CSF ,Clock switched flag" "Not switched,Switched" rbitfld.long 0x00 0. " RUN ,RUN" "Inactive,Active" else rgroup.long 0x04++0x03 line.long 0x00 "WTSR,Timer Status Register" bitfld.long 0x00 8. " RUNC ,Run calibration" "Inactive,In progress" bitfld.long 0x00 1. " CSF ,Clock switched flag" "Not switched,Switched" bitfld.long 0x00 0. " RUN ,RUN" "Inactive,Active" endif group.long 0x08++0x03 line.long 0x00 "WINS_SET/CLR,Interrupt Status Register" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CALD_SET/CLR ,Calibration done" "In progress,Done" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CFD_SET/CLR ,Calibration failure detection" "No failure,Failure" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DAY_SET/CLR ,Day flag" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " HOUR_SET/CLR ,Hour flag" "No interrupt,Interrupt" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " MIN_SET/CLR ,Minute flag" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SEC_SET/CLR ,Second flag" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SUBSEC_SET/CLR ,Sub-second flag" "No interrupt,Interrupt" group.long 0x14++0x0B line.long 0x00 "WTBR,Sub-second Register" hexmask.long.tbyte 0x00 0.--23. 1. " WTBR ,Sub-second value" line.long 0x04 "WRT,Real Time Register" bitfld.long 0x04 16.--20. " WTHR ,Hour register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." bitfld.long 0x04 8.--13. " WTMR ,Minute register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..." bitfld.long 0x04 0.--5. " WTSR ,Second register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..." line.long 0x08 "RTR1,Real Time Clock Real Time Register 1" hexmask.long.word 0x08 0.--15. 1. " WTDR ,Date bits" rgroup.long 0x20++0x03 line.long 0x00 "CNTCAL,Calibration Clock Counter Register" hexmask.long.tbyte 0x00 0.--23. 1. " CNTCAL ,Calibration clock counter value" group.long 0x24++0x0B line.long 0x00 "CNTPCAL,Calibration Clock Period Counter Register" hexmask.long.word 0x00 0.--10. 1. " CNTPCAL ,Calibration clock period register" line.long 0x04 "DURMW,Calibration Duration Register" hexmask.long.tbyte 0x04 0.--23. 1. " DURMW ,Calibration duration value" line.long 0x08 "CALTRG,Calibration Trigger Register" hexmask.long.word 0x08 0.--11. 1. " CALTRG ,Calibration trigger counter value" sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA")) group.long 0x30++0x03 line.long 0x00 "DEBUG,Debug Register" bitfld.long 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" endif sif !cpuis("S6J312?HAA")&&!cpuis("S6J311?HAA") group.long 0x34++0x03 line.long 0x00 "PWUTRGCR,Partial Wake Up Trigger Control Register" hexmask.long.tbyte 0x00 8.--25. 1. " C8MRL ,Reload value setting bit of 8ms counter" bitfld.long 0x00 4. " MD ,Reload value setting bit to 8ms counter" "Manual operation,Sub-second" bitfld.long 0x00 0.--2. " SEL ,Reload value setting bit to trigger counter" "8ms,16ms,24ms,32ms,40ms,48ms,56ms,64sms" rgroup.long 0x38++0x03 line.long 0x00 "PWUTRGSR,Partial Wake Up Trigger Status Register" bitfld.long 0x00 0. " BUSY ,Busy status" "Idle,Busy" endif width 0x0B tree.end tree "CR CALIBRATION" base ad:0xB0688400 width 8. group.word 0x00++0x03 line.word 0x00 "CUCR1,Correction Unit Register 1" bitfld.word 0x00 4. " STRT ,Correction start" "Aborted,Started" setclrfld.word 0x00 1. 0x00 1. 0x08 1. " INT_SET/CLR ,Interrupt" "No interrupt,Interrupt" bitfld.word 0x00 0. " INTEN ,Enabling interrupts" "Disabled,Enabled" line.word 0x02 "CUTD1,CR Clock Timer Data Register 1" rgroup.long 0x04++0x03 line.long 0x00 "CUTR1,Main Oscillation Timer Data Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer data" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "BURIF (BACKUP RAM INTERFACE)" base ad:0xB0680000 width 11. wgroup.long 0x0++0x3 line.long 0x00 "UNLOCK,Unlock register" rgroup.long 0x4++0x3 line.long 0x00 "STATUS,Status register" sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA")) bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" bitfld.long 0x00 2. " TM_ESKPG ,ECC generation function disable status bit" "Not allowed,Allowed" bitfld.long 0x00 1. " TM_ESKPC ,ECC test function disable status bit" "Not allowed,Allowed" textline " " bitfld.long 0x00 0. " TM_EEACC ,ECC area access enable status bit" "Not allowed,Allowed" textline " " else bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" endif rgroup.word 0x8++0x1 line.word 0x00 "DEEAR,Double-bit ECC error address register" hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Double-bit error occurrence address bits" rgroup.word 0xA++0x1 line.word 0x00 "SEEAR,Single-bit ECC error address register" hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Single-bit error occurrence address bits" if (((per.l(ad:0xB0680000+0x04))&0x100)==0x00) group.word 0xC++0x1 line.word 0x00 "EFEAR,ECC pseudo-error generation address register" hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Single-bit error occurrence address bits" group.byte 0xF++0x0 line.byte 0x00 "EECSR,ECC error control register" bitfld.byte 0x00 3. " DEIE ,Double-bit-error-caused interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " DEI ,Double-bit error occurrence bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " SEIE ,Single-bit-error-caused interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not occurred,Occurred" group.tbyte 0x10++0x2 line.tbyte 0x00 "EFECR,ECC pseudo-error generation control register" bitfld.tbyte 0x00 16. " FERR ,Pseudo-error generation enable bit" "Disabled,Enabled" hexmask.tbyte.byte 0x00 8.--15. 1. " EY ,Pseudo-error generation byte setting bits" hexmask.tbyte.byte 0x00 0.--7. 1. " EI ,Pseudo-error generation bit setting bits" else rgroup.word 0xC++0x1 line.word 0x00 "EFEAR,ECC pseudo-error generation address register" hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Single-bit error occurrence address bits" rgroup.byte 0xF++0x0 line.byte 0x00 "EECSR,ECC error control register" bitfld.byte 0x00 3. " DEIE ,Double-bit-error-caused interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " DEI ,Double-bit error occurrence bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " SEIE ,Single-bit-error-caused interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not occurred,Occurred" rgroup.tbyte 0x10++0x2 line.tbyte 0x00 "EFECR,ECC pseudo-error generation control register" bitfld.tbyte 0x00 16. " FERR ,Pseudo-error generation enable bit" "Disabled,Enabled" hexmask.tbyte.byte 0x00 8.--15. 1. " EY ,Pseudo-error generation byte setting bits" hexmask.tbyte.byte 0x00 0.--7. 1. " EI ,Pseudo-error generation bit setting bits" endif sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA")) if (((per.l(ad:0xB0680000+0x04))&0x100)==0x00) group.byte 0x13++0x0 line.byte 0x00 "EPDCR,ECC data path control register" bitfld.byte 0x00 2. " SKPG ,ECC generation function disable bit" "No,Yes" bitfld.byte 0x00 1. " SKPC ,ECC test function disable bit" "No,Yes" bitfld.byte 0x00 0. " EACC ,ECC area access enable bit" "Disabled,Enabled" else rgroup.byte 0x13++0x0 line.byte 0x00 "EPDCR,ECC data path control register" bitfld.byte 0x00 2. " SKPG ,ECC generation function disable bit" "No,Yes" bitfld.byte 0x00 1. " SKPC ,ECC test function disable bit" "No,Yes" bitfld.byte 0x00 0. " EACC ,ECC area access enable bit" "Disabled,Enabled" endif rgroup.byte 0x14++0x0 line.byte 0x00 "ECCTKCCR,ECC test mode key code control register" bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 2. " TM_ESKPG ,ECC generation function skip enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " TM_ESKPC ,ECC test function skip enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TM_EEACC ,ECC area access enable bit" "Data area,ECC area" endif if (((per.l(ad:0xB0680000+0x18))&0xE0000000)!=0x00) rgroup.long 0x18++0x3 line.long 0x00 "TEAR0,Test error address register 0" bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..." hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address" else rgroup.long 0x18++0x3 line.long 0x00 "TEAR0,Test error address register 0" bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..." endif if (((per.l(ad:0xB0680000+0x1C))&0xE0000000)!=0x00) rgroup.long 0x1C++0x3 line.long 0x00 "TEAR1,Test error address register 1" bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..." hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address" else rgroup.long 0x1C++0x3 line.long 0x00 "TEAR1,Test error address register 1" bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..." endif if (((per.l(ad:0xB0680000+0x20))&0xE0000000)!=0x00) rgroup.long 0x20++0x3 line.long 0x00 "TEAR2,Test error address register 2" bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..." hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address" else rgroup.long 0x20++0x3 line.long 0x00 "TEAR2,Test error address register 2" bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..." endif if (((per.l(ad:0xB0680000+0x04))&0x100)==0x00) group.word 0x24++0x1 line.word 0x00 "TASAR,Test start address register" hexmask.word 0x00 0.--14. 1. " SADDR ,RAM diagnosis start address" group.word 0x26++0x1 line.word 0x00 "TAEAR,Test end address register" hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address" group.word 0x28++0x1 line.word 0x00 "TTCR,Test diagnosis function register" rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or fewer,4 or more" bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TEI ,Error occurrence during diagnosis" "No error,Error" bitfld.word 0x00 5. " TCIE ,Diagnosis end factor interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed" textline " " bitfld.word 0x00 3. " TTYP[2] ,Unique diagnosis not performed/performed" "Not performed,Performed" bitfld.word 0x00 2. " TTYP[1] ,Checker diagnosis not performed/performed" "Not performed,Performed" bitfld.word 0x00 1. " TTYP[0] ,March diagnosis not performed/performed" "Not performed,Performed" textline " " rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress" group.byte 0x2A++0x0 line.byte 0x00 "TICR,Test initialization function register" bitfld.byte 0x00 3. " ICIE ,RAM initialization end factor interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ICI ,RAM initialization end" "Not completed,Completed" bitfld.byte 0x00 1. " ITYP ,RAM initialization contents specification" "0's,1's" textline " " rbitfld.byte 0x00 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress" group.byte 0x2B++0x0 line.byte 0x00 "TFECR,Test pseudo-error control register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,Pseudo-error generation processing specification (unique)" "No error,Error" bitfld.byte 0x00 1. " ETYP[1] ,Pseudo-error generation processing specification (checker)" "No error,Error" textline " " bitfld.byte 0x00 0. " ETYP[0] ,Pseudo-error generation processing specification (march)" "No error,Error" group.byte 0x2C++0x0 line.byte 0x00 "TKCCR,Test key code control register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis," else textline " " bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis," endif wgroup.byte 0x2F++0x0 line.byte 0x00 "TSRCR,Test software reset generation control register" bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset" wgroup.long 0x30++0x3 line.long 0x00 "EVENTCLR,Event clear register" bitfld.long 0x00 26. " DEICLR ,Double-bit error occurrence clear bit" "No effect,Clear" bitfld.long 0x00 24. " SEICLR ,Single-bit error occurrence clear bit" "No effect,Clear" bitfld.long 0x00 18. " ICICLR ,RAM initialization end clear bit" "No effect,Clear" textline " " bitfld.long 0x00 6. " TEICLR ,Error occurrence during diagnosis" "No effect,Clear" bitfld.long 0x00 4. " TCICLR ,Diagnosis end" "No effect,Clear" else rgroup.word 0x24++0x1 line.word 0x00 "TASAR,Test start address register" hexmask.word 0x00 0.--14. 1. " SADDR ,RAM diagnosis start address" rgroup.word 0x26++0x1 line.word 0x00 "TAEAR,Test end address register" hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address" rgroup.word 0x28++0x1 line.word 0x00 "TTCR,Test diagnosis function register" bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or fewer,4 or more" bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TEI ,Error occurrence during diagnosis" "No error,Error" bitfld.word 0x00 5. " TCIE ,Diagnosis end factor interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed" textline " " bitfld.word 0x00 3. " TTYP[2] ,Unique diagnosis not performed/performed" "Not performed,Performed" bitfld.word 0x00 2. " TTYP[1] ,Checker diagnosis not performed/performed" "Not performed,Performed" bitfld.word 0x00 1. " TTYP[0] ,March diagnosis not performed/performed" "Not performed,Performed" textline " " bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress" rgroup.byte 0x2A++0x0 line.byte 0x00 "TICR,Test initialization function register" bitfld.byte 0x00 3. " ICIE ,RAM initialization end factor interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ICI ,RAM initialization end" "Not completed,Completed" bitfld.byte 0x00 1. " ITYP ,RAM initialization contents specification" "0's,1's" textline " " bitfld.byte 0x00 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress" rgroup.byte 0x2B++0x0 line.byte 0x00 "TFECR,Test pseudo-error control register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,Pseudo-error generation processing specification (unique)" "No error,Error" bitfld.byte 0x00 1. " ETYP[1] ,Pseudo-error generation processing specification (checker)" "No error,Error" textline " " bitfld.byte 0x00 0. " ETYP[0] ,Pseudo-error generation processing specification (march)" "No error,Error" rgroup.byte 0x2C++0x0 line.byte 0x00 "TKCCR,Test key code control register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis," textline " " else bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis," endif hgroup.byte 0x2F++0x0 hide.byte 0x00 "TSRCR,Test software reset generation control register" hgroup.long 0x30++0x3 hide.long 0x00 "EVENTCLR,Event clear register" endif width 0xB tree.end endif tree "EXTERNAL INTERRUPT" base ad:0xB0620000 width 14. group.long 0x00++0x03 line.long 0x00 "ENIR_SET/CLR,External Interrupt Enable Register" sif cpuis("S6J342*")||cpuis("S6J351*") setclrfld.long 0x00 31. 0x04 31. 0x08 31. " EN_[31] ,External interrupt enable bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,External interrupt enable bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,External interrupt enable bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,External interrupt enable bit 28" "Disabled,Enabled" newline setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,External interrupt enable bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,External interrupt enable bit 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,External interrupt enable bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,External interrupt enable bit 24" "Disabled,Enabled" newline setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,External interrupt enable bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,External interrupt enable bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,External interrupt enable bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,External interrupt enable bit 20" "Disabled,Enabled" newline else setclrfld.long 0x00 23. 0x04 23. 0x08 23. " EN_[23] ,External interrupt enable bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,External interrupt enable bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,External interrupt enable bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,External interrupt enable bit 20" "Disabled,Enabled" newline endif setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,External interrupt enable bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,External interrupt enable bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,External interrupt enable bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,External interrupt enable bit 16" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,External interrupt enable bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,External interrupt enable bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,External interrupt enable bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,External interrupt enable bit 12" "Disabled,Enabled" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,External interrupt enable bit 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,External interrupt enable bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,External interrupt enable bit 09" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,External interrupt enable bit 08" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,External interrupt enable bit 07" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,External interrupt enable bit 06" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,External interrupt enable bit 05" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,External interrupt enable bit 04" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,External interrupt enable bit 03" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,External interrupt enable bit 02" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,External interrupt enable bit 01" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,External interrupt enable bit 00" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "EIRR,External Factor Register" sif cpuis("S6J342*")||cpuis("S6J351*") bitfld.long 0x00 31. " ER_[31] ,External interrupt factor detection bit 31" "Not detected,Detected" bitfld.long 0x00 30. " [30] ,External interrupt factor detection bit 30" "Not detected,Detected" bitfld.long 0x00 29. " [29] ,External interrupt factor detection bit 29" "Not detected,Detected" bitfld.long 0x00 28. " [28] ,External interrupt factor detection bit 28" "Not detected,Detected" newline bitfld.long 0x00 27. " [27] ,External interrupt factor detection bit 27" "Not detected,Detected" bitfld.long 0x00 26. " [26] ,External interrupt factor detection bit 26" "Not detected,Detected" bitfld.long 0x00 25. " [25] ,External interrupt factor detection bit 25" "Not detected,Detected" bitfld.long 0x00 24. " [24] ,External interrupt factor detection bit 24" "Not detected,Detected" newline bitfld.long 0x00 23. " [23] ,External interrupt factor detection bit 23" "Not detected,Detected" bitfld.long 0x00 22. " [22] ,External interrupt factor detection bit 22" "Not detected,Detected" bitfld.long 0x00 21. " [21] ,External interrupt factor detection bit 21" "Not detected,Detected" bitfld.long 0x00 20. " [20] ,External interrupt factor detection bit 20" "Not detected,Detected" newline else bitfld.long 0x00 23. " ER_[23] ,External interrupt factor detection bit 23" "Not detected,Detected" bitfld.long 0x00 22. " [22] ,External interrupt factor detection bit 22" "Not detected,Detected" bitfld.long 0x00 21. " [21] ,External interrupt factor detection bit 21" "Not detected,Detected" bitfld.long 0x00 20. " [20] ,External interrupt factor detection bit 20" "Not detected,Detected" newline endif bitfld.long 0x00 19. " [19] ,External interrupt factor detection bit 19" "Not detected,Detected" bitfld.long 0x00 18. " [18] ,External interrupt factor detection bit 18" "Not detected,Detected" bitfld.long 0x00 17. " [17] ,External interrupt factor detection bit 17" "Not detected,Detected" bitfld.long 0x00 16. " [16] ,External interrupt factor detection bit 16" "Not detected,Detected" newline bitfld.long 0x00 15. " [15] ,External interrupt factor detection bit 15" "Not detected,Detected" bitfld.long 0x00 14. " [14] ,External interrupt factor detection bit 14" "Not detected,Detected" bitfld.long 0x00 13. " [13] ,External interrupt factor detection bit 13" "Not detected,Detected" bitfld.long 0x00 12. " [12] ,External interrupt factor detection bit 12" "Not detected,Detected" newline bitfld.long 0x00 11. " [11] ,External interrupt factor detection bit 11" "Not detected,Detected" bitfld.long 0x00 10. " [10] ,External interrupt factor detection bit 10" "Not detected,Detected" bitfld.long 0x00 9. " [9] ,External interrupt factor detection bit 09" "Not detected,Detected" bitfld.long 0x00 8. " [8] ,External interrupt factor detection bit 08" "Not detected,Detected" newline bitfld.long 0x00 7. " [7] ,External interrupt factor detection bit 07" "Not detected,Detected" bitfld.long 0x00 6. " [6] ,External interrupt factor detection bit 06" "Not detected,Detected" bitfld.long 0x00 5. " [5] ,External interrupt factor detection bit 05" "Not detected,Detected" bitfld.long 0x00 4. " [4] ,External interrupt factor detection bit 04" "Not detected,Detected" newline bitfld.long 0x00 3. " [3] ,External interrupt factor detection bit 03" "Not detected,Detected" bitfld.long 0x00 2. " [2] ,External interrupt factor detection bit 02" "Not detected,Detected" bitfld.long 0x00 1. " [1] ,External interrupt factor detection bit 01" "Not detected,Detected" bitfld.long 0x00 0. " [0] ,External interrupt factor detection bit 00" "Not detected,Detected" group.long 0x10++0x07 line.long 0x00 "EIRCR,External Interrupt Factor Clear Register" sif cpuis("S6J342*")||cpuis("S6J351*") bitfld.long 0x00 31. " ERC_[31] ,External interrupt factor clear bit 31" "Not detected,Detected" bitfld.long 0x00 30. " [30] ,External interrupt factor clear bit 30" "Not detected,Detected" bitfld.long 0x00 29. " [29] ,External interrupt factor clear bit 29" "Not detected,Detected" bitfld.long 0x00 28. " [28] ,External interrupt factor clear bit 28" "Not detected,Detected" newline bitfld.long 0x00 27. " [27] ,External interrupt factor clear bit 27" "Not detected,Detected" bitfld.long 0x00 26. " [26] ,External interrupt factor clear bit 26" "Not detected,Detected" bitfld.long 0x00 25. " [25] ,External interrupt factor clear bit 25" "Not detected,Detected" bitfld.long 0x00 24. " [24] ,External interrupt factor clear bit 24" "Not detected,Detected" newline bitfld.long 0x00 23. " [23] ,External interrupt factor clear bit 23" "Not detected,Detected" bitfld.long 0x00 22. " [22] ,External interrupt factor clear bit 22" "Not detected,Detected" bitfld.long 0x00 21. " [21] ,External interrupt factor clear bit 21" "Not detected,Detected" bitfld.long 0x00 20. " [20] ,External interrupt factor clear bit 20" "Not detected,Detected" newline else bitfld.long 0x00 23. " ERC_[23] ,External interrupt factor clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,External interrupt factor clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,External interrupt factor clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,External interrupt factor clear bit 20" "No effect,Clear" newline endif bitfld.long 0x00 19. " [19] ,External interrupt factor clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,External interrupt factor clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,External interrupt factor clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,External interrupt factor clear bit 16" "No effect,Clear" newline bitfld.long 0x00 15. " [15] ,External interrupt factor clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,External interrupt factor clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,External interrupt factor clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,External interrupt factor clear bit 12" "No effect,Clear" newline bitfld.long 0x00 11. " [11] ,External interrupt factor clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,External interrupt factor clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,External interrupt factor clear bit 09" "No effect,Clear" bitfld.long 0x00 8. " [8] ,External interrupt factor clear bit 08" "No effect,Clear" newline bitfld.long 0x00 7. " [7] ,External interrupt factor clear bit 07" "No effect,Clear" bitfld.long 0x00 6. " [6] ,External interrupt factor clear bit 06" "No effect,Clear" bitfld.long 0x00 5. " [5] ,External interrupt factor clear bit 05" "No effect,Clear" bitfld.long 0x00 4. " [4] ,External interrupt factor clear bit 04" "No effect,Clear" newline bitfld.long 0x00 3. " [3] ,External interrupt factor clear bit 03" "No effect,Clear" bitfld.long 0x00 2. " [2] ,External interrupt factor clear bit 02" "No effect,Clear" bitfld.long 0x00 1. " [1] ,External interrupt factor clear bit 01" "No effect,Clear" bitfld.long 0x00 0. " [0] ,External interrupt factor clear bit 00" "No effect,Clear" line.long 0x04 "NFER_SET/CLR,Noise Filter Enable Register" sif cpuis("S6J342*")||cpuis("S6J351*") setclrfld.long 0x04 31. 0x08 31. 0x0C 31. " NFE_[31] ,Noise filter enable bit 31" "Disabled,Enabled" setclrfld.long 0x04 30. 0x08 30. 0x0C 30. " [30] ,Noise filter enable bit 30" "Disabled,Enabled" setclrfld.long 0x04 29. 0x08 29. 0x0C 29. " [29] ,Noise filter enable bit 29" "Disabled,Enabled" setclrfld.long 0x04 28. 0x08 28. 0x0C 28. " [28] ,Noise filter enable bit 28" "Disabled,Enabled" newline setclrfld.long 0x04 27. 0x08 27. 0x0C 27. " [27] ,Noise filter enable bit 27" "Disabled,Enabled" setclrfld.long 0x04 26. 0x08 26. 0x0C 26. " [26] ,Noise filter enable bit 26" "Disabled,Enabled" setclrfld.long 0x04 25. 0x08 25. 0x0C 25. " [25] ,Noise filter enable bit 25" "Disabled,Enabled" setclrfld.long 0x04 24. 0x08 24. 0x0C 24. " [24] ,Noise filter enable bit 24" "Disabled,Enabled" newline setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " [23] ,Noise filter enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Noise filter enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Noise filter enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Noise filter enable bit 20" "Disabled,Enabled" newline else setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " NFE_[23] ,Noise filter enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Noise filter enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Noise filter enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Noise filter enable bit 20" "Disabled,Enabled" newline endif setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,Noise filter enable bit 19" "Disabled,Enabled" setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,Noise filter enable bit 18" "Disabled,Enabled" setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,Noise filter enable bit 17" "Disabled,Enabled" setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,Noise filter enable bit 16" "Disabled,Enabled" newline setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,Noise filter enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,Noise filter enable bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,Noise filter enable bit 13" "Disabled,Enabled" setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,Noise filter enable bit 12" "Disabled,Enabled" newline setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,Noise filter enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,Noise filter enable bit 10" "Disabled,Enabled" setclrfld.long 0x04 9. 0x08 09. 0x0C 09. " [9] ,Noise filter enable bit 09" "Disabled,Enabled" setclrfld.long 0x04 8. 0x08 08. 0x0C 08. " [8] ,Noise filter enable bit 08" "Disabled,Enabled" newline setclrfld.long 0x04 7. 0x08 07. 0x0C 07. " [7] ,Noise filter enable bit 07" "Disabled,Enabled" setclrfld.long 0x04 6. 0x08 06. 0x0C 06. " [6] ,Noise filter enable bit 06" "Disabled,Enabled" setclrfld.long 0x04 5. 0x08 05. 0x0C 05. " [5] ,Noise filter enable bit 05" "Disabled,Enabled" setclrfld.long 0x04 4. 0x08 04. 0x0C 04. " [4] ,Noise filter enable bit 04" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x08 03. 0x0C 03. " [3] ,Noise filter enable bit 03" "Disabled,Enabled" setclrfld.long 0x04 2. 0x08 02. 0x0C 02. " [2] ,Noise filter enable bit 02" "Disabled,Enabled" setclrfld.long 0x04 1. 0x08 01. 0x0C 01. " [1] ,Noise filter enable bit 01" "Disabled,Enabled" setclrfld.long 0x04 0. 0x08 00. 0x0C 00. " [0] ,Noise filter enable bit 00" "Disabled,Enabled" group.long 0x20++0x0B line.long 0x00 "ELVR0,External Interrupt Level Register" bitfld.long 0x00 28.--30. " LCBA[7] ,INT7 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 24.--26. " [6] ,INT6 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 20.--22. " [5] ,INT5 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 16.--18. " [4] ,INT4 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x00 12.--14. " [3] ,INT3 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 8.--10. " [2] ,INT2 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 4.--6. " [1] ,INT1 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 0.--2. " [0] ,INT0 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" line.long 0x04 "ELVR1,External Interrupt Level Register" bitfld.long 0x04 28.--30. " LCBA[7] ,INT15 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 24.--26. " [6] ,INT14 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 20.--22. " [5] ,INT13 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 16.--18. " [4] ,INT12 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x04 12.--14. " [3] ,INT11 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 8.--10. " [2] ,INT10 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 4.--6. " [1] ,INT9 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 0.--2. " [0] ,INT8 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" line.long 0x08 "ELVR2,External Interrupt Level Register" bitfld.long 0x08 28.--30. " LCBA[7] ,INT23 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 24.--26. " [6] ,INT22 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 20.--22. " [5] ,INT21 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 16.--18. " [4] ,INT20 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x08 12.--14. " [3] ,INT19 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 8.--10. " [2] ,INT18 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 4.--6. " [1] ,INT17 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 0.--2. " [0] ,INT16 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" sif cpuis("S6J342*")||cpuis("S6J351*") group.long 0x2C++0x3 line.long 0x00 "ELVR3,External Interrupt Level Register" bitfld.long 0x00 28.--30. " LCBA[7] ,INT31 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 24.--26. " [6] ,INT30 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 20.--22. " [5] ,INT29 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 16.--18. " [4] ,INT28 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x00 12.--14. " [3] ,INT27 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 8.--10. " [2] ,INT26 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 4.--6. " [1] ,INT25 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 0.--2. " [0] ,INT24 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" endif group.long 0x30++0x07 line.long 0x00 "NMIR,Non Maskable Interrupt Register" bitfld.long 0x00 8. " NMICLR ,Non maskable interrupt clear bit" ",Clear" rbitfld.long 0x00 0. " NMIINT ,Non maskable interrupt request detection bit" "Not detected,Detected" line.long 0x04 "DRER_SET/CLR,DMA Request Enable Register" sif cpuis("S6J342*")||cpuis("S6J351*") setclrfld.long 0x04 31. 0x08 31. 0x0C 31. " DRE_[31] ,DMA request enable bit 31" "Disabled,Enabled" setclrfld.long 0x04 30. 0x08 30. 0x0C 30. " [30] ,DMA request enable bit 30" "Disabled,Enabled" setclrfld.long 0x04 29. 0x08 29. 0x0C 29. " [29] ,DMA request enable bit 29" "Disabled,Enabled" setclrfld.long 0x04 28. 0x08 28. 0x0C 28. " [28] ,DMA request enable bit 28" "Disabled,Enabled" newline setclrfld.long 0x04 27. 0x08 27. 0x0C 27. " [27] ,DMA request enable bit 27" "Disabled,Enabled" setclrfld.long 0x04 26. 0x08 26. 0x0C 26. " [26] ,DMA request enable bit 26" "Disabled,Enabled" setclrfld.long 0x04 25. 0x08 25. 0x0C 25. " [25] ,DMA request enable bit 25" "Disabled,Enabled" setclrfld.long 0x04 24. 0x08 24. 0x0C 24. " [24] ,DMA request enable bit 24" "Disabled,Enabled" newline setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " [23] ,DMA request enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,DMA request enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,DMA request enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,DMA request enable bit 20" "Disabled,Enabled" newline else setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " DRE_[23] ,DMA request enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,DMA request enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,DMA request enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,DMA request enable bit 20" "Disabled,Enabled" newline endif setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,DMA request enable bit 19" "Disabled,Enabled" setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,DMA request enable bit 18" "Disabled,Enabled" setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,DMA request enable bit 17" "Disabled,Enabled" setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,DMA request enable bit 16" "Disabled,Enabled" newline setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,DMA request enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,DMA request enable bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,DMA request enable bit 13" "Disabled,Enabled" setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,DMA request enable bit 12" "Disabled,Enabled" newline setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,DMA request enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,DMA request enable bit 10" "Disabled,Enabled" setclrfld.long 0x04 9. 0x08 09. 0x0C 09. " [9] ,DMA request enable bit 9" "Disabled,Enabled" setclrfld.long 0x04 8. 0x08 08. 0x0C 08. " [8] ,DMA request enable bit 8" "Disabled,Enabled" newline setclrfld.long 0x04 7. 0x08 07. 0x0C 07. " [7] ,DMA request enable bit 7" "Disabled,Enabled" setclrfld.long 0x04 6. 0x08 06. 0x0C 06. " [6] ,DMA request enable bit 6" "Disabled,Enabled" setclrfld.long 0x04 5. 0x08 05. 0x0C 05. " [5] ,DMA request enable bit 5" "Disabled,Enabled" setclrfld.long 0x04 4. 0x08 04. 0x0C 04. " [4] ,DMA request enable bit 4" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x08 03. 0x0C 03. " [3] ,DMA request enable bit 3" "Disabled,Enabled" setclrfld.long 0x04 2. 0x08 02. 0x0C 02. " [2] ,DMA request enable bit 2" "Disabled,Enabled" setclrfld.long 0x04 1. 0x08 01. 0x0C 01. " [1] ,DMA request enable bit 1" "Disabled,Enabled" setclrfld.long 0x04 0. 0x08 00. 0x0C 00. " [0] ,DMA request enable bit 0" "Disabled,Enabled" rgroup.long 0x40++0x03 line.long 0x00 "DRFR,DMA Request Flag Register" sif cpuis("S6J342*")||cpuis("S6J351*") bitfld.long 0x00 31. " DRF_[31] ,DMA request detection bit 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,DMA request detection bit 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,DMA request detection bit 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,DMA request detection bit 28" "Not requested,Requested" newline bitfld.long 0x00 27. " [27] ,DMA request detection bit 27" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,DMA request detection bit 26" "Not requested,Requested" bitfld.long 0x00 25. " [25] ,DMA request detection bit 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,DMA request detection bit 24" "Not requested,Requested" newline bitfld.long 0x00 23. " [23] ,DMA request detection bit 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,DMA request detection bit 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,DMA request detection bit 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,DMA request detection bit 20" "Not requested,Requested" newline else bitfld.long 0x00 23. " DRF_[23] ,DMA request detection bit 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,DMA request detection bit 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,DMA request detection bit 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,DMA request detection bit 20" "Not requested,Requested" newline endif bitfld.long 0x00 19. " [19] ,DMA request detection bit 19" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,DMA request detection bit 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,DMA request detection bit 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,DMA request detection bit 16" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,DMA request detection bit 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,DMA request detection bit 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,DMA request detection bit 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,DMA request detection bit 12" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,DMA request detection bit 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,DMA request detection bit 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,DMA request detection bit 09" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,DMA request detection bit 08" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,DMA request detection bit 07" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,DMA request detection bit 06" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,DMA request detection bit 05" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,DMA request detection bit 04" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,DMA request detection bit 03" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,DMA request detection bit 02" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,DMA request detection bit 01" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,DMA request detection bit 00" "Not requested,Requested" width 0x0B tree.end tree "HWDT (HARDWARE WATCHDOG TIMER)" base ad:0xB060C000 width 10. group.long 0x00++0x03 line.long 0x00 "PROT,Watchdog Protection Register" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Watchdog Counter Register" group.long 0x0C++0x03 line.long 0x00 "RSTCAUSE,Watchdog Reset Factor Register" bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "No Reset,Reset" bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "No Reset,Reset" bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "No Reset,Reset" newline bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "No Reset,Reset" bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "No Reset,Reset" wgroup.long 0x10++0x03 line.long 0x00 "TRG0,Watchdog Trigger 0" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0" wgroup.long 0x18++0x03 line.long 0x00 "TRG1,Watchdog Trigger 1" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1" group.long 0x20++0x03 line.long 0x00 "INT,Watchdog Interrupt" bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Generated" bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated" rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected" newline rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected" wgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" group.long 0x2C++0x17 line.long 0x00 "TRG0CFG,Watchdog Trigger 0 Configuration Register" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits" line.long 0x04 "TRG1CFG,Watchdog trigger 1 configuration register" hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits" line.long 0x08 "RUNLLS,Watchdog Lower Limit RUN Setting Register" line.long 0x0C "RUNULS,Watchdog Upper Limit RUN Setting Register" line.long 0x10 "PSSLLS,Watchdog Lower Limit PSS Setting Register" line.long 0x14 "PSSULS,Watchdog Upper Limit PSS Setting Register" wgroup.long 0x44++0x03 line.long 0x00 "RSTDLY,Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02) group.long 0x48++0x03 line.long 0x00 "CFG,Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline rbitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled" rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CFG,Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif rgroup.long 0x4C++0x0F line.long 0x00 "RUNLLC,Watchdog Lower Limit RUN Current Register" line.long 0x04 "RUNULC,Watchdog Upper Limit RUN Current Register" line.long 0x08 "PSSLLC,Watchdog Lower Limit PSS Current Register" line.long 0x0C "PSSULC,Watchdog Upper Limit PSS Current Register" width 0x0B tree.end tree "SWDT (SOFTWARE WATCHDOG TIMER)" base ad:0xB0308000 width 10. group.long 0x00++0x03 line.long 0x00 "PROT,Watchdog Protection Register" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Watchdog Counter Register" group.long 0x0C++0x03 line.long 0x00 "RSTCAUSE,Watchdog Reset Factor Register" bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "No Reset,Reset" bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "No Reset,Reset" bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "No Reset,Reset" newline bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "No Reset,Reset" bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "No Reset,Reset" wgroup.long 0x10++0x03 line.long 0x00 "TRG0,Watchdog Trigger 0" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0" wgroup.long 0x18++0x03 line.long 0x00 "TRG1,Watchdog Trigger 1" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1" group.long 0x20++0x03 line.long 0x00 "INT,Watchdog Interrupt" bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Generated" bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated" rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected" newline rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected" wgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" group.long 0x2C++0x17 line.long 0x00 "TRG0CFG,Watchdog Trigger 0 Configuration Register" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits" line.long 0x04 "TRG1CFG,Watchdog trigger 1 configuration register" hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits" line.long 0x08 "RUNLLS,Watchdog Lower Limit RUN Setting Register" line.long 0x0C "RUNULS,Watchdog Upper Limit RUN Setting Register" line.long 0x10 "PSSLLS,Watchdog Lower Limit PSS Setting Register" line.long 0x14 "PSSULS,Watchdog Upper Limit PSS Setting Register" wgroup.long 0x44++0x03 line.long 0x00 "RSTDLY,Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" if ((per.l(ad:0xB0308000+0x48)&0x02)==0x02) group.long 0x48++0x03 line.long 0x00 "CFG,Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline rbitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled" rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CFG,Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif rgroup.long 0x4C++0x0F line.long 0x00 "RUNLLC,Watchdog Lower Limit RUN Current Register" line.long 0x04 "RUNULC,Watchdog Upper Limit RUN Current Register" line.long 0x08 "PSSLLC,Watchdog Lower Limit PSS Current Register" line.long 0x0C "PSSULC,Watchdog Upper Limit PSS Current Register" width 0x0B tree.end tree "TCRAM (TCRAM INTERFACE)" base ad:0xB0410000 width 14. if ((per.l(ad:0xB0410000)&0x100)==0x00) group.long 0x00++0x07 line.long 0x00 "TCMCFG0,Configuration Register 0" bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3" rbitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits" line.long 0x04 "TCMCFG1,Configuration Register 1" else rgroup.long 0x00++0x07 line.long 0x00 "TCMCFG0,Configuration Register 0" bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3" bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits" line.long 0x04 "TCMCFG1,Configuration Register 1" endif wgroup.long 0x08++0x03 line.long 0x00 "TCMUNLOCK,Unlock register" sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA")) if ((per.l(ad:0xB0410000)&0x100)==0x00) group.long 0x10++0x03 line.long 0x00 "ECCDEN,ECC Direct Access Enable Register" bitfld.long 0x00 23. " DEN ,Direct access enable" "Disabled,Enabled" newline sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") hexmask.long.byte 0x00 16.--22. 1. " DENUNLOCK ,Direct access enable unlock" endif else rgroup.long 0x10++0x03 line.long 0x00 "ECCDEN,ECC Direct Access Enable Register" bitfld.long 0x00 23. " DEN ,Direct access enable" "Disabled,Enabled" newline sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") hexmask.long.byte 0x00 16.--22. 1. " DENUNLOCK ,Direct access enable unlock" endif endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") rgroup.long 0x14++0x0B line.long 0x00 "ECCDR_PARITY,ECC Direct Read Parity Register" hexmask.long.word 0x00 0.--13. 1. " ECCDR_PARITY ,Direct read parity data" line.long 0x04 "ECCDR_DATA0,ECC Direct Read Data Register 0" line.long 0x08 "ECCDR_DATA1,ECC Direct Read Data Register 1" else group.long 0x14++0x0B line.long 0x00 "ECCDR_PARITY,ECC Direct Read Parity Register" hexmask.long.word 0x00 0.--13. 1. " ECCDR_PARITY ,Direct read parity data" line.long 0x04 "ECCDR_DATA0,ECC Direct Read Data Register 0" line.long 0x08 "ECCDR_DATA1,ECC Direct Read Data Register 1" endif if ((per.l(ad:0xB0410000)&0x100)==0x00) group.long 0x24++0x03 line.long 0x00 "ECCDW,ECC Direct Write Register" bitfld.long 0x00 31. " DWEN ,Direct access enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " DWENUNLOCK ,Direct write access enable unlock" hexmask.long.word 0x00 0.--13. 1. " ECCDW_PARITY ,Direct write parity data" else rgroup.long 0x24++0x03 line.long 0x00 "ECCDW,ECC Direct Write Register" bitfld.long 0x00 31. " DWEN ,Direct access enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " DWENUNLOCK ,Direct write access enable unlock" hexmask.long.word 0x00 0.--13. 1. " ECCDW_PARITY ,Direct write parity data" endif endif if ((per.l(ad:0xB0410000+0x30)&0xE0000000)!=0x00) rgroup.long 0x30++0x03 line.long 0x00 "TEAR0,Error Address Register 0" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.long.word 0x00 0.--13. 1. " ERR_ADDR ,Error occurrence address" newline else hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address" endif else rgroup.long 0x30++0x03 line.long 0x00 "TEAR0,Error Address Register 0" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error " "No error,Error" bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error" endif if ((per.l(ad:0xB0410000+0x34)&0xE0000000)!=0x00) rgroup.long 0x34++0x03 line.long 0x00 "TEAR1,Error Address Register 1" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.long.word 0x00 0.--13. 1. " ERR_ADDR ,Error occurrence address" newline else hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address" endif else rgroup.long 0x34++0x03 line.long 0x00 "TEAR1,Error Address Register 1" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error" endif if ((per.l(ad:0xB0410000+0x38)&0xE0000000)!=0x00) rgroup.long 0x38++0x03 line.long 0x00 "TEAR2,Error Address Register 2" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.long.word 0x00 0.--13. 1. " ERR_ADDR ,Error occurrence address" newline else hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address" endif else rgroup.long 0x38++0x03 line.long 0x00 "TEAR2,Error Address Register 2" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error" endif if ((per.l(ad:0xB0410000)&0x100)==0x00) group.word 0x3C++0x03 line.word 0x00 "TAEAR,End Address Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--13. 1. " EADDR ,RAM diagnosis end address" else hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address" endif line.word 0x02 "TASAR,Start Address Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.word 0x02 0.--13. 1. " SADDR ,RAM diagnosis start address" else hexmask.word 0x02 0.--14. 1. " SADDR ,RAM diagnosis start address" endif group.byte 0x40++0x01 line.byte 0x00 "TFECR,Pseudo Error Generation Control Register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,Unique pseudo-error generation" "Not generated,Generated" bitfld.byte 0x00 1. " ETYP[1] ,Checker pseudo-error generation" "Not generated,Generated" newline bitfld.byte 0x00 0. " ETYP[0] ,March pseudo-error generation" "Not generated,Generated" line.byte 0x01 "TICR,Initialization Function Register" bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled" rbitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed" bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1" newline rbitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress" group.word 0x42++0x01 line.word 0x00 "TTCR,Diagnosis Function Register" rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more" bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" newline rbitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1" bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed" newline bitfld.word 0x00 3. " TTYP[2] ,Perform unique diagnosis" "Not performed,Performed" bitfld.word 0x00 2. " TTYP[1] ,Perform checked diagnosis" "Not performed,Performed" bitfld.word 0x00 1. " TTYP[0] ,Perform march diagnosis" "Not performed,Performed" newline rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress" wgroup.byte 0x44++0x00 line.byte 0x00 "TSRCR,Soft Reset Generation Control Register" bitfld.byte 0x00 7. " SRST ,Software reset" "Not reset,Reset" group.byte 0x47++0x00 line.byte 0x00 "TKCCR,Key Code Control Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..." else bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..." endif wgroup.byte 0x45++0x00 line.byte 0x00 "TSCR,Status Clear Register" bitfld.byte 0x00 6. " TEIC ,Diagnosis-time error generation clear" "No effect,Clear" bitfld.byte 0x00 4. " TCIC ,Diagnosis end clear" "No effect,Clear" bitfld.byte 0x00 2. " ICIC ,Ram initialization end clear" "No effect,Clear" else rgroup.word 0x3C++0x03 line.word 0x00 "TAEAR,End Address Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--13. 1. " EADDR ,RAM diagnosis end address" else hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address" endif line.word 0x02 "TASAR,Start Address Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") hexmask.word 0x02 0.--13. 1. " SADDR ,RAM diagnosis start address" else hexmask.word 0x02 0.--14. 1. " SADDR ,RAM diagnosis start address" endif rgroup.byte 0x40++0x01 line.byte 0x00 "TFECR,Pseudo Error Generation Control Register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,March pseudo-error generation processing specification" "Not generated,Generated" bitfld.byte 0x00 1. " ETYP[1] ,Checker pseudo-error generation processing specification" "Not generated,Generated" newline bitfld.byte 0x00 0. " ETYP[0] ,Unique pseudo-error generation processing specification" "Not generated,Generated" line.byte 0x01 "TICR,Initialization Function Register" bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed" bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1" newline bitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress" rgroup.word 0x42++0x01 line.word 0x00 "TTCR,Diagnosis Function Register" bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more" bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" newline bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1" bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed" newline bitfld.word 0x00 3. " TTYP[2] ,Perform march diagnosis" "Not performed,Performed" bitfld.word 0x00 2. " TTYP[1] ,Perform checked diagnosis" "Not performed,Performed" bitfld.word 0x00 1. " TTYP[0] ,Perform unique diagnosis" "Not performed,Performed" newline bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") hgroup.byte 0x44++0x00 hide.byte 0x00 "TSRCR,Soft Reset Generation Control Register" rgroup.byte 0x47++0x00 line.byte 0x00 "TKCCR,Key Code Control Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis," else bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis," endif hgroup.byte 0x45++0x00 hide.byte 0x00 "TSCR,Status Clear Register" else rgroup.byte 0x44++0x00 line.byte 0x00 "TSRCR,Soft Reset Generation Control Register" bitfld.byte 0x00 7. " SRST ,software reset" "No reset,Reset" rgroup.byte 0x47++0x00 line.byte 0x00 "TKCCR,Key Code Control Register" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis," else bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis," endif rgroup.byte 0x45++0x00 line.byte 0x00 "TSCR,Status Clear Register" bitfld.byte 0x00 6. " TEIC ,Diagnosis-time error generation clear" "No effect,Clear" bitfld.byte 0x00 4. " TCIC ,Diagnosis end clear" "No effect,Clear" bitfld.byte 0x00 2. " ICIC ,Ram initialization end clear" "No effect,Clear" endif endif width 0x0B tree.end tree "TCFLASH" base ad:0xB0411000 width 11. group.long 0x00++0x03 line.long 0x00 "FCPROTKEY,Configuration Protection Key Register" group.long 0x08++0x03 line.long 0x00 "FCFGR,Configuration Register" bitfld.long 0x00 6. " SWFRST ,Software reset" "No reset,Reset" bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM" bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") newline bitfld.long 0x00 2. " TCMSPEC ,TCM speculative access enable" "Disabled,Enabled" textfld " " endif bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2cycles,3cycles" group.long 0x10++0x03 line.long 0x00 "FECCCTRL,ECC Control Register" bitfld.long 0x00 0. " ECCOFF ,ECC off" "Performed,Not performed" newline sif cpuis("S6J336*")||cpuis("S6j337*") group.long 0x28++0x07 line.long 0x00 "FDATEIR_L,Data Bit Error Injection Register" bitfld.long 0x00 31. " FDATEIR[63] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 30. " [62] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 29. " [61] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 28. " [60] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 27. " [59] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 26. " [58] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 25. " [57] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 24. " [56] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 23. " [55] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 22. " [54] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 21. " [53] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 20. " [52] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 19. " [51] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 18. " [50] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 17. " [49] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 16. " [48] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 15. " [47] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 14. " [46] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 13. " [45] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 12. " [44] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 11. " [43] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 10. " [42] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 9. " [41] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 8. " [40] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 7. " [39] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 6. " [38] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 5. " [37] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 4. " [36] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 3. " [35] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 2. " [34] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 1. " [33] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 0. " [32] ,Data bit error injection point" "No error,Error" line.long 0x04 "FDATEIR_H,Data Bit Error Injection Register" bitfld.long 0x04 31. " FDATEIR[31] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 30. " [30] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 29. " [29] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 28. " [28] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 27. " [27] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 26. " [26] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 25. " [25] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 24. " [24] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 23. " [23] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 22. " [22] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 21. " [21] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 20. " [20] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 19. " [19] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 18. " [18] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 17. " [17] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 16. " [16] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 15. " [15] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 14. " [14] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 13. " [13] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 12. " [12] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 11. " [11] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 10. " [10] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 9. " [9] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 8. " [8] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 7. " [7] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 6. " [6] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 5. " [5] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 4. " [4] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 3. " [3] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 2. " [2] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 1. " [1] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 0. " [0] ,Data bit error injection point" "No error,Error" newline endif group.long 0x1C++0x03 line.long 0x00 "FECCEIR,Bit Error Injection Register" sif (cpuis("S6J33*")) bitfld.long 0x00 27. " LMASK[3] ,Error injection lane mask (0x18 to 0x1F)" "Error,No error" bitfld.long 0x00 26. " LMASK[2] ,Error injection lane mask (0x10 to 0x17)" "Error,No error" bitfld.long 0x00 25. " LMASK[1] ,Error injection lane mask (0x08 to 0x0F)" "Error,No error" bitfld.long 0x00 24. " LMASK[0] ,Error injection lane mask (0x00 to 0x07)" "Error,No error" newline bitfld.long 0x00 7. " FECCEIR[7] ,ECC bit injection point" "0,1" bitfld.long 0x00 6. " FECCEIR[6] ,ECC bit injection point" "0,1" bitfld.long 0x00 5. " FECCEIR[5] ,ECC bit injection point" "0,1" bitfld.long 0x00 4. " FECCEIR[4] ,ECC bit injection point" "0,1" newline bitfld.long 0x00 3. " FECCEIR[3] ,ECC bit injection point" "0,1" bitfld.long 0x00 2. " FECCEIR[2] ,ECC bit injection point" "0,1" bitfld.long 0x00 1. " FECCEIR[1] ,ECC bit injection point" "0,1" bitfld.long 0x00 0. " FECCEIR[0] ,ECC bit injection point" "0,1" else bitfld.long 0x00 25. " LMASK[1] ,Error injection lane mask" "Error,No error" bitfld.long 0x00 24. " LMASK[0] ,Error injection lane mask" "Error,No error" bitfld.long 0x00 7. " FECCEIR[7] ,ECC bit injection point" "0,1" bitfld.long 0x00 6. " FECCEIR[6] ,ECC bit injection point" "0,1" newline bitfld.long 0x00 5. " FECCEIR[5] ,ECC bit injection point" "0,1" bitfld.long 0x00 4. " FECCEIR[4] ,ECC bit injection point" "0,1" bitfld.long 0x00 3. " FECCEIR[3] ,ECC bit injection point" "0,1" bitfld.long 0x00 2. " FECCEIR[2] ,ECC bit injection point" "0,1" newline bitfld.long 0x00 1. " FECCEIR[1] ,ECC bit injection point" "0,1" bitfld.long 0x00 0. " FECCEIR[0] ,ECC bit injection point" "0,1" endif sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") group.long 0x20++0x07 line.long 0x00 "FICTRL0,Interrupt Control Register" bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled" line.long 0x04 "FICTRL1,Interrupt Control Register" bitfld.long 0x04 9. " HANGIC ,Hang interrupt bit" "No effect,Clear" bitfld.long 0x04 8. " RDYIC ,Ready interrupt clear" "No effect,Clear" bitfld.long 0x04 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FICTRL,Interrupt Control Register" bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled" endif sif !cpuis("S6J33*") group.long 0x28++0x07 line.long 0x00 "FDATEIR_L,Data Bit Error Injection Register" line.long 0x04 "FDATEIR_H,Data Bit Error Injection Register" endif sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") rgroup.long 0x38++0x07 line.long 0x00 "FSTAT0,Status Register" bitfld.long 0x00 16. " MARGIN ,MARGIN" "0,1" bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " CERS ,Chip erase status" "Not performed,Performed" bitfld.long 0x00 6. " PGMS ,Program status" "No programming,Programming" bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended" newline bitfld.long 0x00 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended" bitfld.long 0x00 3. " SERS ,Sector erase status" "Not performed,Performed" bitfld.long 0x00 2. " READ ,Reading ready" "Unable,Able" newline bitfld.long 0x00 1. " HANG ,Hangup" "No,Yes" bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Performing,Completed" line.long 0x04 "FSTAT1,Status Register" bitfld.long 0x04 16. " MARGIN ,MARGIN" "0,1" bitfld.long 0x04 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt" newline bitfld.long 0x04 7. " CERS ,Chip erase status" "Not performed,Performed" bitfld.long 0x04 6. " PGMS ,Program status" "No programming,Programming" bitfld.long 0x04 5. " ESPS ,Erase suspend status" "Not suspended,Suspended" newline bitfld.long 0x04 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended" bitfld.long 0x04 3. " SERS ,Sector erase status" "Not performed,Performed" bitfld.long 0x04 2. " READ ,Reading ready" "Not ready,Ready" newline bitfld.long 0x04 1. " HANG ,Hangup" "No,Yes" bitfld.long 0x04 0. " RDY ,Programming/erasing ready" "Performing,Completed" else rgroup.long 0x38++0x03 line.long 0x00 "FSTAT,Status Register" bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt" bitfld.long 0x00 7. " CERS ,Chip erase status" "Not performed,Performed" newline bitfld.long 0x00 6. " PGMS ,Program status" "No programming,Programming" bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended" bitfld.long 0x00 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended" newline bitfld.long 0x00 3. " SERS ,Sector erase status" "Not performed,Performed" bitfld.long 0x00 2. " READ ,Reading ready" "Not ready,Ready" bitfld.long 0x00 1. " HANG ,Hangup" "No,Yes" newline bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Performing,Completed" endif group.long 0x50++0x03 line.long 0x00 "FSECIR,Interrupt Register" sif !cpuis("S6J336*")&&!cpuis("S6j337*") hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome" newline endif rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear" newline bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled" sif cpuis("S6J33*") rgroup.long 0x54++0x03 line.long 0x00 "FECCEAR,ECC Error Address Register" hexmask.long 0x00 5.--31. 0x20 " FECCEAR_BASE ,Base Error Address" newline bitfld.long 0x00 3. " SELF[3] ,Single Error Lane Flag bit 3 [255:192]" "No error,Error" bitfld.long 0x00 2. " SELF[2] ,Single Error Lane Flag bit 2 [191:128]" "No error,Error" bitfld.long 0x00 1. " SELF[1] ,Single Error Lane Flag bit 1 [127:64]" "No error,Error" newline bitfld.long 0x00 0. " SELF[0] ,Single Error Lane Flag bit 0 [63:0]" "No error,Error" rgroup.long 0x60++0x07 line.long 0x00 "FUIDR0,TCFLASH Unique ID ROM Register 0" line.long 0x04 "FUIDR1,TCFLASH Unique ID ROM Register 1" group.long 0x80++0x03 line.long 0x00 "FUCEDIR,Uncorrectable Error Detection Interrupt Register" rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "No error,Error" bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" "No effect,Clear" rgroup.long 0x84++0x03 line.long 0x00 "FUCEAR,Uncorrectable Error Address Register" hexmask.long 0x00 5.--31. 0x20 " UCEA_BASE ,Uncorrectable Error Address" newline bitfld.long 0x00 3. " UCELF[3] ,Uncorrectable Error Lane Flag bit 3 [255:192]" "No error,Error" bitfld.long 0x00 2. " UCELF[2] ,Uncorrectable Error Lane Flag bit 2 [191:128]" "No error,Error" bitfld.long 0x00 1. " UCELF[1] ,Uncorrectable Error Lane Flag bit 1 [127:64]" "No error,Error" newline bitfld.long 0x00 0. " UCELF[0] ,Uncorrectable Error Lane Flag bit 0 [63:0]" "No error,Error" sif cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x88++0x03 line.long 0x00 "SYNR,Syndrome Register" hexmask.long.byte 0x00 24.--31. 1. " SYN[3] ,Syndrome of FWORD256 [255:192]" hexmask.long.byte 0x00 17.--23. 1. " SYN[2] ,Syndrome of FWORD256 [191:128]" hexmask.long.word 0x00 8.--16. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]" newline hexmask.long.byte 0x00 0.--7. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]" else group.long 0x88++0x03 line.long 0x00 "SYNR,Syndrome Register" hexmask.long.byte 0x00 24.--31. 1. " SYN[3] ,Syndrome of FWORD256 [255:192]" hexmask.long.byte 0x00 17.--23. 1. " SYN[2] ,Syndrome of FWORD256 [191:128]" hexmask.long.word 0x00 8.--16. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]" newline hexmask.long.byte 0x00 0.--7. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]" endif else rgroup.long 0x54++0x03 line.long 0x00 "FECCEAR,ECC Error Address Register" group.long 0x80++0x03 line.long 0x00 "FUCEDIR,Uncorrectable Error Detection Interrupt Register" hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome" rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "Not generated,Generated" bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" "No effect,Clear" rgroup.long 0x84++0x03 line.long 0x00 "FUCEAR,Uncorrectable Error Address Register" endif group.long 0x90++0x03 line.long 0x00 "BRCFG,Buffer Region Configuration Register" hexmask.long.word 0x00 16.--31. 1. " REGION_END_BUF ,TCM buffer word number of region end" hexmask.long.byte 0x00 8.--15. 1. " SSEC ,Starting bufferable sector number" hexmask.long.byte 0x00 0.--7. 1. " ESEC ,Ending bufferable sector number" group.long 0x98++0x03 line.long 0x00 "BRAT,Buffer Region Attribute Register" bitfld.long 0x00 16. " VCLR ,TCM buffer region international clear" "No effect,Clear" bitfld.long 0x00 8.--9. " AM ,Buffer policy for TCM buffer region" "Wait state,2 pieces,Locked,?..." bitfld.long 0x00 0. " RGEN ,TCM Buffer region enable" "Disabled,Enabled" newline width 26. sif (cpuis("S6J33*")) if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x400+0x00)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" group.long (0x400+0x04)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" group.long (0x400+0x08)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" group.long (0x400+0x0C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" group.long (0x400+0x10)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register" group.long (0x400+0x14)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register" group.long (0x400+0x18)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register" group.long (0x400+0x1C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register" group.long (0x400+0x20)++0x03 line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x400+0x24)++0x03 line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x400+0x28)++0x03 line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x400+0x00)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x400+0x04)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x400+0x08)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x400+0x0C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x400+0x14)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x400+0x18)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x400+0x1C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x400+0x20)++0x03 line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x400+0x24)++0x03 line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x400+0x28)++0x03 line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x400+0x00)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x400+0x04)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x400+0x08)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x400+0x0C)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x400+0x10)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x400+0x14)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x400+0x18)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x400+0x1C)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x400+0x20)++0x03 hide.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" hgroup.long (0x400+0x24)++0x03 hide.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" hgroup.long (0x400+0x28)++0x03 hide.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x440+0x00)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" group.long (0x440+0x04)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" group.long (0x440+0x08)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" group.long (0x440+0x0C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" group.long (0x440+0x10)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register" group.long (0x440+0x14)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register" group.long (0x440+0x18)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register" group.long (0x440+0x1C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register" group.long (0x440+0x20)++0x03 line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x440+0x24)++0x03 line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x440+0x28)++0x03 line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x440+0x00)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x440+0x04)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x440+0x08)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x440+0x0C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x440+0x10)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x440+0x14)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x440+0x18)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x440+0x1C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x440+0x20)++0x03 line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x440+0x24)++0x03 line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x440+0x28)++0x03 line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x440+0x00)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x440+0x04)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x440+0x08)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x440+0x0C)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x440+0x10)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x440+0x14)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x440+0x18)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x440+0x1C)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x440+0x20)++0x03 hide.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" hgroup.long (0x440+0x24)++0x03 hide.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" hgroup.long (0x440+0x28)++0x03 hide.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x480+0x00)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" group.long (0x480+0x04)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" group.long (0x480+0x08)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" group.long (0x480+0x0C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" group.long (0x480+0x10)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register" group.long (0x480+0x14)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register" group.long (0x480+0x18)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register" group.long (0x480+0x1C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register" group.long (0x480+0x20)++0x03 line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x480+0x24)++0x03 line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x480+0x28)++0x03 line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x480+0x00)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x480+0x04)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x480+0x08)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x480+0x0C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x480+0x10)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x480+0x14)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x480+0x18)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x480+0x1C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x480+0x24)++0x03 line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x480+0x28)++0x03 line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x480+0x00)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x480+0x04)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x480+0x08)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x480+0x0C)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x480+0x10)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x480+0x14)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x480+0x18)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x480+0x1C)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x480+0x20)++0x03 hide.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" hgroup.long (0x480+0x24)++0x03 hide.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" hgroup.long (0x480+0x28)++0x03 hide.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x4C0+0x00)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" group.long (0x4C0+0x04)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" group.long (0x4C0+0x08)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" group.long (0x4C0+0x0C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" group.long (0x4C0+0x10)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register" group.long (0x4C0+0x14)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register" group.long (0x4C0+0x18)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register" group.long (0x4C0+0x1C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register" group.long (0x4C0+0x20)++0x03 line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x4C0+0x24)++0x03 line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x4C0+0x28)++0x03 line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x4C0+0x00)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x4C0+0x04)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x4C0+0x08)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x4C0+0x0C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x4C0+0x10)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x4C0+0x14)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x4C0+0x18)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x4C0+0x1C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x4C0+0x20)++0x03 line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x4C0+0x24)++0x03 line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x4C0+0x28)++0x03 line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x4C0+0x00)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x4C0+0x04)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x4C0+0x08)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x4C0+0x0C)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x4C0+0x10)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x4C0+0x14)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x4C0+0x18)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x4C0+0x1C)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x4C0+0x20)++0x03 hide.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" hgroup.long (0x4C0+0x24)++0x03 hide.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" hgroup.long (0x4C0+0x28)++0x03 hide.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x500+0x00)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" group.long (0x500+0x04)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" group.long (0x500+0x08)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" group.long (0x500+0x0C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" group.long (0x500+0x10)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register" group.long (0x500+0x14)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register" group.long (0x500+0x18)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register" group.long (0x500+0x1C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register" group.long (0x500+0x20)++0x03 line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x500+0x24)++0x03 line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x500+0x28)++0x03 line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x500+0x00)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x500+0x04)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x500+0x08)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x500+0x0C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x500+0x14)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x500+0x18)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x500+0x1C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x500+0x20)++0x03 line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x500+0x24)++0x03 line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x500+0x28)++0x03 line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x500+0x00)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x500+0x04)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x500+0x08)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x500+0x0C)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x500+0x14)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x500+0x18)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x500+0x1C)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x500+0x20)++0x03 hide.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" hgroup.long (0x500+0x24)++0x03 hide.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" hgroup.long (0x500+0x28)++0x03 hide.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x540+0x00)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" group.long (0x540+0x04)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" group.long (0x540+0x08)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" group.long (0x540+0x0C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" group.long (0x540+0x10)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register" group.long (0x540+0x14)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register" group.long (0x540+0x18)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register" group.long (0x540+0x1C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register" group.long (0x540+0x20)++0x03 line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x540+0x24)++0x03 line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x540+0x28)++0x03 line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x540+0x00)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x540+0x04)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x540+0x08)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x540+0x0C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x540+0x10)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x540+0x14)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x540+0x18)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x540+0x1C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x540+0x20)++0x03 line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x540+0x24)++0x03 line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x540+0x28)++0x03 line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x540+0x00)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x540+0x04)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x540+0x08)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x540+0x0C)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x540+0x10)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x540+0x14)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x540+0x18)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x540+0x1C)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x540+0x20)++0x03 hide.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" hgroup.long (0x540+0x24)++0x03 hide.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" hgroup.long (0x540+0x28)++0x03 hide.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x580+0x00)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" group.long (0x580+0x04)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" group.long (0x580+0x08)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" group.long (0x580+0x0C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" group.long (0x580+0x10)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register" group.long (0x580+0x14)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register" group.long (0x580+0x18)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register" group.long (0x580+0x1C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register" group.long (0x580+0x20)++0x03 line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x580+0x24)++0x03 line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x580+0x28)++0x03 line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x580+0x00)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x580+0x04)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x580+0x08)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x580+0x0C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x580+0x10)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x580+0x14)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x580+0x18)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x580+0x1C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x580+0x20)++0x03 line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x580+0x24)++0x03 line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x580+0x28)++0x03 line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x580+0x00)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x580+0x04)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x580+0x08)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x580+0x0C)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x580+0x10)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x580+0x14)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x580+0x18)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x580+0x1C)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x580+0x20)++0x03 hide.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" hgroup.long (0x580+0x24)++0x03 hide.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" hgroup.long (0x580+0x28)++0x03 hide.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x5C0+0x00)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" group.long (0x5C0+0x04)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" group.long (0x5C0+0x08)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" group.long (0x5C0+0x0C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" group.long (0x5C0+0x10)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register" group.long (0x5C0+0x14)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register" group.long (0x5C0+0x18)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register" group.long (0x5C0+0x1C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register" group.long (0x5C0+0x20)++0x03 line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x5C0+0x24)++0x03 line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x5C0+0x28)++0x03 line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x5C0+0x00)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x5C0+0x04)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x5C0+0x08)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x5C0+0x0C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x5C0+0x10)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x5C0+0x14)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x5C0+0x18)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x5C0+0x1C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x5C0+0x20)++0x03 line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x5C0+0x24)++0x03 line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x5C0+0x28)++0x03 line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x5C0+0x00)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x5C0+0x04)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x5C0+0x08)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x5C0+0x0C)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x5C0+0x10)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x5C0+0x14)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x5C0+0x18)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x5C0+0x1C)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x5C0+0x20)++0x03 hide.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" hgroup.long (0x5C0+0x24)++0x03 hide.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" hgroup.long (0x5C0+0x28)++0x03 hide.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x600+0x00)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" group.long (0x600+0x04)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" group.long (0x600+0x08)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" group.long (0x600+0x0C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" group.long (0x600+0x10)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register" group.long (0x600+0x14)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register" group.long (0x600+0x18)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register" group.long (0x600+0x1C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register" group.long (0x600+0x20)++0x03 line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x600+0x24)++0x03 line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x600+0x28)++0x03 line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x600+0x00)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x600+0x04)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x600+0x08)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x600+0x0C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x600+0x10)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x600+0x14)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x600+0x18)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x600+0x1C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x600+0x20)++0x03 line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x600+0x24)++0x03 line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x600+0x28)++0x03 line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x600+0x00)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x600+0x04)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x600+0x08)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x600+0x0C)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x600+0x10)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x600+0x14)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x600+0x18)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x600+0x1C)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x600+0x20)++0x03 hide.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" hgroup.long (0x600+0x24)++0x03 hide.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" hgroup.long (0x600+0x28)++0x03 hide.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x640+0x00)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" group.long (0x640+0x04)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" group.long (0x640+0x08)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" group.long (0x640+0x0C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" group.long (0x640+0x10)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register" group.long (0x640+0x14)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register" group.long (0x640+0x18)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register" group.long (0x640+0x1C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register" group.long (0x640+0x20)++0x03 line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x640+0x24)++0x03 line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x640+0x28)++0x03 line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x640+0x00)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x640+0x04)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x640+0x08)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x640+0x0C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x640+0x10)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x640+0x14)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x640+0x18)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x640+0x1C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x640+0x24)++0x03 line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x640+0x28)++0x03 line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x640+0x00)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x640+0x04)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x640+0x08)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x640+0x0C)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x640+0x10)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x640+0x14)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x640+0x18)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x640+0x1C)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x640+0x20)++0x03 hide.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" hgroup.long (0x640+0x24)++0x03 hide.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" hgroup.long (0x640+0x28)++0x03 hide.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x680+0x00)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" group.long (0x680+0x04)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" group.long (0x680+0x08)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" group.long (0x680+0x0C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" group.long (0x680+0x10)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register" group.long (0x680+0x14)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register" group.long (0x680+0x18)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register" group.long (0x680+0x1C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register" group.long (0x680+0x20)++0x03 line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x680+0x24)++0x03 line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x680+0x28)++0x03 line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x680+0x00)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x680+0x04)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x680+0x08)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x680+0x0C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x680+0x10)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x680+0x14)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x680+0x18)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x680+0x1C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x680+0x20)++0x03 line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x680+0x24)++0x03 line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x680+0x28)++0x03 line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x680+0x00)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x680+0x04)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x680+0x08)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x680+0x0C)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x680+0x10)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x680+0x14)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x680+0x18)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x680+0x1C)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x680+0x20)++0x03 hide.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" hgroup.long (0x680+0x24)++0x03 hide.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" hgroup.long (0x680+0x28)++0x03 hide.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x6C0+0x00)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" group.long (0x6C0+0x04)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" group.long (0x6C0+0x08)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" group.long (0x6C0+0x0C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" group.long (0x6C0+0x10)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register" group.long (0x6C0+0x14)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register" group.long (0x6C0+0x18)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register" group.long (0x6C0+0x1C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register" group.long (0x6C0+0x20)++0x03 line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x6C0+0x24)++0x03 line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x6C0+0x28)++0x03 line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x6C0+0x00)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x6C0+0x04)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x6C0+0x08)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x6C0+0x0C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x6C0+0x10)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x6C0+0x14)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x6C0+0x18)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x6C0+0x1C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x6C0+0x20)++0x03 line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x6C0+0x24)++0x03 line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x6C0+0x28)++0x03 line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x6C0+0x00)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x6C0+0x04)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x6C0+0x08)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x6C0+0x0C)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x6C0+0x10)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x6C0+0x14)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x6C0+0x18)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x6C0+0x1C)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x6C0+0x20)++0x03 hide.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" hgroup.long (0x6C0+0x24)++0x03 hide.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" hgroup.long (0x6C0+0x28)++0x03 hide.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x700+0x00)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" group.long (0x700+0x04)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" group.long (0x700+0x08)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" group.long (0x700+0x0C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" group.long (0x700+0x10)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register" group.long (0x700+0x14)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register" group.long (0x700+0x18)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register" group.long (0x700+0x1C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register" group.long (0x700+0x20)++0x03 line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x700+0x24)++0x03 line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x700+0x28)++0x03 line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x700+0x00)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x700+0x04)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x700+0x08)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x700+0x0C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x700+0x10)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x700+0x14)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x700+0x18)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x700+0x1C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x700+0x20)++0x03 line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x700+0x24)++0x03 line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x700+0x28)++0x03 line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x700+0x00)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x700+0x04)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x700+0x08)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x700+0x0C)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x700+0x10)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x700+0x14)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x700+0x18)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x700+0x1C)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x700+0x20)++0x03 hide.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" hgroup.long (0x700+0x24)++0x03 hide.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" hgroup.long (0x700+0x28)++0x03 hide.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x740+0x00)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" group.long (0x740+0x04)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" group.long (0x740+0x08)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" group.long (0x740+0x0C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" group.long (0x740+0x10)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register" group.long (0x740+0x14)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register" group.long (0x740+0x18)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register" group.long (0x740+0x1C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register" group.long (0x740+0x20)++0x03 line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x740+0x24)++0x03 line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x740+0x28)++0x03 line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x740+0x00)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x740+0x04)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x740+0x08)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x740+0x0C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x740+0x10)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x740+0x14)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x740+0x18)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x740+0x1C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x740+0x20)++0x03 line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x740+0x24)++0x03 line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x740+0x28)++0x03 line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x740+0x00)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x740+0x04)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x740+0x08)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x740+0x0C)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x740+0x10)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x740+0x14)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x740+0x18)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x740+0x1C)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x740+0x20)++0x03 hide.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" hgroup.long (0x740+0x24)++0x03 hide.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" hgroup.long (0x740+0x28)++0x03 hide.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x780+0x00)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" group.long (0x780+0x04)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" group.long (0x780+0x08)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" group.long (0x780+0x0C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" group.long (0x780+0x10)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register" group.long (0x780+0x14)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register" group.long (0x780+0x18)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register" group.long (0x780+0x1C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register" group.long (0x780+0x20)++0x03 line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x780+0x24)++0x03 line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x780+0x28)++0x03 line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x780+0x00)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x780+0x04)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x780+0x08)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x780+0x0C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x780+0x10)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x780+0x14)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x780+0x18)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x780+0x1C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x780+0x20)++0x03 line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x780+0x24)++0x03 line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x780+0x28)++0x03 line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x780+0x00)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x780+0x04)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x780+0x08)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x780+0x0C)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x780+0x10)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x780+0x14)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x780+0x18)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x780+0x1C)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x780+0x20)++0x03 hide.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" hgroup.long (0x780+0x24)++0x03 hide.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" hgroup.long (0x780+0x28)++0x03 hide.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x7C0+0x00)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" group.long (0x7C0+0x04)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" group.long (0x7C0+0x08)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" group.long (0x7C0+0x0C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" group.long (0x7C0+0x10)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register" group.long (0x7C0+0x14)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register" group.long (0x7C0+0x18)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register" group.long (0x7C0+0x1C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register" group.long (0x7C0+0x20)++0x03 line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x7C0+0x24)++0x03 line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x7C0+0x28)++0x03 line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x7C0+0x00)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x7C0+0x04)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x7C0+0x08)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x7C0+0x0C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x7C0+0x10)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x7C0+0x14)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x7C0+0x18)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x7C0+0x1C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x7C0+0x20)++0x03 line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" sif cpuis("S6J336*")||cpuis("S6J337*") hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit" else bitfld.long 0x00 24. " READ1 , Read 1" ",1" hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif rgroup.long (0x7C0+0x24)++0x03 line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x7C0+0x28)++0x03 line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x7C0+0x00)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x7C0+0x04)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x7C0+0x08)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x7C0+0x0C)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x7C0+0x10)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x7C0+0x14)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x7C0+0x18)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x7C0+0x1C)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x7C0+0x20)++0x03 hide.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" hgroup.long (0x7C0+0x24)++0x03 hide.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" hgroup.long (0x7C0+0x28)++0x03 hide.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" endif else if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x100+0x00)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" group.long (0x100+0x04)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" group.long (0x100+0x08)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" group.long (0x100+0x0C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" group.long (0x100+0x10)++0x03 line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x100+0x14)++0x03 line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x100+0x18)++0x03 line.long 0x00 "TCMBUF0_W6,TCMBUF0_W6" group.long (0x100+0x1C)++0x03 line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" else group.long (0x100+0x1C)++0x03 line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x100+0x00)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x100+0x04)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x100+0x08)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x100+0x0C)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x100+0x10)++0x03 hide.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" hgroup.long (0x100+0x14)++0x03 hide.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x100+0x18)++0x03 hide.long 0x00 "TCMBUF0_W6,TCMBUF0_W6" endif hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x120+0x00)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" group.long (0x120+0x04)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" group.long (0x120+0x08)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" group.long (0x120+0x0C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" group.long (0x120+0x10)++0x03 line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x120+0x14)++0x03 line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x120+0x18)++0x03 line.long 0x00 "TCMBUF1_W6,TCMBUF1_W6" group.long (0x120+0x1C)++0x03 line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" else group.long (0x120+0x1C)++0x03 line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x120+0x00)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x120+0x04)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x120+0x08)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x120+0x0C)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x120+0x10)++0x03 hide.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" hgroup.long (0x120+0x14)++0x03 hide.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x120+0x18)++0x03 hide.long 0x00 "TCMBUF1_W6,TCMBUF1_W6" endif hgroup.long (0x120+0x1C)++0x03 hide.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x140+0x00)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" group.long (0x140+0x04)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" group.long (0x140+0x08)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" group.long (0x140+0x0C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" group.long (0x140+0x10)++0x03 line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x140+0x14)++0x03 line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x140+0x18)++0x03 line.long 0x00 "TCMBUF2_W6,TCMBUF2_W6" group.long (0x140+0x1C)++0x03 line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" else group.long (0x140+0x1C)++0x03 line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x140+0x00)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x140+0x04)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x140+0x08)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x140+0x0C)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x140+0x10)++0x03 hide.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" hgroup.long (0x140+0x14)++0x03 hide.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x140+0x18)++0x03 hide.long 0x00 "TCMBUF2_W6,TCMBUF2_W6" endif hgroup.long (0x140+0x1C)++0x03 hide.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x160+0x00)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" group.long (0x160+0x04)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" group.long (0x160+0x08)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" group.long (0x160+0x0C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" group.long (0x160+0x10)++0x03 line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x160+0x14)++0x03 line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x160+0x18)++0x03 line.long 0x00 "TCMBUF3_W6,TCMBUF3_W6" group.long (0x160+0x1C)++0x03 line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" else group.long (0x160+0x1C)++0x03 line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x160+0x00)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x160+0x04)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x160+0x08)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x160+0x0C)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x160+0x10)++0x03 hide.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" hgroup.long (0x160+0x14)++0x03 hide.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x160+0x18)++0x03 hide.long 0x00 "TCMBUF3_W6,TCMBUF3_W6" endif hgroup.long (0x160+0x1C)++0x03 hide.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x180+0x00)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" group.long (0x180+0x04)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" group.long (0x180+0x08)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" group.long (0x180+0x0C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" group.long (0x180+0x10)++0x03 line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x180+0x14)++0x03 line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x180+0x18)++0x03 line.long 0x00 "TCMBUF4_W6,TCMBUF4_W6" group.long (0x180+0x1C)++0x03 line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" else group.long (0x180+0x1C)++0x03 line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x180+0x00)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x180+0x04)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x180+0x08)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x180+0x0C)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x180+0x10)++0x03 hide.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" hgroup.long (0x180+0x14)++0x03 hide.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x180+0x18)++0x03 hide.long 0x00 "TCMBUF4_W6,TCMBUF4_W6" endif hgroup.long (0x180+0x1C)++0x03 hide.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x1A0+0x00)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" group.long (0x1A0+0x04)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" group.long (0x1A0+0x0C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" group.long (0x1A0+0x10)++0x03 line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x1A0+0x14)++0x03 line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x1A0+0x18)++0x03 line.long 0x00 "TCMBUF5_W6,TCMBUF5_W6" group.long (0x1A0+0x1C)++0x03 line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" else group.long (0x1A0+0x1C)++0x03 line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x1A0+0x00)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x1A0+0x04)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x1A0+0x08)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x1A0+0x0C)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x1A0+0x10)++0x03 hide.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" hgroup.long (0x1A0+0x14)++0x03 hide.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x1A0+0x18)++0x03 hide.long 0x00 "TCMBUF5_W6,TCMBUF5_W6" endif hgroup.long (0x1A0+0x1C)++0x03 hide.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x1C0+0x00)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" group.long (0x1C0+0x04)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" group.long (0x1C0+0x0C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" group.long (0x1C0+0x10)++0x03 line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x1C0+0x14)++0x03 line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x1C0+0x18)++0x03 line.long 0x00 "TCMBUF6_W6,TCMBUF6_W6" group.long (0x1C0+0x1C)++0x03 line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" else group.long (0x1C0+0x1C)++0x03 line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x1C0+0x00)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x1C0+0x04)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x1C0+0x08)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x1C0+0x0C)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x1C0+0x10)++0x03 hide.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" hgroup.long (0x1C0+0x14)++0x03 hide.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x1C0+0x18)++0x03 hide.long 0x00 "TCMBUF6_W6,TCMBUF6_W6" endif hgroup.long (0x1C0+0x1C)++0x03 hide.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x1E0+0x00)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" group.long (0x1E0+0x04)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" group.long (0x1E0+0x0C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x1E0+0x14)++0x03 line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x1E0+0x18)++0x03 line.long 0x00 "TCMBUF7_W6,TCMBUF7_W6" group.long (0x1E0+0x1C)++0x03 line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" else group.long (0x1E0+0x1C)++0x03 line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x1E0+0x00)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x1E0+0x04)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x1E0+0x08)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x1E0+0x0C)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x1E0+0x10)++0x03 hide.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" hgroup.long (0x1E0+0x14)++0x03 hide.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x1E0+0x18)++0x03 hide.long 0x00 "TCMBUF7_W6,TCMBUF7_W6" endif hgroup.long (0x1E0+0x1C)++0x03 hide.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x200+0x00)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" group.long (0x200+0x04)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" group.long (0x200+0x08)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" group.long (0x200+0x0C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" group.long (0x200+0x10)++0x03 line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x200+0x14)++0x03 line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x200+0x18)++0x03 line.long 0x00 "TCMBUF8_W6,TCMBUF8_W6" group.long (0x200+0x1C)++0x03 line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" else group.long (0x200+0x1C)++0x03 line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x200+0x00)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x200+0x04)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x200+0x08)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x200+0x0C)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x200+0x10)++0x03 hide.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" hgroup.long (0x200+0x14)++0x03 hide.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x200+0x18)++0x03 hide.long 0x00 "TCMBUF8_W6,TCMBUF8_W6" endif hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x220+0x00)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" group.long (0x220+0x04)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" group.long (0x220+0x08)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" group.long (0x220+0x0C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" group.long (0x220+0x10)++0x03 line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x220+0x14)++0x03 line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x220+0x18)++0x03 line.long 0x00 "TCMBUF9_W6,TCMBUF9_W6" group.long (0x220+0x1C)++0x03 line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" else group.long (0x220+0x1C)++0x03 line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x220+0x00)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x220+0x04)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x220+0x08)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x220+0x0C)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x220+0x10)++0x03 hide.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" hgroup.long (0x220+0x14)++0x03 hide.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x220+0x18)++0x03 hide.long 0x00 "TCMBUF9_W6,TCMBUF9_W6" endif hgroup.long (0x220+0x1C)++0x03 hide.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x240+0x00)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" group.long (0x240+0x04)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" group.long (0x240+0x08)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" group.long (0x240+0x0C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" group.long (0x240+0x10)++0x03 line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x240+0x14)++0x03 line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x240+0x18)++0x03 line.long 0x00 "TCMBUF10_W6,TCMBUF10_W6" group.long (0x240+0x1C)++0x03 line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" else group.long (0x240+0x1C)++0x03 line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x240+0x00)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x240+0x04)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x240+0x08)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x240+0x0C)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x240+0x10)++0x03 hide.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" hgroup.long (0x240+0x14)++0x03 hide.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x240+0x18)++0x03 hide.long 0x00 "TCMBUF10_W6,TCMBUF10_W6" endif hgroup.long (0x240+0x1C)++0x03 hide.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x260+0x00)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" group.long (0x260+0x04)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" group.long (0x260+0x08)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" group.long (0x260+0x0C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" group.long (0x260+0x10)++0x03 line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x260+0x14)++0x03 line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x260+0x18)++0x03 line.long 0x00 "TCMBUF11_W6,TCMBUF11_W6" group.long (0x260+0x1C)++0x03 line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" else group.long (0x260+0x1C)++0x03 line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x260+0x00)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x260+0x04)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x260+0x08)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x260+0x0C)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x260+0x10)++0x03 hide.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" hgroup.long (0x260+0x14)++0x03 hide.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x260+0x18)++0x03 hide.long 0x00 "TCMBUF11_W6,TCMBUF11_W6" endif hgroup.long (0x260+0x1C)++0x03 hide.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x280+0x00)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" group.long (0x280+0x04)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" group.long (0x280+0x08)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" group.long (0x280+0x0C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" group.long (0x280+0x10)++0x03 line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x280+0x14)++0x03 line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x280+0x18)++0x03 line.long 0x00 "TCMBUF12_W6,TCMBUF12_W6" group.long (0x280+0x1C)++0x03 line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" else group.long (0x280+0x1C)++0x03 line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x280+0x00)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x280+0x04)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x280+0x08)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x280+0x0C)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x280+0x10)++0x03 hide.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" hgroup.long (0x280+0x14)++0x03 hide.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x280+0x18)++0x03 hide.long 0x00 "TCMBUF12_W6,TCMBUF12_W6" endif hgroup.long (0x280+0x1C)++0x03 hide.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x2A0+0x00)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" group.long (0x2A0+0x04)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" group.long (0x2A0+0x08)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" group.long (0x2A0+0x0C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" group.long (0x2A0+0x10)++0x03 line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x2A0+0x14)++0x03 line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x2A0+0x18)++0x03 line.long 0x00 "TCMBUF13_W6,TCMBUF13_W6" group.long (0x2A0+0x1C)++0x03 line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" else group.long (0x2A0+0x1C)++0x03 line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x2A0+0x00)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x2A0+0x04)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x2A0+0x08)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x2A0+0x0C)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x2A0+0x10)++0x03 hide.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" hgroup.long (0x2A0+0x14)++0x03 hide.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x2A0+0x18)++0x03 hide.long 0x00 "TCMBUF13_W6,TCMBUF13_W6" endif hgroup.long (0x2A0+0x1C)++0x03 hide.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x2C0+0x00)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" group.long (0x2C0+0x04)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" group.long (0x2C0+0x08)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" group.long (0x2C0+0x0C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x2C0+0x14)++0x03 line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x2C0+0x18)++0x03 line.long 0x00 "TCMBUF14_W6,TCMBUF14_W6" group.long (0x2C0+0x1C)++0x03 line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" else group.long (0x2C0+0x1C)++0x03 line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x2C0+0x00)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x2C0+0x04)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x2C0+0x08)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x2C0+0x0C)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x2C0+0x10)++0x03 hide.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" hgroup.long (0x2C0+0x14)++0x03 hide.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x2C0+0x18)++0x03 hide.long 0x00 "TCMBUF14_W6,TCMBUF14_W6" endif hgroup.long (0x2C0+0x1C)++0x03 hide.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00) group.long (0x2E0+0x00)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" group.long (0x2E0+0x04)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" group.long (0x2E0+0x08)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" group.long (0x2E0+0x0C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" group.long (0x2E0+0x10)++0x03 line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit" newline else hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit" endif group.long (0x2E0+0x14)++0x03 line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.long (0x2E0+0x18)++0x03 line.long 0x00 "TCMBUF15_W6,TCMBUF15_W6" group.long (0x2E0+0x1C)++0x03 line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" else group.long (0x2E0+0x1C)++0x03 line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer" endif else hgroup.long (0x2E0+0x00)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x2E0+0x04)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x2E0+0x08)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x2E0+0x0C)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x2E0+0x10)++0x03 hide.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" hgroup.long (0x2E0+0x14)++0x03 hide.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hgroup.long (0x2E0+0x18)++0x03 hide.long 0x00 "TCMBUF15_W6,TCMBUF15_W6" endif hgroup.long (0x2E0+0x1C)++0x03 hide.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" endif endif width 0x0B tree.end tree "WORKFLASH" base ad:0xB0412000 width 9. group.long 0x00++0x03 line.long 0x00 "CPR,Configuration Protection Key Register" group.long 0x08++0x03 line.long 0x00 "CR,Configuration Register" bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset" bitfld.long 0x00 8. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FAWC ,Flash access wait control" "Disabled,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" group.long 0x10++0x03 line.long 0x00 "WCR,Write Command Sequencer Configuration Register" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" rgroup.long 0x14++0x03 line.long 0x00 "WSR,Write Command Sequencer Status Register" bitfld.long 0x00 0.--1. " ST ,Write command sequencer status" "Idle,Sending,Waiting,?..." group.long 0x78++0x03 line.long 0x00 "DBEIR,Data Bit Error Injection Register" bitfld.long 0x00 31. " DBEIR[31] ,Data bit error injection location bit 31" "Sent,Inverted" bitfld.long 0x00 30. " [30] ,Data bit error injection location bit 30" "Sent,Inverted" bitfld.long 0x00 29. " [29] ,Data bit error injection location bit 29" "Sent,Inverted" newline bitfld.long 0x00 28. " [28] ,Data bit error injection location bit 28" "Sent,Inverted" bitfld.long 0x00 27. " [27] ,Data bit error injection location bit 27" "Sent,Inverted" bitfld.long 0x00 26. " [26] ,Data bit error injection location bit 26" "Sent,Inverted" newline bitfld.long 0x00 25. " [25] ,Data bit error injection location bit 25" "Sent,Inverted" bitfld.long 0x00 24. " [24] ,Data bit error injection location bit 24" "Sent,Inverted" bitfld.long 0x00 23. " [23] ,Data bit error injection location bit 23" "Sent,Inverted" newline bitfld.long 0x00 22. " [22] ,Data bit error injection location bit 22" "Sent,Inverted" bitfld.long 0x00 21. " [21] ,Data bit error injection location bit 21" "Sent,Inverted" bitfld.long 0x00 20. " [20] ,Data bit error injection location bit 20" "Sent,Inverted" newline bitfld.long 0x00 19. " [19] ,Data bit error injection location bit 19" "Sent,Inverted" bitfld.long 0x00 18. " [18] ,Data bit error injection location bit 18" "Sent,Inverted" bitfld.long 0x00 17. " [17] ,Data bit error injection location bit 17" "Sent,Inverted" newline bitfld.long 0x00 16. " [16] ,Data bit error injection location bit 16" "Sent,Inverted" bitfld.long 0x00 15. " [15] ,Data bit error injection location bit 15" "Sent,Inverted" bitfld.long 0x00 14. " [14] ,Data bit error injection location bit 14" "Sent,Inverted" newline bitfld.long 0x00 13. " [13] ,Data bit error injection location bit 13" "Sent,Inverted" bitfld.long 0x00 12. " [12] ,Data bit error injection location bit 12" "Sent,Inverted" bitfld.long 0x00 11. " [11] ,Data bit error injection location bit 11" "Sent,Inverted" newline bitfld.long 0x00 10. " [10] ,Data bit error injection location bit 10" "Sent,Inverted" bitfld.long 0x00 9. " [9] ,Data bit error injection location bit 9" "Sent,Inverted" bitfld.long 0x00 8. " [8] ,Data bit error injection location bit 8" "Sent,Inverted" newline bitfld.long 0x00 7. " [7] ,Data bit error injection location bit 7" "Sent,Inverted" bitfld.long 0x00 6. " [6] ,Data bit error injection location bit 6" "Sent,Inverted" bitfld.long 0x00 5. " [5] ,Data bit error injection location bit 5" "Sent,Inverted" newline bitfld.long 0x00 4. " [4] ,Data bit error injection location bit 4" "Sent,Inverted" bitfld.long 0x00 3. " [3] ,Data bit error injection location bit 3" "Sent,Inverted" bitfld.long 0x00 2. " [2] ,Data bit error injection location bit 2" "Sent,Inverted" newline bitfld.long 0x00 1. " [1] ,Data bit error injection location bit 1" "Sent,Inverted" bitfld.long 0x00 0. " [0] ,Data bit error injection location bit 0" "Sent,Inverted" group.long 0x1C++0x03 line.long 0x00 "EEIR,ECC Bit Error Injection Register" bitfld.long 0x00 6. " EEIR[6] ,ECC bit error injection location bit 6" "Sent,Inverted" bitfld.long 0x00 5. " [5] ,ECC bit error injection location bit 5" "Sent,Inverted" bitfld.long 0x00 4. " [4] ,ECC bit error injection location bit 4" "Sent,Inverted" newline bitfld.long 0x00 3. " [3] ,ECC bit error injection location bit 3" "Sent,Inverted" bitfld.long 0x00 2. " [2] ,ECC bit error injection location bit 2" "Sent,Inverted" bitfld.long 0x00 1. " [1] ,ECC bit error injection location bit 1" "Sent,Inverted" newline bitfld.long 0x00 0. " [0] ,ECC bit error injection location bit 0" "Sent,Inverted" group.long 0x24++0x03 line.long 0x00 "ICR,Interrupt Control Register" bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RDYIE ,Ready interrupt enable" "Disabled,Enabled" rgroup.long 0x28++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 12. " WERINT ,Write enable release interrupt" "No interrupt,Interrupt" bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended" bitfld.long 0x00 3. " SERS ,Sector erase status" "Not erasing,Erasing" bitfld.long 0x00 0. " RDY ,Ready" "Not ready,Ready" group.long 0x2C++0x03 line.long 0x00 "SECIR,SEC Interrupt Register" hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome" rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear" newline bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled" rgroup.long 0x30++0x03 line.long 0x00 "EEAR,ECC Error Address Register" group.long 0x38++0x03 line.long 0x00 "EMENR,Extra Mode Enable Register" bitfld.long 0x00 8. " AEE ,Read arbitration error enable" "Disabled,Enabled" bitfld.long 0x00 0. " EMEN ,Extra mode enable" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "SEQCM,Sequencer Command Register" hexmask.long.byte 0x00 16.--23. 1. " ERS ,Sector erase instruction" bitfld.long 0x00 0.--3. " OPC ,Command" "No operation,Read/Reset,Erase command,Suspend 1 command,,,,,,,,Suspend 2 command,?..." rgroup.long 0x58++0x03 line.long 0x00 "ARBERR,Arbitration Error Register" bitfld.long 0x00 0. " ARBERR ,Read arbitration error" "No error,Error" group.long 0x5C++0x03 line.long 0x00 "ARBCLR,Arbitration Error Clear Register" bitfld.long 0x00 0. " ARBCLR ,Read arbitration error clear" "No effect,Clear" rgroup.long 0x60++0x03 line.long 0x00 "BERR,Bus Error Response Status Register" bitfld.long 0x00 11. " ERSERR ,ERS writing violation" "Not detected,Detected" bitfld.long 0x00 10. " RORW ,Write access to a read-only register" "Not detected,Detected" bitfld.long 0x00 9. " NWTM ,Writing to mirror area 4" "Not detected,Detected" newline bitfld.long 0x00 8. " ACCIGN ,Command overrun" "Not detected,Detected" bitfld.long 0x00 7. " ECRWL ,Protection sequence violation" "Not detected,Detected" bitfld.long 0x00 6. " UNACC ,Unprivileged writing" "Not detected,Detected" newline bitfld.long 0x00 5. " RESA ,Reserved area access" "Not detected,Detected" bitfld.long 0x00 4. " RWE ,Write protected sector access error" "Not detected,Detected" bitfld.long 0x00 2. " SIZE ,Access size violation" "Not detected,Detected" newline bitfld.long 0x00 1. " CRWE ,Writing prohibition violation" "Not detected,Detected" bitfld.long 0x00 0. " DED ,Uncorrectable error detection" "Not detected,Detected" group.long 0x64++0x03 line.long 0x00 "BERRCLR,Bus Error Response Status Clear Register" bitfld.long 0x00 11. " ERSERRCLR ,ERSERR clear" "No effect,Clear" bitfld.long 0x00 10. " RORWCLR ,RORW clear" "No effect,Clear" bitfld.long 0x00 9. " NWTMCLR ,NWTM clear" "No effect,Clear" newline bitfld.long 0x00 8. " ACCIGNCLR ,ACCIGN clear" "No effect,Clear" bitfld.long 0x00 7. " ECRWLCLR ,ECRWL clear" "No effect,Clear" bitfld.long 0x00 6. " UNACCLR ,UNACC clear" "No effect,Clear" newline bitfld.long 0x00 5. " RESACLR ,RESA clear" "No effect,Clear" bitfld.long 0x00 4. " RWECLR ,RWE clear" "No effect,Clear" bitfld.long 0x00 2. " SIZECLR ,SIZE clear" "No effect,Clear" newline bitfld.long 0x00 1. " CRWECLR ,CRWE clear" "No effect,Clear" bitfld.long 0x00 0. " DEDCLR ,DED clear" "No effect,Clear" rgroup.long 0x6C++0x07 line.long 0x00 "UCESR,Uncorrectable Error Status Register" hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome" line.long 0x04 "UCEAR,Uncorrectable Error Address Register" group.long 0x68++0x03 line.long 0x00 "WARBR,Write Arbitration Register" rbitfld.long 0x00 24. " WERSTS ,Write enable release status" "Disabled,Enabled" rbitfld.long 0x00 16. " WERINT ,Write enable release interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " WERINTCLR ,Write enable release interrupt clear" "No effect,Clear" newline bitfld.long 0x00 0. " WERINTE ,Write enable release interrupt" "Disabled,Enabled" width 0x0B tree.end tree "BOOTROM HARDWARE INTERFACE" base ad:0xFFFEFC00 width 13. wgroup.long 0x358++0x03 line.long 0x00 "UNLOCK,Lock Release Register" group.long 0x360++0x03 line.long 0x00 "CNFG,Setting Register" bitfld.long 0x00 8. " SWAP ,Exception vector register swap bit" "No effect,Swap" rbitfld.long 0x00 0. " LST ,BootROM hardware interface lock status bit" "Unlocked,Locked" group.long 0x384++0x0F line.long 0x00 "UNDEFINACT,Undefined Instruction Vector Register" line.long 0x04 "SVCINACT,Supervisor Call Vector Register" line.long 0x08 "PABORTINACT,Prefetch Abort Vector Register" line.long 0x0C "DABORTINACT,Data Abort Vector Register" rgroup.long 0x3C4++0x0F line.long 0x00 "UNDEFACT,Undefined Instruction Vector Register" line.long 0x04 "SVCACT,Supervisor Call Vector Register" line.long 0x08 "PABORTACT,Prefetch Abort Vector Register" line.long 0x0C "DABORTACT,Data Abort Vector Register" width 0x0B tree.end tree "BOOTROM SOFTWARE INTERFACE" tree "TCM" base ad:0x009F0000 width 11. tree "SR" group.long 0x00++0x03 line.long 0x00 "MK_SER,Security Enable Marker" group.long 0x08++0x03 line.long 0x00 "MK_SSR,Security Scope Marker" group.long 0x10++0x03 line.long 0x00 "MK_CEER,Chip Erase Enable" group.long 0x18++0x03 line.long 0x00 "MK_SOER,Security Overwrite Enable Marker" group.long 0x20++0x03 line.long 0x00 "MK_SWPOER,Sector Write Permission Overwrite Enable Marker" group.long 0x28++0x03 line.long 0x00 "MK_CSWP0,Code Flash Sector Write Permissions Of The Small Sectors Marker 0" group.long 0x30++0x03 line.long 0x00 "MK_CSWP1,Code Flash Sector Write Permissions Of The Large Sectors Marker 1" group.long 0x34++0x03 line.long 0x00 "MK_CSWP2,Code Flash Sector Write Permissions Of The Large Sectors Marker 2" group.long 0x38++0x03 line.long 0x00 "MK_CSWP3,Code Flash Sector Write Permissions Of The Large Sectors Marker 3" group.long 0x3C++0x03 line.long 0x00 "MK_CSWP4,Code Flash Sector Write Permissions Of The Large Sectors Marker 4" group.long 0x40++0x03 line.long 0x00 "MK_CSWP5,Code Flash Sector Write Permissions Of The Large Sectors Marker 5" group.long 0x44++0x03 line.long 0x00 "MK_CSWP6,Code Flash Sector Write Permissions Of The Large Sectors Marker 6" group.long 0x48++0x03 line.long 0x00 "MK_CSWP7,Code Flash Sector Write Permissions Of The Large Sectors Marker 7" group.long 0x4C++0x03 line.long 0x00 "MK_CSWP8,Code Flash Sector Write Permissions Of The Large Sectors Marker 8" group.long 0x70++0x03 line.long 0x00 "MK_WSWP0,Work Flash Sector Write Permissions Marker 0" group.long 0x74++0x03 line.long 0x00 "MK_WSWP1,Work Flash Sector Write Permissions Marker 1" group.long 0x78++0x03 line.long 0x00 "MK_WSWP2,Work Flash Sector Write Permissions Marker 2" group.long 0x7C++0x03 line.long 0x00 "MK_WSWP3,Work Flash Sector Write Permissions Marker 3" tree.end width 7. tree "DDR" group.long 0x88++0x03 line.long 0x00 "DSEM,Debugger Connection Enable Marker" group.long 0x90++0x03 line.long 0x00 "DSKM0,Debugger Security Key Marker 0 (Bits 127:96)" group.long 0x98++0x03 line.long 0x00 "DSKM1,Debugger Security Key Marker 1 (Bits 95:64)" group.long 0xA0++0x03 line.long 0x00 "DSKM2,Debugger Security Key Marker 2 (Bits 63:32)" group.long 0xA8++0x03 line.long 0x00 "DSKM3,Debugger Security Key Marker 3 (Bits 31:0)" tree.end width 7. tree "BDR" group.long 0xC0++0x03 line.long 0x00 "SBMM,SHE Secure Boot Mode Marker" group.long 0xC8++0x03 line.long 0x00 "SBSM,SHE Secure Boot Size Marker" group.long 0xE0++0x03 line.long 0x00 "DWEM,Debugger Connection Wait Enable Marker" group.long 0xE8++0x03 line.long 0x00 "ABVM,Alternative Boot Vector Marker" group.long 0xF0++0x03 line.long 0x00 "ABVEM,Alternative Boot Vector Enable Marker" tree.end width 10. tree "WDR" group.long 0x100++0x03 line.long 0x00 "INTM,Hardware Watchdog Interrupt Configuration Marker" bitfld.long 0x00 17. " RSTENM ,Reset enable marker" "NMI,Reset" bitfld.long 0x00 16. " IRQENM ,Prior warning interrupt enable marker" "Disabled,Enabled" group.long 0x108++0x03 line.long 0x00 "TRG0CFGM,Hardware Watchdog Trigger 0 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFGM ,Watchdog trigger 0 configuration marker" group.long 0x110++0x03 line.long 0x00 "TRG1CFGM,Hardware Watchdog Trigger 1 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " TRG1CFGM ,Hardware watchdog trigger 1 configuration marker" group.long 0x118++0x03 line.long 0x00 "RUNLLM,Hardware Watchdog Lower Limit RUN Setting Marker" group.long 0x120++0x03 line.long 0x00 "RUNULM,Hardware Watchdog Upper Limit RUN Setting Marker" group.long 0x128++0x03 line.long 0x00 "PSSLLM,Hardware Watchdog Lower Limit PSS Setting Marker" group.long 0x130++0x03 line.long 0x00 "PSSULM,Hardware Watchdog Upper Limit PSS Setting Marker" group.long 0x138++0x03 line.long 0x00 "RSTDLYM,Hardware Watchdog Reset Delay Counter Marker" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLYM ,Reset/NMI delay counter marker" group.long 0x140++0x03 line.long 0x00 "CFGM,Hardware Watchdog Configuration Marker" bitfld.long 0x00 16.--20. " OBSSELM ,Watchdog counter monitor bit output selection marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSELM ,Clock selection marker" "High-speed,Low-speed,High-speed,Low-speed" group.long 0x148++0x03 line.long 0x00 "CEM,Hardware Watchdog Configuration Enable Marker" tree.end width 0x0B tree.end tree "AXI" base ad:0x019F0000 width 11. tree "SR" group.long 0x00++0x03 line.long 0x00 "MK_SER,Security Enable Marker" group.long 0x08++0x03 line.long 0x00 "MK_SSR,Security Scope Marker" group.long 0x10++0x03 line.long 0x00 "MK_CEER,Chip Erase Enable" group.long 0x18++0x03 line.long 0x00 "MK_SOER,Security Overwrite Enable Marker" group.long 0x20++0x03 line.long 0x00 "MK_SWPOER,Sector Write Permission Overwrite Enable Marker" group.long 0x28++0x03 line.long 0x00 "MK_CSWP0,Code Flash Sector Write Permissions Of The Small Sectors Marker 0" group.long 0x30++0x03 line.long 0x00 "MK_CSWP1,Code Flash Sector Write Permissions Of The Large Sectors Marker 1" group.long 0x34++0x03 line.long 0x00 "MK_CSWP2,Code Flash Sector Write Permissions Of The Large Sectors Marker 2" group.long 0x38++0x03 line.long 0x00 "MK_CSWP3,Code Flash Sector Write Permissions Of The Large Sectors Marker 3" group.long 0x3C++0x03 line.long 0x00 "MK_CSWP4,Code Flash Sector Write Permissions Of The Large Sectors Marker 4" group.long 0x40++0x03 line.long 0x00 "MK_CSWP5,Code Flash Sector Write Permissions Of The Large Sectors Marker 5" group.long 0x44++0x03 line.long 0x00 "MK_CSWP6,Code Flash Sector Write Permissions Of The Large Sectors Marker 6" group.long 0x48++0x03 line.long 0x00 "MK_CSWP7,Code Flash Sector Write Permissions Of The Large Sectors Marker 7" group.long 0x4C++0x03 line.long 0x00 "MK_CSWP8,Code Flash Sector Write Permissions Of The Large Sectors Marker 8" group.long 0x70++0x03 line.long 0x00 "MK_WSWP0,Work Flash Sector Write Permissions Marker 0" group.long 0x74++0x03 line.long 0x00 "MK_WSWP1,Work Flash Sector Write Permissions Marker 1" group.long 0x78++0x03 line.long 0x00 "MK_WSWP2,Work Flash Sector Write Permissions Marker 2" group.long 0x7C++0x03 line.long 0x00 "MK_WSWP3,Work Flash Sector Write Permissions Marker 3" tree.end width 7. tree "DDR" group.long 0x88++0x03 line.long 0x00 "DSEM,Debugger Connection Enable Marker" group.long 0x90++0x03 line.long 0x00 "DSKM0,Debugger Security Key Marker 0 (Bits 127:96)" group.long 0x98++0x03 line.long 0x00 "DSKM1,Debugger Security Key Marker 1 (Bits 95:64)" group.long 0xA0++0x03 line.long 0x00 "DSKM2,Debugger Security Key Marker 2 (Bits 63:32)" group.long 0xA8++0x03 line.long 0x00 "DSKM3,Debugger Security Key Marker 3 (Bits 31:0)" tree.end width 7. tree "BDR" group.long 0xC0++0x03 line.long 0x00 "SBMM,SHE Secure Boot Mode Marker" group.long 0xC8++0x03 line.long 0x00 "SBSM,SHE Secure Boot Size Marker" group.long 0xE0++0x03 line.long 0x00 "DWEM,Debugger Connection Wait Enable Marker" group.long 0xE8++0x03 line.long 0x00 "ABVM,Alternative Boot Vector Marker" group.long 0xF0++0x03 line.long 0x00 "ABVEM,Alternative Boot Vector Enable Marker" tree.end width 10. tree "WDR" group.long 0x100++0x03 line.long 0x00 "INTM,Hardware Watchdog Interrupt Configuration Marker" bitfld.long 0x00 17. " RSTENM ,Reset enable marker" "NMI,Reset" bitfld.long 0x00 16. " IRQENM ,Prior warning interrupt enable marker" "Disabled,Enabled" group.long 0x108++0x03 line.long 0x00 "TRG0CFGM,Hardware Watchdog Trigger 0 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFGM ,Watchdog trigger 0 configuration marker" group.long 0x110++0x03 line.long 0x00 "TRG1CFGM,Hardware Watchdog Trigger 1 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " TRG1CFGM ,Hardware watchdog trigger 1 configuration marker" group.long 0x118++0x03 line.long 0x00 "RUNLLM,Hardware Watchdog Lower Limit RUN Setting Marker" group.long 0x120++0x03 line.long 0x00 "RUNULM,Hardware Watchdog Upper Limit RUN Setting Marker" group.long 0x128++0x03 line.long 0x00 "PSSLLM,Hardware Watchdog Lower Limit PSS Setting Marker" group.long 0x130++0x03 line.long 0x00 "PSSULM,Hardware Watchdog Upper Limit PSS Setting Marker" group.long 0x138++0x03 line.long 0x00 "RSTDLYM,Hardware Watchdog Reset Delay Counter Marker" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLYM ,Reset/NMI delay counter marker" group.long 0x140++0x03 line.long 0x00 "CFGM,Hardware Watchdog Configuration Marker" bitfld.long 0x00 16.--20. " OBSSELM ,Watchdog counter monitor bit output selection marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSELM ,Clock selection marker" "High-speed,Low-speed,High-speed,Low-speed" group.long 0x148++0x03 line.long 0x00 "CEM,Hardware Watchdog Configuration Enable Marker" tree.end width 0x0B tree.end tree.end tree "INTC (INTERRUPT CONTROLER)" base ad:0xB0400000 sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) width 10. rgroup.long 0x0++0x03 line.long 0x00 "NMIVAS,IRC NMI vector address status register" rgroup.long 0x4++0x3 line.long 0x00 "NMIST,IRC NMI Status register" bitfld.long 0x00 8.--11. " NMIPS ,NMI priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("S6J335*")) bitfld.long 0x00 0.--5. " NMISN ,NMI channel number bits" "0,,,,4,5,6,7,8,,,11,12,13,,15,,,18,?..." elif (cpuis("S6J334*")) bitfld.long 0x00 0.--5. " NMISN ,NMI channel number bits" "0,,,,4,5,6,7,8,,,11,12,13,,15,,,18,,20,21,?..." elif (cpuis("S6J333*")||cpuis("S6J332*")||cpuis("S6J331*")) bitfld.long 0x00 0.--5. " NMISN ,NMI channel number bits" "0,,,,4,5,6,7,8,,,11,12,13,,15,,,18,,20,21,22,23,?..." else bitfld.long 0x00 0.--5. " NMISN ,NMI channel number bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." endif rgroup.long 0x8++0x3 line.long 0x00 "IRQVAS,IRC IRQ vector address status register" rgroup.long 0xC++0x3 line.long 0x00 "IRQST,IRC IRQ status register" bitfld.long 0x00 24. " NIRQ ,IRQ interrupt status bit" "No interrupt,Interrupt" bitfld.long 0x00 16.--20. " IRQPS ,IRQ priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. " IRQSN ,IRQ channel number bits" tree "NMI vector address registers" group.long 0x10++0x3 line.long 0x00 "NMIVA0,(NMIX pin (Ext-IRC)) IRQ NMI vector address register" group.long 0x20++0x3 line.long 0x00 "NMIVA4,(LVDs IRQ) IRQ NMI vector address register" group.long 0x24++0x3 line.long 0x00 "NMIVA5,(CSV Profile) IRQ NMI vector address register" group.long 0x28++0x3 line.long 0x00 "NMIVA6,(HW-WDT) IRQ NMI vector address register" group.long 0x2C++0x3 line.long 0x00 "NMIVA7,(SW-WDT) IRQ NMI vector address register" group.long 0x30++0x3 line.long 0x00 "NMIVA8,(IRC 2-bit ECC error detection) IRQ NMI vector address register" group.long 0x3C++0x3 line.long 0x00 "NMIVA11,(Backup RAM 2-bit ECC error detection) IRQ NMI vector address register" group.long 0x40++0x3 line.long 0x00 "NMIVA12,(M-CAN RAMs 2-bit ECC error detection) IRQ NMI vector address register" group.long 0x44++0x3 line.long 0x00 "NMIVA13,(DMAC MPU #0 protection violation) IRQ NMI vector address register" sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") group.long 0x48++0x3 line.long 0x00 "NMIVA14,(DMAC MPU #1 protection violation) IRQ NMI vector address register" endif group.long 0x4C++0x3 line.long 0x00 "NMIVA15,(SHE MPU) IRQ NMI vector address register" group.long 0x58++0x3 line.long 0x00 "NMIVA18,(TPU protection violation) IRQ NMI vector address register" sif (!cpuis("S6J335*")) group.long 0x60++0x3 line.long 0x00 "NMIVA20,(2d Graphics Core_NMI[0]) IRQ NMI vector address register" group.long 0x64++0x3 line.long 0x00 "NMIVA21,(2d Graphics Core_NMI[1]) IRQ NMI vector address register" sif (!cpuis("S6J334*")) group.long 0x68++0x3 line.long 0x00 "NMIVA22,(MLB_MPU_NMI) IRQ NMI vector address register" group.long 0x6C++0x3 line.long 0x00 "NMIVA23,(ETHERNET_PMU_NMI) IRQ NMI vector address register" endif endif tree.end tree "IRQ vector address registers" group.long 0x94++0x3 line.long 0x00 "IRQVA1,(System Control Status) IRQ vector address register" group.long 0x98++0x3 line.long 0x00 "IRQVA2,(HW-WDT Pre-warning) IRQ vector address register" group.long 0x9C++0x3 line.long 0x00 "IRQVA3,(SW-WDT Pre-warning) IRQ vector address register" group.long 0xB0++0x3 line.long 0x00 "IRQVA8,(TCFLASH Single Bit Error ) IRQ vector address register" group.long 0xB8++0x3 line.long 0x00 "IRQVA10,(Work FLASH Single Bit Error) IRQ vector address register" group.long 0xC8++0x3 line.long 0x00 "IRQVA14,(System RAM Single Bit Error) IRQ vector address register" group.long 0xCC++0x3 line.long 0x00 "IRQVA15,(Backup RAM/CAN FD RAM(ch. 0,1,5,6) Single Bit Error) IRQ vector address register" group.long 0xD0++0x3 line.long 0x00 "IRQVA16,(IRC Vector Address Ram Single Bit Error) IRQ vector address register" group.long 0xE0++0x3 line.long 0x00 "IRQVA20,(Work FLASH Write Completion) IRQ vector address register" group.long 0xEC++0x3 line.long 0x00 "IRQVA23,(EICU) IRQ vector address register" group.long 0xF0++0x3 line.long 0x00 "IRQVA24,(External Interrupt Request ch.0) IRQ vector address register" group.long 0xF4++0x3 line.long 0x00 "IRQVA25,(External Interrupt Request ch.1) IRQ vector address register" group.long 0xF8++0x3 line.long 0x00 "IRQVA26,(External Interrupt Request ch.2) IRQ vector address register" group.long 0xFC++0x3 line.long 0x00 "IRQVA27,(External Interrupt Request ch.3) IRQ vector address register" group.long 0x100++0x3 line.long 0x00 "IRQVA28,(External Interrupt Request ch.4) IRQ vector address register" group.long 0x104++0x3 line.long 0x00 "IRQVA29,(External Interrupt Request ch.5) IRQ vector address register" group.long 0x108++0x3 line.long 0x00 "IRQVA30,(External Interrupt Request ch.6) IRQ vector address register" group.long 0x10C++0x3 line.long 0x00 "IRQVA31,(External Interrupt Request ch.7) IRQ vector address register" group.long 0x110++0x3 line.long 0x00 "IRQVA32,(External Interrupt Request ch.8) IRQ vector address register" group.long 0x114++0x3 line.long 0x00 "IRQVA33,(External Interrupt Request ch.9) IRQ vector address register" group.long 0x118++0x3 line.long 0x00 "IRQVA34,(External Interrupt Request ch.10) IRQ vector address register" group.long 0x11C++0x3 line.long 0x00 "IRQVA35,(External Interrupt Request ch.11) IRQ vector address register" group.long 0x120++0x3 line.long 0x00 "IRQVA36,(External Interrupt Request ch.12) IRQ vector address register" group.long 0x124++0x3 line.long 0x00 "IRQVA37,(External Interrupt Request ch.13) IRQ vector address register" group.long 0x128++0x3 line.long 0x00 "IRQVA38,(External Interrupt Request ch.14) IRQ vector address register" group.long 0x12C++0x3 line.long 0x00 "IRQVA39,(External Interrupt Request ch.15) IRQ vector address register" group.long 0x130++0x3 line.long 0x00 "IRQVA40,(MFS RX ch.16 IRQ) vector address register" group.long 0x134++0x3 line.long 0x00 "IRQVA41,(MFS TX ch.16 IRQ) vector address register" group.long 0x138++0x3 line.long 0x00 "IRQVA42,(MFS RX ch.17 IRQ) vector address register" group.long 0x13C++0x3 line.long 0x00 "IRQVA43,(MFS TX ch.17 IRQ) vector address register" group.long 0x148++0x3 line.long 0x00 "IRQVA46,(Reload Timer ch.48,49 OR-ed) IRQ vector address register" group.long 0x150++0x3 line.long 0x00 "IRQVA48,(CANFD ch.5) IRQ vector address register" sif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) group.long 0x154++0x3 line.long 0x00 "IRQVA49,(CANFD ch.6) IRQ vector address register" endif sif (cpuis("S6J335*")) group.long 0x158++0x3 line.long 0x00 "IRQVA50,(CANFD ch.7) IRQ vector address register" endif group.long 0x170++0x3 line.long 0x00 "IRQVA56,(CANFD ch.0) IRQ vector address register" group.long 0x174++0x3 line.long 0x00 "IRQVA57,(CANFD ch.1) IRQ vector address register" sif (cpuis("S6J33*")) group.long 0x178++0x3 line.long 0x00 "IRQVA58,(CANFD ch.2) IRQ vector address register" group.long 0x17C++0x3 line.long 0x00 "IRQVA59,(CANFD ch.3) IRQ vector address register" group.long 0x180++0x3 line.long 0x00 "IRQVA60,(CANFD ch.4) IRQ vector address register" endif group.long 0x190++0x3 line.long 0x00 "IRQVA64,(M.F.S RX ch.0) IRQ vector address register" group.long 0x194++0x3 line.long 0x00 "IRQVA65,(M.F.S TX ch.0) IRQ vector address register" group.long 0x198++0x3 line.long 0x00 "IRQVA66,(M.F.S Rx ch.1) IRQ vector address register" group.long 0x19C++0x3 line.long 0x00 "IRQVA67,(M.F.S TX ch.1) IRQ vector address register" group.long 0x1A0++0x3 line.long 0x00 "IRQVA68,(M.F.S Rx ch.2) IRQ vector address register" group.long 0x1A4++0x3 line.long 0x00 "IRQVA69,(M.F.S TX ch.2) IRQ vector address register" group.long 0x1A8++0x3 line.long 0x00 "IRQVA70,(M.F.S Rx ch.3) IRQ vector address register" group.long 0x1AC++0x3 line.long 0x00 "IRQVA71,(M.F.S TX ch.3) IRQ vector address register" group.long 0x1B0++0x3 line.long 0x00 "IRQVA72,(M.F.S Rx ch.4) IRQ vector address register" group.long 0x1B4++0x3 line.long 0x00 "IRQVA73,(M.F.S TX ch.4) IRQ vector address register" group.long 0x1D0++0x3 line.long 0x00 "IRQVA80,(MFS RX ch.8) IRQ vector address register" group.long 0x1D4++0x3 line.long 0x00 "IRQVA81,(MFS TX ch.8)IRQ vector address register" group.long 0x1D8++0x3 line.long 0x00 "IRQVA82,(MFS RX ch.9)IRQ vector address register" group.long 0x1DC++0x3 line.long 0x00 "IRQVA83,(MFS TX ch.9)IRQ vector address register" group.long 0x1E0++0x3 line.long 0x00 "IRQVA84,(MFS RX ch.10)IRQ vector address register" group.long 0x1E4++0x3 line.long 0x00 "IRQVA85,(MFS TX ch.10)IRQ vector address register" group.long 0x1E8++0x3 line.long 0x00 "IRQVA86,(MFS RX ch.11)IRQ vector address register" group.long 0x1EC++0x3 line.long 0x00 "IRQVA87,(MFS TX ch.11)IRQ vector address register" group.long 0x1F0++0x3 line.long 0x00 "IRQVA88,(MFS RX ch.12)IRQ vector address register" group.long 0x1F4++0x3 line.long 0x00 "IRQVA89,(MFS TX ch.12)IRQ vector address register" group.long 0x220++0x3 line.long 0x00 "IRQVA100,(SHE Err) IRQ vector address register" group.long 0x224++0x3 line.long 0x00 "IRQVA101,(SHE) IRQ vector address register" group.long 0x228++0x3 line.long 0x00 "IRQVA102,(DDR HSSPI RX) IRQ vector address register" group.long 0x22C++0x3 line.long 0x00 "IRQVA103,(DDR HSSPI TX) IRQ vector address register" group.long 0x248++0x3 line.long 0x00 "IRQVA110,(TCRAM) IRQ vector address register" group.long 0x250++0x3 line.long 0x00 "IRQVA112,(Backup RAM) IRQ vector address register" group.long 0x260++0x3 line.long 0x00 "IRQVA116,(RTC) IRQ vector address register" group.long 0x264++0x3 line.long 0x00 "IRQVA117,(CR calibration) IRQ vector address register" group.long 0x290++0x3 line.long 0x00 "IRQVA128,(Base Timer ch.0/8/9/10/11) IRQ vector address register" group.long 0x294++0x3 line.long 0x00 "IRQVA129,(Base Timer ch.1) IRQ vector address register" group.long 0x298++0x3 line.long 0x00 "IRQVA130,(Base Timer ch.2) IRQ vector address register" group.long 0x29C++0x3 line.long 0x00 "IRQVA131,(Base Timer ch.3) IRQ vector address register" group.long 0x2A0++0x3 line.long 0x00 "IRQVA132,(Base Timer ch.4) IRQ vector address register" group.long 0x2A4++0x3 line.long 0x00 "IRQVA133,(Base Timer ch.5) IRQ vector address register" group.long 0x2A8++0x3 line.long 0x00 "IRQVA134,(Base Timer ch.6) IRQ vector address register" group.long 0x2AC++0x3 line.long 0x00 "IRQVA135,(Base Timer ch.7) IRQ vector address register" group.long 0x2B0++0x3 line.long 0x00 "IRQVA136,(Base Timer ch.12/20/21/22/23) IRQ vector address register" group.long 0x2B4++0x3 line.long 0x00 "IRQVA137,(Base Timer ch.13) IRQ vector address register" group.long 0x2B8++0x3 line.long 0x00 "IRQVA138,(Base Timer ch.14) IRQ vector address register" group.long 0x2BC++0x3 line.long 0x00 "IRQVA139,(Base Timer ch.15) IRQ vector address register" group.long 0x2C0++0x3 line.long 0x00 "IRQVA140,(Base Timer ch.16) IRQ vector address register" group.long 0x2C4++0x3 line.long 0x00 "IRQVA141,(Base Timer ch.17) IRQ vector address register" group.long 0x2C8++0x3 line.long 0x00 "IRQVA142,(Base Timer ch.18) IRQ vector address register" group.long 0x2CC++0x3 line.long 0x00 "IRQVA143,(Base Timer ch.19) IRQ vector address register" group.long 0x2F0++0x3 line.long 0x00 "IRQVA152,(Reload Timer ch.0) IRQ vector address register" group.long 0x2F4++0x3 line.long 0x00 "IRQVA153,(Reload Timer ch.1) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x2F8++0x3 line.long 0x00 "IRQVA154,(Reload Timer ch.2) IRQ vector address register" group.long 0x2FC++0x3 line.long 0x00 "IRQVA155,(Reload Timer ch.3) IRQ vector address register" endif group.long 0x310++0x3 line.long 0x00 "IRQVA160,(Reload Timer ch.16) IRQ vector address register" group.long 0x314++0x3 line.long 0x00 "IRQVA161,(Reload Timer ch.17) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x318++0x3 line.long 0x00 "IRQVA162,(Reload Timer ch.18) IRQ vector address register" group.long 0x31C++0x3 line.long 0x00 "IRQVA163,(Reload Timer ch.19) IRQ vector address register" group.long 0x330++0x3 line.long 0x00 "IRQVA168,(Reload Timer ch.32) IRQ vector address register" group.long 0x334++0x3 line.long 0x00 "IRQVA169,(Reload Timer ch.33) IRQ vector address register" group.long 0x338++0x3 line.long 0x00 "IRQVA170,(Reload Timer ch.34) IRQ vector address register" group.long 0x33C++0x3 line.long 0x00 "IRQVA171,(Reload Timer ch.35) IRQ vector address register" endif group.long 0x350++0x3 line.long 0x00 "IRQVA176,(FRT ch.0) IRQ vector address register" group.long 0x354++0x3 line.long 0x00 "IRQVA177,(FRT ch.1) IRQ vector address register" group.long 0x358++0x3 line.long 0x00 "IRQVA178,(FRT ch.2) IRQ vector address register" group.long 0x35C++0x3 line.long 0x00 "IRQVA179,(FRT ch.3) IRQ vector address register" group.long 0x360++0x3 line.long 0x00 "IRQVA180,(FRT ch.4) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x364++0x3 line.long 0x00 "IRQVA181,(FRT ch.5) IRQ vector address register" group.long 0x368++0x3 line.long 0x00 "IRQVA182,(FRT ch.6) IRQ vector address register" group.long 0x36C++0x3 line.long 0x00 "IRQVA183,(FRT ch.7) IRQ vector address register" endif group.long 0x370++0x3 line.long 0x00 "IRQVA184,(FRT ch.8) IRQ vector address register" group.long 0x374++0x3 line.long 0x00 "IRQVA185,(FRT ch.9) IRQ vector address register" group.long 0x378++0x3 line.long 0x00 "IRQVA186,(FRT ch.10) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x37C++0x3 line.long 0x00 "IRQVA187,(FRT ch.11) IRQ vector address register" endif group.long 0x390++0x3 line.long 0x00 "IRQVA192,(ICU ch.0) IRQ vector address register" group.long 0x394++0x3 line.long 0x00 "IRQVA193,(ICU ch.1) IRQ vector address register" group.long 0x398++0x3 line.long 0x00 "IRQVA194,(ICU ch.2) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x39C++0x3 line.long 0x00 "IRQVA195,(ICU ch.3) IRQ vector address register" group.long 0x3A0++0x3 line.long 0x00 "IRQVA196,(ICU ch.4) IRQ vector address register" group.long 0x3A4++0x3 line.long 0x00 "IRQVA197,(ICU ch.5) IRQ vector address register" group.long 0x3A8++0x3 line.long 0x00 "IRQVA198,(ICU ch.6) IRQ vector address register" group.long 0x3AC++0x3 line.long 0x00 "IRQVA199,(ICU ch.7) IRQ vector address register" endif group.long 0x3B0++0x3 line.long 0x00 "IRQVA200,(ICU ch.8) IRQ vector address register" group.long 0x3B4++0x3 line.long 0x00 "IRQVA201,(ICU ch.9) IRQ vector address register" group.long 0x3B8++0x3 line.long 0x00 "IRQVA202,(ICU ch.10) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x3BC++0x3 line.long 0x00 "IRQVA203,(ICU ch.11) IRQ vector address register" endif group.long 0x3D0++0x3 line.long 0x00 "IRQVA208,(OCU ch.0) IRQ vector address register" group.long 0x3D4++0x3 line.long 0x00 "IRQVA209,(OCU ch.1) IRQ vector address register" group.long 0x3D8++0x3 line.long 0x00 "IRQVA210,(OCU ch.2) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x3DC++0x3 line.long 0x00 "IRQVA211,(OCU ch.3) IRQ vector address register" group.long 0x3E0++0x3 line.long 0x00 "IRQVA212,(OCU ch.4) IRQ vector address register" group.long 0x3E4++0x3 line.long 0x00 "IRQVA213,(OCU ch.5) IRQ vector address register" group.long 0x3E8++0x3 line.long 0x00 "IRQVA214,(OCU ch.6) IRQ vector address register" group.long 0x3EC++0x3 line.long 0x00 "IRQVA215,(OCU ch.7) IRQ vector address register" endif group.long 0x3F0++0x3 line.long 0x00 "IRQVA216,(OCU ch.8) IRQ vector address register" group.long 0x3F4++0x3 line.long 0x00 "IRQVA217,(OCU ch.9) IRQ vector address register" group.long 0x3F8++0x3 line.long 0x00 "IRQVA218,(OCU ch.10) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x3FC++0x3 line.long 0x00 "IRQVA219,(OCU ch.11) IRQ vector address register" endif group.long 0x430++0x3 line.long 0x00 "IRQVA232,(QPRC ch.8) IRQ vector address register" group.long 0x434++0x3 line.long 0x00 "IRQVA233,(QPRC ch.9) IRQ vector address register" group.long 0x450++0x3 line.long 0x00 "IRQVA240,(ICU ch.0) IRQ vector address register" group.long 0x454++0x3 line.long 0x00 "IRQVA241,(ICU ch.1) IRQ vector address register" group.long 0x458++0x3 line.long 0x00 "IRQVA242,(ICU ch.2) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x45C++0x3 line.long 0x00 "IRQVA243,(ICU ch.3) IRQ vector address register" group.long 0x460++0x3 line.long 0x00 "IRQVA244,(ICU ch.4) IRQ vector address register" group.long 0x464++0x3 line.long 0x00 "IRQVA245,(ICU ch.5) IRQ vector address register" group.long 0x468++0x3 line.long 0x00 "IRQVA246,(ICU ch.6) IRQ vector address register" group.long 0x46C++0x3 line.long 0x00 "IRQVA247,(ICU ch.7) IRQ vector address register" endif group.long 0x470++0x3 line.long 0x00 "IRQVA248,(ICU ch.8) IRQ vector address register" group.long 0x474++0x3 line.long 0x00 "IRQVA249,(ICU ch.9) IRQ vector address register" group.long 0x478++0x3 line.long 0x00 "IRQVA250,(ICU ch.10) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x47C++0x3 line.long 0x00 "IRQVA251,(ICU ch.11) IRQ vector address register" endif group.long 0x490++0x3 line.long 0x00 "IRQVA256,(OCU ch.0) IRQ vector address register" group.long 0x494++0x3 line.long 0x00 "IRQVA257,(OCU ch.1) IRQ vector address register" group.long 0x498++0x3 line.long 0x00 "IRQVA258,(OCU ch.2) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x49C++0x3 line.long 0x00 "IRQVA259,(OCU ch.3) IRQ vector address register" group.long 0x4A0++0x3 line.long 0x00 "IRQVA260,(OCU ch.4) IRQ vector address register" group.long 0x4A4++0x3 line.long 0x00 "IRQVA261,(OCU ch.5) IRQ vector address register" group.long 0x4A8++0x3 line.long 0x00 "IRQVA262,(OCU ch.6) IRQ vector address register" group.long 0x4AC++0x3 line.long 0x00 "IRQVA263,(OCU ch.7) IRQ vector address register" endif group.long 0x4B0++0x3 line.long 0x00 "IRQVA264,(OCU ch.8) IRQ vector address register" group.long 0x4B4++0x3 line.long 0x00 "IRQVA265,(OCU ch.9) IRQ vector address register" group.long 0x4B8++0x3 line.long 0x00 "IRQVA266,(OCU ch.10) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x4BC++0x3 line.long 0x00 "IRQVA267,(OCU ch.11) IRQ vector address register" endif group.long 0x4D0++0x3 line.long 0x00 "IRQVA272,(DMA Error) IRQ vector address register" group.long 0x4D4++0x3 line.long 0x00 "IRQVA273,(DMA Completion ch.0) IRQ vector address register" group.long 0x4D8++0x3 line.long 0x00 "IRQVA274,(DMA Completion ch.1) IRQ vector address register" group.long 0x4DC++0x3 line.long 0x00 "IRQVA275,(DMA Completion ch.2) IRQ vector address register" group.long 0x4E0++0x3 line.long 0x00 "IRQVA276,(DMA Completion ch.3) IRQ vector address register" group.long 0x4E4++0x3 line.long 0x00 "IRQVA277,(DMA Completion ch.4) IRQ vector address register" group.long 0x4E8++0x3 line.long 0x00 "IRQVA278,(DMA Completion ch.5) IRQ vector address register" group.long 0x4EC++0x3 line.long 0x00 "IRQVA279,(DMA Completion ch.6) IRQ vector address register" group.long 0x4F0++0x3 line.long 0x00 "IRQVA280,(DMA Completion ch.7) IRQ vector address register" group.long 0x4F8++0x3 line.long 0x00 "IRQVA282,(DMAC RLT ch.0/1/2/3, OR-ed) IRQ vector address register" group.long 0x504++0x3 line.long 0x00 "IRQVA285,(DMA Completion ch.8) IRQ vector address register" group.long 0x508++0x3 line.long 0x00 "IRQVA286,(DMA Completion ch.9) IRQ vector address register" group.long 0x50C++0x3 line.long 0x00 "IRQVA287,(DMA Completion ch.10) IRQ vector address register" group.long 0x510++0x3 line.long 0x00 "IRQVA288,(DMA Completion ch.11) IRQ vector address register" group.long 0x514++0x3 line.long 0x00 "IRQVA289,(DMA Completion ch.12) IRQ vector address register" group.long 0x518++0x3 line.long 0x00 "IRQVA290,(DMA Completion ch.13) IRQ vector address register" group.long 0x51C++0x3 line.long 0x00 "IRQVA291,(DMA Completion ch.14) IRQ vector address register" group.long 0x520++0x3 line.long 0x00 "IRQVA292,(DMA Completion ch.15) IRQ vector address register" group.long 0x560++0x3 line.long 0x00 "IRQVA308,(SCT CR IRQ) IRQ vector address register" group.long 0x564++0x3 line.long 0x00 "IRQVA309,(SCT SRC IRQ) IRQ vector address register" group.long 0x568++0x3 line.long 0x00 "IRQVA310,(SCT Main OSC IRQ) IRQ vector address register" group.long 0x56C++0x3 line.long 0x00 "IRQVA311,(SCT Sub OSC IRQ) IRQ vector address register" group.long 0x570++0x3 line.long 0x00 "IRQVA312,(CR5 Performance Monitor Unit IRQ) IRQ vector address register" group.long 0x590++0x3 line.long 0x00 "IRQVA320,(M.F.S Error ch.0) IRQ vector address register" group.long 0x594++0x3 line.long 0x00 "IRQVA321,(M.F.S Error ch.1) IRQ vector address register" group.long 0x598++0x3 line.long 0x00 "IRQVA322,(M.F.S Error ch.2) IRQ vector address register" group.long 0x59C++0x3 line.long 0x00 "IRQVA323,(M.F.S Error ch.3) IRQ vector address register" group.long 0x5A0++0x3 line.long 0x00 "IRQVA324,(M.F.S Error ch.4) IRQ vector address register" group.long 0x5B0++0x3 line.long 0x00 "IRQVA328,(M.F.S Error ch.8) IRQ vector address register" group.long 0x5B4++0x3 line.long 0x00 "IRQVA329,(M.F.S Error ch.9) IRQ vector address register" group.long 0x5B8++0x3 line.long 0x00 "IRQVA330,(M.F.S Error ch.10) IRQ vector address register" group.long 0x5BC++0x3 line.long 0x00 "IRQVA331,(M.F.S Error ch.11) IRQ vector address register" group.long 0x5C0++0x3 line.long 0x00 "IRQVA332,(M.F.S Error ch.12) IRQ vector address register" group.long 0x5D0++0x3 line.long 0x00 "IRQVA336,(M.F.S Error ch.16) IRQ vector address register" group.long 0x5D4++0x3 line.long 0x00 "IRQVA337,(M.F.S Error ch.17) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x5DC++0x3 line.long 0x00 "IRQVA339,(SMC ch.0) IRQ vector address register" group.long 0x5E0++0x3 line.long 0x00 "IRQVA340,(SMC ch.1) IRQ vector address register" group.long 0x5E4++0x3 line.long 0x00 "IRQVA341,(SMC ch.2) IRQ vector address register" group.long 0x5E8++0x3 line.long 0x00 "IRQVA342,(SMC ch.3) IRQ vector address register" group.long 0x5EC++0x3 line.long 0x00 "IRQVA343,(SMC ch.4) IRQ vector address register" group.long 0x5F0++0x3 line.long 0x00 "IRQVA344,(SMC ch.5) IRQ vector address register" endif sif (!cpuis("S6J335*")) group.long 0x5FC++0x3 line.long 0x00 "IRQVA347,(SG ch.0) IRQ vector address register" group.long 0x600++0x3 line.long 0x00 "IRQVA348,(SG ch.1) IRQ vector address register" group.long 0x604++0x3 line.long 0x00 "IRQVA349,(SG ch.2) IRQ vector address register" group.long 0x608++0x3 line.long 0x00 "IRQVA350,(SG ch.3) IRQ vector address register" sif (cpuis("S6J33*")) group.long 0x60C++0x3 line.long 0x00 "IRQVA351,(SG ch.4) IRQ vector address register" endif endif group.long 0x614++0x3 line.long 0x00 "IRQVA353,(ADC12B Conversion Done) IRQ vector address register" group.long 0x618++0x3 line.long 0x00 "IRQVA354,(ADC12B Group interrupt) IRQ vector address register" group.long 0x61C++0x3 line.long 0x00 "IRQVA355,(ADC12B pulse detection function) IRQ vector address register" group.long 0x620++0x3 line.long 0x00 "IRQVA356,(ADC12B RCO) IRQ vector address register" group.long 0x624++0x3 line.long 0x00 "IRQVA357,(RPGCRC) IRQ vector address register" sif (!cpuis("S6J334*")) group.long 0x62C++0x3 line.long 0x00 "IRQVA359,(MLB channel interrupt) IRQ vector address register" group.long 0x630++0x3 line.long 0x00 "IRQVA360,(MLB system interrupt) IRQ vector address register" group.long 0x634++0x3 line.long 0x00 "IRQVA361,(ETHERNET IRQ) IRQ vector address register" group.long 0x638++0x3 line.long 0x00 "IRQVA362,(ETHERNET Q1 IRQ) IRQ vector address register" group.long 0x63C++0x3 line.long 0x00 "IRQVA363,(ETHERNET Q2 IRQ) IRQ vector address register" group.long 0x640++0x3 line.long 0x00 "IRQVA364,(ETHERNET Q3 IRQ) IRQ vector address register" endif group.long 0x650++0x3 line.long 0x00 "IRQVA368,(Indicator PWM) IRQ vector address register" sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) group.long 0x654++0x3 line.long 0x00 "IRQVA369,(PCMPWM_DREQ) IRQ vector address register" group.long 0x658++0x3 line.long 0x00 "IRQVA370,(PCMPWM_OVFL) IRQ vector address register" group.long 0x65C++0x3 line.long 0x00 "IRQVA371,(PCMPWM_UDRN) IRQ vector address register" group.long 0x660++0x3 line.long 0x00 "IRQVA372,(PCMPWM_DMAE) IRQ vector address register" group.long 0x664++0x3 line.long 0x00 "IRQVA373,(AUDIO_DAC_DREQ) IRQ vector address register" group.long 0x668++0x3 line.long 0x00 "IRQVA374,(AUDIO_DAC_OVFL_IRQ) IRQ vector address register" group.long 0x66C++0x3 line.long 0x00 "IRQVA375,(AUDIO_DAC_UDRN_IRQ) IRQ vector address register" group.long 0x670++0x3 line.long 0x00 "IRQVA376,(AUDIO_DAC_DMAE_IRQ) IRQ vector address register" endif sif (!cpuis("S6J335*")) group.long 0x674++0x3 line.long 0x00 "IRQVA377,(I2S0_IRQ) IRQ vector address register" group.long 0x678++0x3 line.long 0x00 "IRQVA378,(I2S1_IRQ) IRQ vector address register" endif sif (cpuis("S6J33*")) group.long 0x6A0++0x3 sif (cpuis("S6J335*")) line.long 0x00 "IRQVA388,(Base Timer ch.24/32/33/34/35) IRQ vector address register" else line.long 0x00 "IRQVA388,(Base Timer ch.24) IRQ vector address register" endif group.long 0x6A4++0x3 line.long 0x00 "IRQVA389,(Base Timer ch.25) IRQ vector address register" group.long 0x6A8++0x3 line.long 0x00 "IRQVA390,(Base Timer ch.26) IRQ vector address register" group.long 0x6AC++0x3 line.long 0x00 "IRQVA391,(Base Timer ch.27) IRQ vector address register" group.long 0x6B0++0x3 line.long 0x00 "IRQVA392,(Base Timer ch.28) IRQ vector address register" group.long 0x6B4++0x3 line.long 0x00 "IRQVA393,(Base Timer ch.29) IRQ vector address register" group.long 0x6B8++0x3 line.long 0x00 "IRQVA394,(Base Timer ch.30) IRQ vector address register" group.long 0x6BC++0x3 line.long 0x00 "IRQVA395,(Base Timer ch.31) IRQ vector address register" endif sif (!cpuis("S6J335*")) group.long 0x6D4++0x3 line.long 0x00 "IRQVA401,(2D Graphics Core Command Sequencer) IRQ vector address register" group.long 0x6D8++0x3 line.long 0x00 "IRQVA402,(2D Graphics Core Blit Engine) IRQ vector address register" group.long 0x6DC++0x3 line.long 0x00 "IRQVA403,(2D Graphics Core Drawing Engine) IRQ vector address register" group.long 0x6E0++0x3 line.long 0x00 "IRQVA404,(2D Graphics Core Content Stream0) IRQ vector address register" group.long 0x6E4++0x3 line.long 0x00 "IRQVA405,(2D Graphics Core Safety Stream0) IRQ vector address register" group.long 0x6E8++0x3 line.long 0x00 "IRQVA406,(2D Graphics Core Display Stream0) IRQ vector address register" group.long 0x6EC++0x3 line.long 0x00 "IRQVA407,(2D Graphics Core Signature0) IRQ vector address register" group.long 0x6F0++0x3 line.long 0x00 "IRQVA408,(2D Graphics Core Display0 Sync0) IRQ vector address register" group.long 0x6F4++0x3 line.long 0x00 "IRQVA409,(2D Graphics Core Display0 Sync1) IRQ vector address register" sif (!cpuis("S6J33*")) group.long 0x6F8++0x3 line.long 0x00 "IRQVA410,(2D Graphics Core Content Stream1) IRQ vector address register" group.long 0x6FC++0x3 line.long 0x00 "IRQVA411,(2D Graphics Core Safety Stream1) IRQ vector address register" group.long 0x700++0x3 line.long 0x00 "IRQVA412,(2D Graphics Core Display Stream1) IRQ vector address register" group.long 0x704++0x3 line.long 0x00 "IRQVA413,(2D Graphics Core Signature1) IRQ vector address register" group.long 0x708++0x3 line.long 0x00 "IRQVA414,(2D Graphics Core Display1 Sync0) IRQ vector address register" group.long 0x70C++0x3 line.long 0x00 "IRQVA415,(2D Graphics Core Display1 Sync1) IRQ vector address register" group.long 0x710++0x3 line.long 0x00 "IRQVA416,(2D Graphics Core Capture Plane0) IRQ vector address register" group.long 0x714++0x3 line.long 0x00 "IRQVA417,(2D Graphics Core Display Plane0) IRQ vector address register" group.long 0x718++0x3 line.long 0x00 "IRQVA418,(2D Graphics Core Storage Stream0) IRQ vector address register" group.long 0x71C++0x3 line.long 0x00 "IRQVA419,(2D Graphics Core Histogram) IRQ vector address register" group.long 0x720++0x3 line.long 0x00 "IRQVA420,(2D Graphics Core DDRHSSPI) IRQ vector address register" group.long 0x724++0x3 line.long 0x00 "IRQVA421,(3D Graphics Core SRUI) IRQ vector address register" group.long 0x728++0x3 line.long 0x00 "IRQVA422,(3D Graphics Core LINI) IRQ vector address register" group.long 0x72C++0x3 line.long 0x00 "IRQVA423,(3D Graphics Core DFI) IRQ vector address register" group.long 0x730++0x3 line.long 0x00 "IRQVA424,(3D Graphics Core DLEI) IRQ vector address register" group.long 0x734++0x3 line.long 0x00 "IRQVA425,(3D Graphics Core DEI) IRQ vector address register" group.long 0x738++0x3 line.long 0x00 "IRQVA426,(3D Graphics Core CAEI) IRQ vector address register" group.long 0x73C++0x3 line.long 0x00 "IRQVA427,(3D Graphics Core BEI) IRQ vector address register" group.long 0x740++0x3 line.long 0x00 "IRQVA428,(3D Graphics Core SBEI) IRQ vector address register" else group.long 0x724++0x3 line.long 0x00 "IRQVA421,(2D Graphics Core LCDBusIf_Control) IRQ vector address register" group.long 0x728++0x3 line.long 0x00 "IRQVA422,(2D Graphics Core LCDBusIf_InstrFifo) IRQ vector address register" group.long 0x72C++0x3 line.long 0x00 "IRQVA423,(2D Graphics Core LCDBusIf_RxFifo) IRQ vector address register" endif endif sif (!cpuis("S6J335*")) group.long 0x750++0x3 line.long 0x00 "IRQVA432,(WG_END_IRQ0) IRQ vector address register" group.long 0x754++0x3 line.long 0x00 "IRQVA433,(WG_END_IRQ1) IRQ vector address register" group.long 0x758++0x3 line.long 0x00 "IRQVA434,(WG_END_IRQ2) IRQ vector address register" group.long 0x75C++0x3 line.long 0x00 "IRQVA435,(WG_END_IRQ3) IRQ vector address register" group.long 0x760++0x3 line.long 0x00 "IRQVA436,(WG_END_IRQ4) IRQ vector address register" group.long 0x764++0x3 line.long 0x00 "IRQVA437,(WG_AHB_ERR_IRQ) IRQ vector address register" group.long 0x768++0x3 line.long 0x00 "IRQVA438,(MX_DATA_REQ_IRQ0) IRQ vector address register" group.long 0x76C++0x3 line.long 0x00 "IRQVA439,(MX_DATA_REQ_IRQ1) IRQ vector address register" group.long 0x770++0x3 line.long 0x00 "IRQVA440,(MX_DATA_REQ_IRQ2) IRQ vector address register" group.long 0x774++0x3 line.long 0x00 "IRQVA441,(MX_DATA_REQ_IRQ3) IRQ vector address register" group.long 0x778++0x3 line.long 0x00 "IRQVA442,(MX_DATA_REQ_IRQ4) IRQ vector address register" group.long 0x77C++0x3 line.long 0x00 "IRQVA443,(MX_OVFL_IRQ0) IRQ vector address register" group.long 0x780++0x3 line.long 0x00 "IRQVA444,(MX_OVFL_IRQ1) IRQ vector address register" group.long 0x784++0x3 line.long 0x00 "IRQVA445,(MX_OVFL_IRQ2) IRQ vector address register" group.long 0x788++0x3 line.long 0x00 "IRQVA446,(MX_OVFL_IRQ3) IRQ vector address register" group.long 0x78C++0x3 line.long 0x00 "IRQVA447,(MX_OVFL_IRQ4) IRQ vector address register" group.long 0x7A4++0x3 line.long 0x00 "IRQVA453,(MX_DMA_ERR_IRQ0) IRQ vector address register" group.long 0x7A8++0x3 line.long 0x00 "IRQVA454,(MX_DMA_ERR_IRQ1) IRQ vector address register" group.long 0x7AC++0x3 line.long 0x00 "IRQVA455,(MX_DMA_ERR_IRQ2) IRQ vector address register" group.long 0x7B0++0x3 line.long 0x00 "IRQVA456,(MX_DMA_ERR_IRQ3) IRQ vector address register" group.long 0x7B4++0x3 line.long 0x00 "IRQVA457,(MX_DMA_ERR_IRQ4) IRQ vector address register" group.long 0x7B8++0x3 line.long 0x00 "IRQVA458,(MX_AHB_ERR_IRQ) IRQ vector address register" endif sif (cpuis("S6J331*")) group.long 0x7C0++0x3 line.long 0x00 "IRQVA460,(ARH IRQ1) IRQ vector address register" group.long 0x7C4++0x3 line.long 0x00 "IRQVA461,(ARH IRQ2) IRQ vector address register" endif sif (cpuis("S6J33*")) group.long 0x7D0++0x3 line.long 0x00 "IRQVA464,(ADC12B1 Conversion Done) IRQ vector address register" group.long 0x7D4++0x3 line.long 0x00 "IRQVA465,(ADC12B1 Group interrupt) IRQ vector address register" group.long 0x7D8++0x3 line.long 0x00 "IRQVA466,(ADC12B1 pulse detection function) IRQ vector address register" group.long 0x7DC++0x3 line.long 0x00 "IRQVA467,(ADC12B1 RCO) IRQ vector address register" endif sif (cpuis("S6J335*")) group.long 0x7E0++0x3 line.long 0x00 "IRQVA468,(Base Timer ch.36/44/45/46/47) IRQ vector address register" group.long 0x7E4++0x3 line.long 0x00 "IRQVA469,(Base Timer ch.37) IRQ vector address register" group.long 0x7E8++0x3 line.long 0x00 "IRQVA470,(Base Timer ch.38) IRQ vector address register" group.long 0x7EC++0x3 line.long 0x00 "IRQVA471,(Base Timer ch.39) IRQ vector address register" group.long 0x7F0++0x3 line.long 0x00 "IRQVA472,(Base Timer ch.40) IRQ vector address register" group.long 0x7F4++0x3 line.long 0x00 "IRQVA473,(Base Timer ch.41) IRQ vector address register" group.long 0x7F8++0x3 line.long 0x00 "IRQVA474,(Base Timer ch.42) IRQ vector address register" group.long 0x7FC++0x3 line.long 0x00 "IRQVA475,(Base Timer ch.43) IRQ vector address register" group.long 0x800++0x3 line.long 0x00 "IRQVA476,(Base Timer ch.48/56/57/58/59) IRQ vector address register" group.long 0x804++0x3 line.long 0x00 "IRQVA477,(Base Timer ch.49) IRQ vector address register" group.long 0x808++0x3 line.long 0x00 "IRQVA478,(Base Timer ch.50) IRQ vector address register" group.long 0x80C++0x3 line.long 0x00 "IRQVA479,(Base Timer ch.51) IRQ vector address register" group.long 0x810++0x3 line.long 0x00 "IRQVA480,(Base Timer ch.52) IRQ vector address register" group.long 0x814++0x3 line.long 0x00 "IRQVA481,(Base Timer ch.53) IRQ vector address register" group.long 0x818++0x3 line.long 0x00 "IRQVA482,(Base Timer ch.54) IRQ vector address register" group.long 0x81C++0x3 line.long 0x00 "IRQVA483,(Base Timer ch.55) IRQ vector address register" group.long 0x820++0x3 line.long 0x00 "IRQVA484,(Base Timer ch.60) IRQ vector address register" group.long 0x824++0x3 line.long 0x00 "IRQVA485,(Base Timer ch.61) IRQ vector address register" group.long 0x828++0x3 line.long 0x00 "IRQVA486,(Base Timer ch.62) IRQ vector address register" group.long 0x82C++0x3 line.long 0x00 "IRQVA487,(Base Timer ch.63) IRQ vector address register" endif tree.end width 8. tree "NMI priority level registers" group.long 0x890++0x3 line.long 0x00 "NMIPL0,NMI Priority Level Register" bitfld.long 0x00 24.--27. " NMIPL4 ,(LVDs IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " NMIPL0 ,(NMIX pin(Ext-IRC)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x894++0x3 line.long 0x00 "NMIPL1,NMI Priority Level Register" bitfld.long 0x00 24.--27. " NMIPL7 ,(SW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NMIPL6 ,(HW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NMIPL5 ,(CSV Profile) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NMIPL4 ,(LVDs IRQ ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x898++0x3 line.long 0x00 "NMIPL2,NMI Priority Level Register" bitfld.long 0x00 24.--27. " NMIPL11 ,(Backup RAM 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NMIPL8 ,(IRC 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x89C++0x3 line.long 0x00 "NMIPL3,NMI Priority Level Register" bitfld.long 0x00 24.--27. " NMIPL15 ,(SHE MPU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 16.--19. " NMIPL14 ,(DMAC MPU #1 protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " endif bitfld.long 0x00 8.--11. " NMIPL13 ,(DMAC MPU #0 protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NMIPL12 ,(M-CAN RAMs 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8A0++0x3 line.long 0x00 "NMIPL4,NMI Priority Level Register" bitfld.long 0x00 16.--19. " NMIPL18 ,(TPU protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("S6J334*")) group.long 0x8A4++0x3 line.long 0x00 "NMIPL5,NMI Priority Level Register" bitfld.long 0x00 8.--11. " NMIPL21 ,(2d Graphics Core_NMI[1]) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NMIPL20 ,(2d Graphics Core_NMI[0]) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (!cpuis("S6J335*")) group.long 0x8A4++0x3 line.long 0x00 "NMIPL5,NMI Priority Level Register" bitfld.long 0x00 24.--27. " NMIPL23 ,(ETHERNET_PMU_NMI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NMIPL22 ,(MLB_MPU_NMI ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NMIPL21 ,(2d Graphics Core_NMI[1]) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NMIPL20 ,(2d Graphics Core_NMI[0]) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 10. tree "IRQ priority level registers" rgroup.long 0x8B0++0x3 line.long 0x00 "IRQPL0,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (SW-WDT Pre-warning) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (HW-WDT Pre-warning) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (System Control Status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8B8++0x3 line.long 0x00 "IRQPL2,IRQ priority level register" bitfld.long 0x00 16.--20. " IRQPL10 ,IRQ10 (Work FLASH Single Bit Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL8 ,IRQ8 (TCFLASH Single Bit Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8BC++0x3 line.long 0x00 "IRQPL3,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL15 ,IRQ15 (Backup RAM / CAN FD RAM(ch.0,1,5,6) Single Bit Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL14 ,IRQ14 (System RAM Single Bit Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8C0++0x3 line.long 0x00 "IRQPL4,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL16 ,IRQ16 (IRC Vector Address RAM Single Bit Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8C4++0x3 line.long 0x00 "IRQPL5,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL23 ,IRQ23 (EICU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL20 ,IRQ20 (Work FLASH Write Completion) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8C8++0x3 line.long 0x00 "IRQPL6,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL27 ,IRQ27 (External Interrupt Request ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL26 ,IRQ26 (External Interrupt Request ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL25 ,IRQ25 (External Interrupt Request ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL24 ,IRQ24 (External Interrupt Request ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8CC++0x3 line.long 0x00 "IRQPL7,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL31 ,IRQ31 (External Interrupt Request ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL30 ,IRQ30 (External Interrupt Request ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL29 ,IRQ29 (External Interrupt Request ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL28 ,IRQ28 (External Interrupt Request ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8D0++0x3 line.long 0x00 "IRQPL8,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL35 ,IRQ35 (External Interrupt Request ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL34 ,IRQ34 (External Interrupt Request ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL33 ,IRQ33 (External Interrupt Request ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL32 ,IRQ32 (External Interrupt Request ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8D4++0x3 line.long 0x00 "IRQPL9,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL39 ,IRQ39 (External Interrupt Request ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL38 ,IRQ38 (External Interrupt Request ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL37 ,IRQ37 (External Interrupt Request ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL36 ,IRQ36 (External Interrupt Request ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8D8++0x3 line.long 0x00 "IRQPL10,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL43 ,IRQ43 (MFS TX ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL42 ,IRQ42 (MFS RX ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL41 ,IRQ41 (MFS TX ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL40 ,IRQ40 (MFS RX ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8DC++0x3 line.long 0x00 "IRQPL11,IRQ priority level register" bitfld.long 0x00 16.--20. " IRQPL46 ,IRQ46 (Reload Timer ch.48,49 OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8E0++0x3 line.long 0x00 "IRQPL12,IRQ priority level register" sif (cpuis("S6J335*")) bitfld.long 0x00 16.--20. " IRQPL50 ,IRQ50 (CAN FD ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) bitfld.long 0x00 8.--12. " IRQPL49 ,IRQ49 (CAN FD ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL48 ,IRQ48 (CAN FD ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 0.--4. " IRQPL48 ,IRQ48 (CAN FD ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x8E8++0x3 line.long 0x00 "IRQPL14,IRQ priority level register" sif (cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL59 ,IRQ59 (CAN FD ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL58 ,IRQ58 (CAN FD ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " else bitfld.long 0x00 8.--12. " IRQPL57 ,IRQ57 (CAN FD ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL56 ,IRQ56 (CAN FD ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("S6J33*")) rgroup.long 0x8EC++0x3 line.long 0x00 "IRQPL15,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL60 ,IRQ60 (CANFD ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x8F0++0x3 line.long 0x00 "IRQPL16,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL67 ,IRQ67 (MFS TX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL66 ,IRQ66 (MFS RX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL65 ,IRQ65 (MFS TX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL64 ,IRQ64 (MFS RX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8F4++0x3 line.long 0x00 "IRQPL17,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL71 ,IRQ71 (MFS TX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL70 ,IRQ70 (MFS RX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL69 ,IRQ69 (MFS TX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL68 ,IRQ68 (MFS RX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x8F8++0x3 line.long 0x00 "IRQPL18,IRQ priority level register" bitfld.long 0x00 8.--12. " IRQPL73 ,IRQ73 (MFS TX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL72 ,IRQ72 (MFS RX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x900++0x3 line.long 0x00 "IRQPL20,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL83 ,IRQ83 (MFS TX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL82 ,IRQ82 (MFS RX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL81 ,IRQ81 (MFS TX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL80 ,IRQ80 (MFS RX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x904++0x3 line.long 0x00 "IRQPL21,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL87 ,IRQ87 (MFS TX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL86 ,IRQ86 (MFS RX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL85 ,IRQ85 (MFS TX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL84 ,IRQ84 (MFS RX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x908++0x3 line.long 0x00 "IRQPL22,IRQ priority level register" bitfld.long 0x00 8.--12. " IRQPL89 ,IRQ89 (MFS TX ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL88 ,IRQ88 (MFS RX ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x914++0x3 line.long 0x00 "IRQPL25,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL103 ,IRQ103 (DDR HSSPI TX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL102 ,IRQ102 (DDR HSSPI RX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL101 ,IRQ101 (SHE) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL100 ,IRQ100 (SHE Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x91C++0x3 line.long 0x00 "IRQPL27,IRQ priority level register" bitfld.long 0x00 16.--20. " IRQPL110 ,IRQ110 (TCRAM) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x920++0x3 line.long 0x00 "IRQPL28,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL112 ,IRQ112 (BACKUP RAM) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x924++0x3 line.long 0x00 "IRQPL29,IRQ priority level register" bitfld.long 0x00 8.--12. " IRQPL117 ,IRQ117 (CR CARIBRATION) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL116 ,IRQ116 (RTC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x930++0x3 line.long 0x00 "IRQPL32,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL131 ,IRQ131 (Base Timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL130 ,IRQ130 (Base Timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL129 ,IRQ129 (Base Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL128 ,IRQ128 (Base Timer ch.0/8/9/10/11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x934++0x3 line.long 0x00 "IRQPL33,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL135 ,IRQ135 (Base Timer ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL134 ,IRQ134 (Base Timer ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL133 ,IRQ133 (Base Timer ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL132 ,IRQ132 (Base Timer ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x938++0x3 line.long 0x00 "IRQPL34,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL139 ,IRQ139 (Base Timer ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL138 ,IRQ138 (Base Timer ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL137 ,IRQ137 (Base Timer ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL136 ,IRQ136 (Base Timer ch.12/20/21/22/23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x93C++0x3 line.long 0x00 "IRQPL35,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL143 ,IRQ143 (Base Timer ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL142 ,IRQ142 (Base Timer ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL141 ,IRQ141 (Base Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL140 ,IRQ140 (Base Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x948++0x3 line.long 0x00 "IRQPL38,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL155 ,IRQ155 (Reload Timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL154 ,IRQ154 (Reload Timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL153 ,IRQ153 (Reload Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL152 ,IRQ152 (Reload Timer ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--12. " IRQPL153 ,IRQ153 (Reload Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL152 ,IRQ152 (Reload Timer ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x950++0x3 line.long 0x00 "IRQPL40,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL163 ,IRQ163 (Reload Timer ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL162 ,IRQ162 (Reload Timer ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL161 ,IRQ161 (Reload Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL160 ,IRQ160 (Reload Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--12. " IRQPL161 ,IRQ161 (Reload Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL160 ,IRQ160 (Reload Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J33*")) rgroup.long 0x958++0x3 line.long 0x00 "IRQPL42,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL171 ,IRQ171 (Reload Timer ch.35) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL170 ,IRQ170 (Reload Timer ch.34) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL169 ,IRQ169 (Reload Timer ch.33) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL168 ,IRQ168 (Reload Timer ch.32) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x960++0x3 line.long 0x00 "IRQPL44,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL179 ,IRQ179 (FRT ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL178 ,IRQ178 (FRT ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL177 ,IRQ177 (FRT ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL176 ,IRQ176 (FRT ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x964++0x3 line.long 0x00 "IRQPL45,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL183 ,IRQ183 (FRT ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL182 ,IRQ182 (FRT ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL181 ,IRQ181 (FRT ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL180 ,IRQ180 (FRT ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 0.--4. " IRQPL180 ,IRQ180 (FRT ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x968++0x3 line.long 0x00 "IRQPL46,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL187 ,IRQ187 (FRT ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL186 ,IRQ186 (FRT ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL185 ,IRQ185 (FRT ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL184 ,IRQ184 (FRT ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL186 ,IRQ186 (FRT ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL185 ,IRQ185 (FRT ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL184 ,IRQ184 (FRT ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x970++0x3 line.long 0x00 "IRQPL48,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL195 ,IRQ195 (IRQ0 of Input Capture 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL194 ,IRQ194 (IRQ0 of Input Capture 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL193 ,IRQ193 (IRQ0 of Input Capture 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL192 ,IRQ192 (IRQ0 of Input Capture 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL194 ,IRQ194 (IRQ0 of Input Capture 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL193 ,IRQ193 (IRQ0 of Input Capture 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL192 ,IRQ192 (IRQ0 of Input Capture 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J33*")) rgroup.long 0x974++0x3 line.long 0x00 "IRQPL49,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL199 ,IRQ199 (IRQ0 of Input Capture 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL198 ,IRQ198 (IRQ0 of Input Capture 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL197 ,IRQ197 (IRQ0 of Input Capture 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL196 ,IRQ196 (IRQ0 of Input Capture 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x978++0x3 line.long 0x00 "IRQPL50,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL203 ,IRQ203 (IRQ0 of Input Capture 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL202 ,IRQ202 (IRQ0 of Input Capture 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL201 ,IRQ201 (IRQ0 of Input Capture 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL200 ,IRQ200 (IRQ0 of Input Capture 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL202 ,IRQ202 (IRQ0 of Input Capture 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL201 ,IRQ201 (IRQ0 of Input Capture 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL200 ,IRQ200 (IRQ0 of Input Capture 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x980++0x3 line.long 0x00 "IRQPL52,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL211 ,IRQ211 (IRQ0 of Output Compare 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL210 ,IRQ210 (IRQ0 of Output Compare 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL209 ,IRQ209 (IRQ0 of Output Compare 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL208 ,IRQ208 (IRQ0 of Output Compare 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL210 ,IRQ210 (IRQ0 of Output Compare 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL209 ,IRQ209 (IRQ0 of Output Compare 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL208 ,IRQ208 (IRQ0 of Output Compare 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J33*")) rgroup.long 0x984++0x3 line.long 0x00 "IRQPL53,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL215 ,IRQ215 (IRQ0 of Output Compare 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL214 ,IRQ214 ()IRQ0 of Output Compare 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL213 ,IRQ213 (IRQ0 of Output Compare 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL212 ,IRQ212 (IRQ0 of Output Compare 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x988++0x3 line.long 0x00 "IRQPL54,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL219 ,IRQ219 (IRQ0 of Output Compare 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL218 ,IRQ218 (IRQ0 of Output Compare 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL217 ,IRQ217 (IRQ0 of Output Compare 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL216 ,IRQ216 (IRQ0 of Output Compare 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL218 ,IRQ218 (IRQ0 of Output Compare 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL217 ,IRQ217 (IRQ0 of Output Compare 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL216 ,IRQ216 (IRQ0 of Output Compare 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x998++0x3 line.long 0x00 "IRQPL58,IRQ priority level register" bitfld.long 0x00 8.--12. " IRQPL233 ,IRQ233 (QPRC ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL232 ,IRQ232 (QPRC ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9A0++0x3 line.long 0x00 "IRQPL60,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL243 ,IRQ243 (IRQ1 of Input Capture 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL242 ,IRQ242 (IRQ1 of Input Capture 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL241 ,IRQ241 (IRQ1 of Input Capture 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL240 ,IRQ240 (IRQ1 of Input Capture 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL242 ,IRQ242 (IRQ1 of Input Capture 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL241 ,IRQ241 (IRQ1 of Input Capture 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL240 ,IRQ240 (IRQ1 of Input Capture 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J33*")) rgroup.long 0x9A4++0x3 line.long 0x00 "IRQPL61,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL247 ,IRQ247 (IRQ1 of Input Capture 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL246 ,IRQ246 (IRQ1 of Input Capture 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL245 ,IRQ245 (IRQ1 of Input Capture 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL244 ,IRQ244 (IRQ1 of Input Capture 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x9A8++0x3 line.long 0x00 "IRQPL62,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL251 ,IRQ251 (IRQ1 of Input Capture 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL250 ,IRQ250 (IRQ1 of Input Capture 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL249 ,IRQ249 (IRQ1 of Input Capture 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL248 ,IRQ248 (IRQ1 of Input Capture 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL250 ,IRQ250 (IRQ1 of Input Capture 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL249 ,IRQ249 (IRQ1 of Input Capture 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL248 ,IRQ248 (IRQ1 of Input Capture 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x9B0++0x3 line.long 0x00 "IRQPL64,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL259 ,IRQ259 (IRQ1 of Output Compare 3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL258 ,IRQ258 (IRQ1 of Output Compare 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL257 ,IRQ257 (IRQ1 of Output Compare 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL256 ,IRQ256 (IRQ1 of Output Compare 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL258 ,IRQ258 (IRQ1 of Output Compare 2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL257 ,IRQ257 (IRQ1 of Output Compare 1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL256 ,IRQ256 (IRQ1 of Output Compare 0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J33*")) rgroup.long 0x9B4++0x3 line.long 0x00 "IRQPL65,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL263 ,IRQ263 (IRQ1 of Output Compare 7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL262 ,IRQ262 (IRQ1 of Output Compare 6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL261 ,IRQ261 (IRQ1 of Output Compare 5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL260 ,IRQ260 (IRQ1 of Output Compare 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x9B8++0x3 line.long 0x00 "IRQPL66,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL267 ,IRQ267 (IRQ1 of Output Compare 11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL266 ,IRQ266 (IRQ1 of Output Compare 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL265 ,IRQ265 (IRQ1 of Output Compare 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL264 ,IRQ264 (IRQ1 of Output Compare 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL266 ,IRQ266 (IRQ1 of Output Compare 10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL265 ,IRQ265 (IRQ1 of Output Compare 9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL264 ,IRQ264 (IRQ1 of Output Compare 8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x9C0++0x3 line.long 0x00 "IRQPL68,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL275 ,IRQ275 (DMAC Completion ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL274 ,IRQ274 (DMAC Completion ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL273 ,IRQ273 (DMAC Completion ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL272 ,IRQ272 (DMA Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9C4++0x3 line.long 0x00 "IRQPL69,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL279 ,IRQ279 (DMAC Completion ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL278 ,IRQ278 (DMAC Completion ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL277 ,IRQ277 (DMAC Completion ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL276 ,IRQ276 (DMAC Completion ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9C8++0x3 line.long 0x00 "IRQPL70,IRQ priority level register" bitfld.long 0x00 16.--20. " IRQPL282 ,IRQ282 (DMAC RLT(ch.0,1,2,3 OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL280 ,IRQ280 (DMAC Completion ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9CC++0x3 line.long 0x00 "IRQPL71,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL287 ,IRQ287 (DMAC Completion ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL286 ,IRQ286 (DMAC Completion ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL285 ,IRQ285 (DMAC Completion ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9D0++0x3 line.long 0x00 "IRQPL72,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL291 ,IRQ291 (DMAC Completion ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL290 ,IRQ290 (DMAC Completion ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL289 ,IRQ289 (DMAC Completion ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL288 ,IRQ288 (DMAC Completion ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9D4++0x3 line.long 0x00 "IRQPL73,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL292 ,IRQ292 (DMAC Completion ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9E4++0x3 line.long 0x00 "IRQPL77,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL311 ,IRQ311 (SCT Sub OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL310 ,IRQ310 (SCT Main OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL309 ,IRQ309 (SCT SRC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL308 ,IRQ308 (SCT CR IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9E8++0x3 line.long 0x00 "IRQPL78,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL312 ,IRQ312 (CR5 Performance Monitor Unit IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9F0++0x3 line.long 0x00 "IRQPL80,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL323 ,IRQ323 (MFS ch.3 Error ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL322 ,IRQ322 (MFS ch.2 Error ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL321 ,IRQ321 (MFS ch.1 Error ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL320 ,IRQ320 (MFS ch.0 Error ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9F4++0x3 line.long 0x00 "IRQPL81,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL324 ,IRQ324 (MFS ch.0 Error 4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9F8++0x3 line.long 0x00 "IRQPL82,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL331 ,IRQ331 (MFS ch.11 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL330 ,IRQ330 ()MFS ch.10 Error priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL329 ,IRQ329 (MFS ch.9 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL328 ,IRQ328 (MFS ch.8 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x9FC++0x3 line.long 0x00 "IRQPL83,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL332 ,IRQ332 (MFS ch.12 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA00++0x3 line.long 0x00 "IRQPL84,IRQ priority level register" sif (!cpuis("S6J33*")) bitfld.long 0x00 24.--28. " IRQPL339 ,IRQ339 (SMC ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL337 ,IRQ337 (MFS ch.17 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL336 ,IRQ336 (MFS ch.16 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--12. " IRQPL337 ,IRQ337 (MFS ch.17 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL336 ,IRQ336 (MFS ch.16 Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J33*")) rgroup.long 0xA04++0x3 line.long 0x00 "IRQPL85,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL343 ,IRQ343 (SMC ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL342 ,IRQ342 (SMC ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL341 ,IRQ341 (SMC ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL340 ,IRQ340 (SMC ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J335*")) rgroup.long 0xA08++0x3 line.long 0x00 "IRQPL86,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL347 ,IRQ347 (SG ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif (!cpuis("S6J33*")) bitfld.long 0x00 0.--4. " IRQPL344 ,IRQ344 (SMC ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif sif (!cpuis("S6J335*")) sif (cpuis("S6J33*")) rgroup.long 0xA0C++0x3 line.long 0x00 "IRQPL87,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL351 ,IRQ350 (SG ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL350 ,IRQ350 (SG ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL349 ,IRQ349 (SG ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL348 ,IRQ348 (SG ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0xA0C++0x3 line.long 0x00 "IRQPL87,IRQ priority level register" bitfld.long 0x00 16.--20. " IRQPL350 ,IRQ350 (SG ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL349 ,IRQ349 (SG ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL348 ,IRQ348 (SG ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif rgroup.long 0xA10++0x3 line.long 0x00 "IRQPL88,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL355 ,IRQ355 (ADC12B pulse detection function) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL354 ,IRQ354 (ADC12B Group interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL353 ,IRQ353 (ADC12B Conversion Done) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA14++0x3 line.long 0x00 "IRQPL89,IRQ priority level register" sif (!cpuis("S6J334*")) bitfld.long 0x00 24.--28. " IRQPL359 ,IRQ359 (MLB channel interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL357 ,IRQ357 (RPGCRC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL356 ,IRQ356 (ADC12B RCO) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 8.--12. " IRQPL357 ,IRQ357 (RPGCRC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL356 ,IRQ356 (ADC12B RCO) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J334*")) rgroup.long 0xA18++0x3 line.long 0x00 "IRQPL90,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL363 ,IRQ363 (ETHERNET Q2 IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL362 ,IRQ362 (ETHERNET Q1 IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL361 ,IRQ361 (ETHERNET IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL360 ,IRQ360 (MLB system interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J334*")) rgroup.long 0xA1C++0x3 line.long 0x00 "IRQPL91,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL364 ,IRQ364 (ETHERNET Q3 IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0xA20++0x3 line.long 0x00 "IRQPL92,IRQ priority level register" sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) bitfld.long 0x00 24.--28. " IRQPL371 ,IRQ371 (PCMPWM_UDRN) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL370 ,IRQ370 (PCMPWM_OVFL) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL369 ,IRQ369 (PCMPWM_DREQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL368 ,IRQ368 (Indicator PWM) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 0.--4. " IRQPL368 ,IRQ368 (Indicator PWM) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) rgroup.long 0xA24++0x3 line.long 0x00 "IRQPL93,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL375 ,IRQ375 (AUDIO_DAC_UDRN_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL374 ,IRQ374 (AUDIO_DAC_OVFL_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL373 ,IRQ373 (AUDIO_DAC_DREQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL372 ,IRQ372 (PCMPWM_DMAE) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J335*")) rgroup.long 0xA28++0x3 line.long 0x00 "IRQPL94,IRQ priority level register" sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) bitfld.long 0x00 16.--20. " IRQPL378 ,IRQ378 (I2S1_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL377 ,IRQ377 (I2S0_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL376 ,IRQ376 (AUDIO_DAC_DMAE_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 16.--20. " IRQPL378 ,IRQ378 (I2S1_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL377 ,IRQ377 (I2S0_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif sif (cpuis("S6J33*")) rgroup.long 0xA34++0x3 line.long 0x00 "IRQPL97,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL391 ,IRQ391 (Base Timer ch.27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL390 ,IRQ390 (Base Timer ch.26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL389 ,IRQ3789 (Base Timer ch.25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif (cpuis("S6J335*")) bitfld.long 0x00 0.--4. " IRQPL388 ,IRQ388 (Base Timer ch.24/32/33/34/35) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 0.--4. " IRQPL388 ,IRQ388 (Base Timer ch.24) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0xA34++0x3 line.long 0x00 "IRQPL98,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL395 ,IRQ395 (Base Timer ch.31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL394 ,IRQ394 (Base Timer ch.30) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL393 ,IRQ393 (Base Timer ch.29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL392 ,IRQ392 (Base Timer ch.28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("S6J33*")&&!cpuis("S6J335*")) rgroup.long 0xA40++0x3 line.long 0x00 "IRQPL100,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL403 ,IRQ403 (2D Graphics Core Drawing Engine) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL402 ,IRQ402 (2D Graphics Core Blit Engine) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL401 ,IRQ401 (2D Graphics Core Command Sequencer) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA44++0x3 line.long 0x00 "IRQPL101,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL407 ,IRQ407 (2D Graphics Core Signature0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL406 ,IRQ406 (2D Graphics Core Display Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL405 ,IRQ405 (2D Graphics Core Safety Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL404 ,IRQ404 (2D Graphics Core Content Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA48++0x3 line.long 0x00 "IRQPL102,IRQ priority level register" bitfld.long 0x00 8.--12. " IRQPL409 ,IRQ409 (2D Graphics Core Display0 Sync1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL408 ,IRQ408 (2D Graphics Core Display0 Sync0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA54++0x3 line.long 0x00 "IRQPL105,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL423 ,IRQ423 (2D Graphics Core LCDBusIf_Control) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL422 ,IRQ422 (2D Graphics Core LCDBusIf_InstrFifo) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL421 ,IRQ421 (2D Graphics Core LCDBusIf_Control) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (!cpuis("S6J335*")) rgroup.long 0xA40++0x3 line.long 0x00 "IRQPL100,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL403 ,IRQ403 (2D Graphics Core Drawing Engine) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL402 ,IRQ402 (2D Graphics Core Blit Engine) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL401 ,IRQ401 (2D Graphics Core Command Sequencer) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA44++0x3 line.long 0x00 "IRQPL101,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL407 ,IRQ407 (2D Graphics Core Signature0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL406 ,IRQ406 (2D Graphics Core Display Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL405 ,IRQ405 (2D Graphics Core Safety Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL404 ,IRQ404 (2D Graphics Core Content Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA48++0x3 line.long 0x00 "IRQPL102,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL411 ,IRQ411 (2D Graphics Core Safety Stream1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL410 ,IRQ410 (2D Graphics Core Content Stream1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL409 ,IRQ409 (2D Graphics Core Display0 Sync1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL408 ,IRQ408 (2D Graphics Core Display0 Sync0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA4C++0x3 line.long 0x00 "IRQPL103,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL415 ,IRQ415 (2D Graphics Core Display1 Sync1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL414 ,IRQ414 (2D Graphics Core Display1 Sync0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL413 ,IRQ413 (2D Graphics Core Signature1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL412 ,IRQ412 (2D Graphics Core Display Stream1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA50++0x3 line.long 0x00 "IRQPL104,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL419 ,IRQ419 (2D Graphics Core Histogram) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL418 ,IRQ418 (2D Graphics Core Storage Stream0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL417 ,IRQ417 (2D Graphics Core Display Plane0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL416 ,IRQ416 (2D Graphics Core Capture Plane0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA54++0x3 line.long 0x00 "IRQPL105,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL423 ,IRQ423 (3D Graphics Core DFI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL422 ,IRQ422 (3D Graphics Core LINI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL421 ,IRQ421 (3D Graphics Core SRUI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL420 ,IRQ420 (2D Graphics Core DDRHSSPI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA58++0x3 line.long 0x00 "IRQPL106,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL427 ,IRQ427 (3D Graphics Core BEI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL426 ,IRQ426 (3D Graphics Core CAEI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL425 ,IRQ425 (3D Graphics Core DEI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL424 ,IRQ424 (3D Graphics Core DLEI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA5C++0x3 line.long 0x00 "IRQPL107,IRQ priority level register" bitfld.long 0x00 0.--4. " IRQPL428 ,IRQ428 (3D Graphics Core SBEI) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (!cpuis("S6J335*")) rgroup.long 0xA60++0x3 line.long 0x00 "IRQPL108,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL435 ,IRQ435 (WG_END_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL434 ,IRQ434 ()WG_END_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL433 ,IRQ433 (WG_END_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL432 ,IRQ432 (WG_END_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA64++0x3 line.long 0x00 "IRQPL109,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL439 ,IRQ439 (MX_DATA_REQ_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL438 ,IRQ438 (MX_DATA_REQ_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL437 ,IRQ437 (WG_AHB_ERR_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL436 ,IRQ436 (WG_END_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA68++0x3 line.long 0x00 "IRQPL110,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL443 ,IRQ443 (MX_OVFL_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL442 ,IRQ442 (MX_DATA_REQ_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL441 ,IRQ441 (MX_DATA_REQ_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL440 ,IRQ440 (MX_DATA_REQ_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA6C++0x3 line.long 0x00 "IRQPL111,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL447 ,IRQ447 (MX_OVFL_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL446 ,IRQ446 (MX_OVFL_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL445 ,IRQ445 (MX_OVFL_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL444 ,IRQ444 (MX_OVFL_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA74++0x3 line.long 0x00 "IRQPL113,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL455 ,IRQ455 (MX_DMA_ERR_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL454 ,IRQ454 (MX_DMA_ERR_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL453 ,IRQ453 (MX_DMA_ERR_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA78++0x3 line.long 0x00 "IRQPL114,IRQ priority level register" bitfld.long 0x00 16.--20. " IRQPL458 ,IRQ458 (MX_AHB_ERR_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL457 ,IRQ457 (MX_DMA_ERR_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL456 ,IRQ456 (MX_DMA_ERR_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("S6J331*")) rgroup.long 0xA7C++0x3 line.long 0x00 "IRQPL115,IRQ priority level register" bitfld.long 0x00 8.--12. " IRQPL461 ,IRQ461 (ARH IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL460 ,IRQ460 (ARH IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("S6J33*")) rgroup.long 0xA80++0x3 line.long 0x00 "IRQPL116,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL467 ,IRQ467 (ADC12B1 RCO) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL466 ,IRQ466 (ADC12B1 pulse detection function) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL465 ,IRQ465 (ADC12B1 Group interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL464 ,IRQ464 (ADC12B1 Conversion Done) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("S6J335*")) rgroup.long 0xA84++0x3 line.long 0x00 "IRQPL117,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL471 ,IRQ471 (Base Timer ch.39) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL470 ,IRQ470 (Base Timer ch.38) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL469 ,IRQ469 (Base Timer ch.37) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL468 ,IRQ468 (Base Timer ch.36/44/45/46/47) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA88++0x3 line.long 0x00 "IRQPL118,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL475 ,IRQ475 (Base Timer ch.43) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL474 ,IRQ474 (Base Timer ch.42) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL473 ,IRQ473 (Base Timer ch.41) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL472 ,IRQ472 (Base Timer ch.40) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA8C++0x3 line.long 0x00 "IRQPL119,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL479 ,IRQ479 (Base Timer ch.51) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL478 ,IRQ478 (Base Timer ch.50) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL477 ,IRQ477 (Base Timer ch.49) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL476 ,IRQ476 (Base Timer ch.48/56/57/58/59) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA90++0x3 line.long 0x00 "IRQPL120,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL483 ,IRQ483 (Base Timer ch.55) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL482 ,IRQ482 (Base Timer ch.54) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL481 ,IRQ481 (Base Timer ch.53) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL480 ,IRQ480 (Base Timer ch.52) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA94++0x3 line.long 0x00 "IRQPL121,IRQ priority level register" bitfld.long 0x00 24.--28. " IRQPL487 ,IRQ487 (Base Timer ch.63) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL486 ,IRQ486 (Base Timer ch.62) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL485 ,IRQ485 (Base Timer ch.61) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL484 ,IRQ484 (Base Timer ch.60) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end textline " " width 16. group.long 0xAB8++0x3 line.long 0x00 "NMISIS_SET/CLR,IRC NMI software interrupt status register" sif (!cpuis("S6J335*")) sif (!cpuis("S6J334*")) setclrfld.long 0x00 23. -0x08 23. -0x04 23. " NMISIS[23] ,NMI23 (ETHERNET_MPU_NMI) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " NMISIS[22] ,NMI22 (MLB_MPU_NMI) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x08 21. -0x04 21. " NMISIS[21] ,NMI21 (2D Graphics Core_NMI[1]) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " NMISIS[20] ,NMI20 (2D Graphics Core_NMI[0]) software interrupt status bit " "No interrupt,Interrupt" textline " " else setclrfld.long 0x00 21. -0x08 21. -0x04 21. " NMISIS[21] ,NMI21 (2D Graphics Core_NMI[1]) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " NMISIS[20] ,NMI20 (2D Graphics Core_NMI[0]) software interrupt status bit " "No interrupt,Interrupt" textline " " endif endif setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS[18] ,NMI18 (TPU protection violation) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NMISIS[15] ,NMI15 (SHE MPU) software interrupt status bit " "No interrupt,Interrupt" textline " " sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NMISIS[14] ,NMI14 (DMAC MPU #1 protection violation) software interrupt status bit " "No interrupt,Interrupt" textline " " endif setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMISIS[13] ,NMI13 (DMAC MPU #0 protection violation) software interrupt status bit " "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. -0x08 12. -0x04 12. " NMISIS[12] ,NMI12 (M-CAN RAMs 2-bit ECC error detection) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " NMISIS[11] ,NMI11 (Backup RAM 2-bit ECC error detection) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x08 08. -0x04 08. " NMISIS[08] ,NMI8 (IRC 2-bit ECC err detection) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x08 07. -0x04 07. " NMISIS[07] ,NMI7 (SW-WDT) software interrupt status bit " "No interrupt,Interrupt" textline " " setclrfld.long 0x00 06. -0x08 06. -0x04 06. " NMISIS[06] ,NMI6 (HW-WDT) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x08 05. -0x04 05. " NMISIS[05] ,NMI5 (CSV, Profile) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x08 04. -0x04 04. " NMISIS[04] ,NMI4 (LVDs IRQ) software interrupt status bit " "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x08 01. -0x04 00. " NMISIS[00] ,NMI0 (NMIX pin(Ext-IRC)) software interrupt status bit " "No interrupt,Interrupt" width 18. tree "IRC IRQ software interrupt status registers" group.long 0xB40++0x3 line.long 0x00 "IRQSIS0_SET/CLR,IRC IRQ software interrupt status register" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[31] ,IRQ (External Interrupt Request ch.7) software interrupt status bit 31" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[30] ,IRQ (External Interrupt Request ch.6) software interrupt status bit 30" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[29] ,IRQ (External Interrupt Request ch.5) software interrupt status bit 29" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[28] ,IRQ (External Interrupt Request ch.4) software interrupt status bit 28" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[27] ,IRQ (External Interrupt Request ch.3) software interrupt status bit 27" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[26] ,IRQ (External Interrupt Request ch.2) software interrupt status bit 26" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[25] ,IRQ (External Interrupt Request ch.1) software interrupt status bit 25" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[24] ,IRQ (External Interrupt Request ch.0) software interrupt status bit 24" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[23] ,IRQ (EICU) software interrupt status bit 23" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[20] ,IRQ (Work FLASH Write Completion) software interrupt status bit 20" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[16] ,IRQ (IRC Vector Address RAM Single Bit Error) software interrupt status bit 16" "No interrupt,Interrupt" setclrfld.long 0x00 15. -0x80 15. -0x40 15. " IRQSIS[15] ,IRQ (Backup RAM / CAN FD RAM(ch.0,1,5,6) Single Bit Error) software interrupt status bit 15" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQSIS[14] ,IRQ (System RAM Single Bit Error) software interrupt status bit 14" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[10] ,IRQ (Work FLASH Single Bit Error) software interrupt status bit 10" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[8] ,IRQ (TCFLASH Single Bit Error) software interrupt status bit 08" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[3] ,IRQ (SW-WDT Pre-warning) software interrupt status bit 03" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[2] ,IRQ (HW-WDT Pre-warning) software interrupt status bit 02" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[1] ,IRQ (System Control Status) software interrupt status bit 01" "No interrupt,Interrupt" group.long 0xB44++0x3 line.long 0x00 "IRQSIS1_SET/CLR,IRC IRQ software interrupt status register" sif (cpuis("S6J335*")) setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[60] ,IRQ (CAN FD ch.4) software interrupt status bit 60" "No interrupt,Interrupt" setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[59] ,IRQ (CAN FD ch.3) software interrupt status bit 59" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[58] ,IRQ (CAN FD ch.2) software interrupt status bit 58" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[57] ,IRQ (CAN FD ch.1) software interrupt status bit 57" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[56] ,IRQ (CAN FD ch.0) software interrupt status bit 56" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[50] ,IRQ (CAN FD ch.7) software interrupt status bit 50" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[49] ,IRQ (CAN FD ch.6) software interrupt status bit 49" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[48] ,IRQ (CAN FD ch.5) software interrupt status bit 48" "No interrupt,Interrupt" elif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[60] ,IRQ (CAN FD ch.4) software interrupt status bit 60" "No interrupt,Interrupt" setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[59] ,IRQ (CAN FD ch.3) software interrupt status bit 59" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[58] ,IRQ (CAN FD ch.2) software interrupt status bit 58" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[57] ,IRQ (CAN FD ch.1) software interrupt status bit 57" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[56] ,IRQ (CAN FD ch.0) software interrupt status bit 56" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[48] ,IRQ (CAN FD ch.5) software interrupt status bit 48" "No interrupt,Interrupt" else setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[57] ,IRQ (CAN FD ch.1) software interrupt status bit 57" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[56] ,IRQ (CAN FD ch.0) software interrupt status bit 56" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[49] ,IRQ (CAN FD ch.6) software interrupt status bit 49" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[48] ,IRQ (CAN FD ch.5) software interrupt status bit 48" "No interrupt,Interrupt" endif textline " " setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQSIS[46] ,IRQ (Reload Timer ch.48,49 OR-ed) software interrupt status bit 46" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[43] ,IRQ (MFS TX ch.17) software interrupt status bit 43" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[42] ,IRQ (MFS RX ch.17) software interrupt status bit 42" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[41] ,IRQ (MFS TX ch.16) software interrupt status bit 41" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[40] ,IRQ (MFS RX ch.16) software interrupt status bit 40" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[39] ,IRQ (External Interrupt Request ch.15) software interrupt status bit 39" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[38] ,IRQ (External Interrupt Request ch.14) software interrupt status bit 38" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[37] ,IRQ (External Interrupt Request ch.13) software interrupt status bit 37" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[36] ,IRQ (External Interrupt Request ch.12) software interrupt status bit 36" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[35] ,IRQ (External Interrupt Request ch.11) software interrupt status bit 35" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[34] ,IRQ (External Interrupt Request ch.10) software interrupt status bit 34" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[33] ,IRQ (External Interrupt Request ch.9) software interrupt status bit 33" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[32] ,IRQ (External Interrupt Request ch.8) software interrupt status bit 32" "No interrupt,Interrupt" group.long 0xB48++0x3 line.long 0x00 "IRQSIS2_SET/CLR,IRC IRQ software interrupt status register" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[89] ,IRQ (MFS TX ch.12) software interrupt status bit 89" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[88] ,IRQ (MFS RX ch.12) software interrupt status bit 88" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[87] ,IRQ (MFS TX ch.11) software interrupt status bit 87" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[86] ,IRQ (MFS RX ch.11) software interrupt status bit 86" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[85] ,IRQ (MFS TX ch.10) software interrupt status bit 85" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[84] ,IRQ (MFS RX ch.10) software interrupt status bit 84" "No interrupt,Interrupt" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[83] ,IRQ (MFS TX ch.9) software interrupt status bit 83" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[82] ,IRQ (MFS RX ch.9) software interrupt status bit 82" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[81] ,IRQ (MFS TX ch.8) software interrupt status bit 81" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[80] ,IRQ (MFS RX ch.8) software interrupt status bit 80" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[73] ,IRQ (MFS TX ch.4) software interrupt status bit 73" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[72] ,IRQ (MFS RX ch.4) software interrupt status bit 72" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[71] ,IRQ (MFS TX ch.3) software interrupt status bit 71" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[70] ,IRQ (MFS RX ch.3) software interrupt status bit 70" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[69] ,IRQ (MFS TX ch.2) software interrupt status bit 69" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[68] ,IRQ (MFS RX ch.2) software interrupt status bit 68" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[67] ,IRQ (MFS TX ch.1) software interrupt status bit 67" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[66] ,IRQ (MFS RX ch.1) software interrupt status bit 66" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[65] ,IRQ (MFS TX ch.0) software interrupt status bit 65" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[64] ,IRQ (MFS RX ch.0) software interrupt status bit 64" "No interrupt,Interrupt" group.long 0xB4C++0x3 line.long 0x00 "IRQSIS3_SET/CLR,IRC IRQ software interrupt status register" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[117] ,IRQ (CR CARIBRATION) software interrupt status bit 117" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[116] ,IRQ (RTC) software interrupt status bit 116" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[112] ,IRQ (BACKUP RAM) software interrupt status bit 112" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQSIS[110] ,IRQ (TCRAM) software interrupt status bit 110" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[103] ,IRQ (DDR HSSPI TX) software interrupt status bit 103" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[102] ,IRQ (DDR HSSPI RX) software interrupt status bit 102" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[101] ,IRQ (SHE) software interrupt status bit 101" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[100] ,IRQ (SHE Error) software interrupt status bit 100" "No interrupt,Interrupt" group.long 0xB50++0x3 line.long 0x00 "IRQSIS4_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[155] ,IRQ (Reload Timer ch.3) software interrupt status bit 155" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[154] ,IRQ (Reload Timer ch.2) software interrupt status bit 154" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[153] ,IRQ (Reload Timer ch.1) software interrupt status bit 153" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[152] ,IRQ (Reload Timer ch.0) software interrupt status bit 152" "No interrupt,Interrupt" else setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[153] ,IRQ (Reload Timer ch.1) software interrupt status bit 153" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[152] ,IRQ (Reload Timer ch.0) software interrupt status bit 152" "No interrupt,Interrupt" endif textline " " setclrfld.long 0x00 15. -0x80 15. -0x40 15. " IRQSIS[143] ,IRQ (Base Timer ch.19) software interrupt status bit 143" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQSIS[142] ,IRQ (Base Timer ch.18) software interrupt status bit 142" "No interrupt,Interrupt" setclrfld.long 0x00 13. -0x80 13. -0x40 13. " IRQSIS[141] ,IRQ (Base Timer ch.17) software interrupt status bit 141" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[140] ,IRQ (Base Timer ch.16) software interrupt status bit 140" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[139] ,IRQ (Base Timer ch.15) software interrupt status bit 139" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[138] ,IRQ (Base Timer ch.14) software interrupt status bit 138" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[137] ,IRQ (Base Timer ch.13) software interrupt status bit 137" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[136] ,IRQ (Base Timer ch.12/20/21/22/23) software interrupt status bit 136" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[135] ,IRQ (Base Timer ch.7) software interrupt status bit 135" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[134] ,IRQ (Base Timer ch.6) software interrupt status bit 134" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[133] ,IRQ (Base Timer ch.5) software interrupt status bit 133" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[132] ,IRQ (Base Timer ch.4) software interrupt status bit 132" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[131] ,IRQ (Base Timer ch.3) software interrupt status bit 131" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[130] ,IRQ (Base Timer ch.2) software interrupt status bit 130" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[129] ,IRQ (Base Timer ch.1) software interrupt status bit 129" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[128] ,IRQ (Base Timer ch.0/8/9/10/11) software interrupt status bit 128" "No interrupt,Interrupt" group.long 0xB54++0x3 line.long 0x00 "IRQSIS5_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[187] ,IRQ (FRT ch.11) software interrupt status bit 187" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[186] ,IRQ (FRT ch.10) software interrupt status bit 186" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[185] ,IRQ (FRT ch.9) software interrupt status bit 185" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[184] ,IRQ (FRT ch.8) software interrupt status bit 184" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[183] ,IRQ (FRT ch.7) software interrupt status bit 183" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[182] ,IRQ (FRT ch.6) software interrupt status bit 182" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[181] ,IRQ (FRT ch.5) software interrupt status bit 181" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[180] ,IRQ (FRT ch.4) software interrupt status bit 180" "No interrupt,Interrupt" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[186] ,IRQ (FRT ch.10) software interrupt status bit 186" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[185] ,IRQ (FRT ch.9) software interrupt status bit 185" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[184] ,IRQ (FRT ch.8) software interrupt status bit 184" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[180] ,IRQ (FRT ch.4) software interrupt status bit 180" "No interrupt,Interrupt" endif textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[179] ,IRQ (FRT ch.3) software interrupt status bit 179" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[178] ,IRQ (FRT ch.2) software interrupt status bit 178" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[177] ,IRQ (FRT ch.1) software interrupt status bit 177" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[176] ,IRQ (FRT ch.0) software interrupt status bit 176" "No interrupt,Interrupt" textline " " sif (!cpuis("S6J33*")) setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[171] ,IRQ (Reload Timer ch.35) software interrupt status bit 171" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[170] ,IRQ (Reload Timer ch.34) software interrupt status bit 170" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[169] ,IRQ (Reload Timer ch.33) software interrupt status bit 169" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[168] ,IRQ (Reload Timer ch.32) software interrupt status bit 168" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[163] ,IRQ (Reload Timer ch.19) software interrupt status bit 163" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[162] ,IRQ (Reload Timer ch.18) software interrupt status bit 162" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[161] ,IRQ (Reload Timer ch.17) software interrupt status bit 161" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[160] ,IRQ (Reload Timer ch.16) software interrupt status bit 160" "No interrupt,Interrupt" else setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[161] ,IRQ (Reload Timer ch.17) software interrupt status bit 161" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[160] ,IRQ (Reload Timer ch.16) software interrupt status bit 160" "No interrupt,Interrupt" endif group.long 0xB58++0x3 line.long 0x00 "IRQSIS6_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[219] ,IRQ (IRQ0 of Output Compare 11) software interrupt status bit 219" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[218] ,IRQ (IRQ0 of Output Compare 10) software interrupt status bit 218" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[217] ,IRQ (IRQ0 of Output Compare 9) software interrupt status bit 217" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[216] ,IRQ (IRQ0 of Output Compare 8) software interrupt status bit 216" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[215] ,IRQ (IRQ0 of Output Compare 7) software interrupt status bit 215" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[214] ,IRQ (IRQ0 of Output Compare 6) software interrupt status bit 214" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[213] ,IRQ (IRQ0 of Output Compare 5) software interrupt status bit 213" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[212] ,IRQ (IRQ0 of Output Compare 4) software interrupt status bit 212" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[211] ,IRQ (IRQ0 of Output Compare 3) software interrupt status bit 211" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[210] ,IRQ (IRQ0 of Output Compare 2) software interrupt status bit 210" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[209] ,IRQ (IRQ0 of Output Compare 1) software interrupt status bit 209" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[208] ,IRQ (IRQ0 of Output Compare 0) software interrupt status bit 208" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[203] ,IRQ (IRQ0 of Input Capture 11) software interrupt status bit 203" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[202] ,IRQ (IRQ0 of Input Capture 10) software interrupt status bit 202" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[201] ,IRQ (IRQ0 of Input Capture 9) software interrupt status bit 201" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[200] ,IRQ (IRQ0 of Input Capture 8) software interrupt status bit 200" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[199] ,IRQ (IRQ0 of Input Capture 7) software interrupt status bit 199" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[198] ,IRQ (IRQ0 of Input Capture 6) software interrupt status bit 198" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[197] ,IRQ (IRQ0 of Input Capture 5) software interrupt status bit 197" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[196] ,IRQ (IRQ0 of Input Capture 4) software interrupt status bit 196" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[195] ,IRQ (IRQ0 of Input Capture 3) software interrupt status bit 195" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[194] ,IRQ (IRQ0 of Input Capture 2) software interrupt status bit 194" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[193] ,IRQ (IRQ0 of Input Capture 1) software interrupt status bit 193" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[192] ,IRQ (IRQ0 of Input Capture 0) software interrupt status bit 192" "No interrupt,Interrupt" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[218] ,IRQ (IRQ0 of Output Compare 10) software interrupt status bit 218" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[217] ,IRQ (IRQ0 of Output Compare 9) software interrupt status bit 217" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[216] ,IRQ (IRQ0 of Output Compare 8) software interrupt status bit 216" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[210] ,IRQ (IRQ0 of Output Compare 2) software interrupt status bit 210" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[209] ,IRQ (IRQ0 of Output Compare 1) software interrupt status bit 209" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[208] ,IRQ (IRQ0 of Output Compare 0) software interrupt status bit 208" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[202] ,IRQ (IRQ0 of Input Capture 10) software interrupt status bit 202" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[201] ,IRQ (IRQ0 of Input Capture 9) software interrupt status bit 201" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[200] ,IRQ (IRQ0 of Input Capture 8) software interrupt status bit 200" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[194] ,IRQ (IRQ0 of Input Capture 2) software interrupt status bit 194" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[193] ,IRQ (IRQ0 of Input Capture 1) software interrupt status bit 193" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[192] ,IRQ (IRQ0 of Input Capture 0) software interrupt status bit 192" "No interrupt,Interrupt" endif group.long 0xB5C++0x3 line.long 0x00 "IRQSIS7_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[251] ,IRQ (IRQ1 of Input Capture 11) software interrupt status bit 251" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[250] ,IRQ (IRQ1 of Input Capture 10) software interrupt status bit 250" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[249] ,IRQ (IRQ1 of Input Capture 9) software interrupt status bit 249" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[248] ,IRQ (IRQ1 of Input Capture 8) software interrupt status bit 248" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[247] ,IRQ (IRQ1 of Input Capture 7) software interrupt status bit 248" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[246] ,IRQ (IRQ1 of Input Capture 6) software interrupt status bit 246" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[245] ,IRQ (IRQ1 of Input Capture 5) software interrupt status bit 245" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[244] ,IRQ (IRQ1 of Input Capture 4) software interrupt status bit 244" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[243] ,IRQ (IRQ1 of Input Capture 3) software interrupt status bit 243" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[242] ,IRQ (IRQ1 of Input Capture 2) software interrupt status bit 242" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[241] ,IRQ (IRQ1 of Input Capture 1) software interrupt status bit 241" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[240] ,IRQ (IRQ1 of Input Capture 0) software interrupt status bit 240" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[233] ,IRQ (QPRC ch.9) software interrupt status bit 233" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[232] ,IRQ (QPRC ch.8) software interrupt status bit 232" "No interrupt,Interrupt" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[250] ,IRQ (IRQ1 of Input Capture 10) software interrupt status bit 250" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[249] ,IRQ (IRQ1 of Input Capture 9) software interrupt status bit 249" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[248] ,IRQ (IRQ1 of Input Capture 8) software interrupt status bit 248" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[242] ,IRQ (IRQ1 of Input Capture 2) software interrupt status bit 242" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[241] ,IRQ (IRQ1 of Input Capture 1) software interrupt status bit 241" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[240] ,IRQ (IRQ1 of Input Capture 0) software interrupt status bit 240" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[233] ,IRQ (QPRC ch.9) software interrupt status bit 233" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[232] ,IRQ (QPRC ch.8) software interrupt status bit 232" "No interrupt,Interrupt" endif group.long 0xB60++0x3 line.long 0x00 "IRQSIS8_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J33*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[287] ,IRQ (DMAC Completion ch.10) software interrupt status bit 287" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[286] ,IRQ (DMAC Completion ch.9) software interrupt status bit 286" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[285] ,IRQ (DMAC Completion ch.8) software interrupt status bit 285" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) software interrupt status bit 282" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[280] ,IRQ (DMAC Completion ch.7) software interrupt status bit 280" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[279] ,IRQ (DMAC Completion ch.6) software interrupt status bit 279" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[278] ,IRQ (DMAC Completion ch.5) software interrupt status bit 278" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[277] ,IRQ (DMAC Completion ch.4) software interrupt status bit 277" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[276] ,IRQ (DMAC Completion ch.3) software interrupt status bit 276" "No interrupt,Interrupt" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[275] ,IRQ (DMAC Completion ch.2) software interrupt status bit 275" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[274] ,IRQ (DMAC Completion ch.1) software interrupt status bit 274" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[273] ,IRQ (DMAC Completion ch.0) software interrupt status bit 273" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[272] ,IRQ (DMA Error) software interrupt status bit 272" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[267] ,IRQ (IRQ1 of Output Compare 11) software interrupt status bit 267" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[266] ,IRQ (IRQ1 of Output Compare 10) software interrupt status bit 266" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[265] ,IRQ (IRQ1 of Output Compare 9) software interrupt status bit 265" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[264] ,IRQ (IRQ1 of Output Compare 8) software interrupt status bit 264" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[263] ,IRQ (IRQ1 of Output Compare 7) software interrupt status bit 263" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[262] ,IRQ (IRQ1 of Output Compare 6) software interrupt status bit 262" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[261] ,IRQ (IRQ1 of Output Compare 5) software interrupt status bit 261" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[260] ,IRQ (IRQ1 of Output Compare 4) software interrupt status bit 260" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[259] ,IRQ (IRQ1 of Output Compare 3) software interrupt status bit 259" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[258] ,IRQ (IRQ1 of Output Compare 2) software interrupt status bit 258" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[257] ,IRQ (IRQ1 of Output Compare 1) software interrupt status bit 257" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[256] ,IRQ (IRQ1 of Output Compare 0) software interrupt status bit 256" "No interrupt,Interrupt" else setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[287] ,IRQ (DMAC Completion ch.10) software interrupt status bit 287" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[286] ,IRQ (DMAC Completion ch.9) software interrupt status bit 286" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[285] ,IRQ (DMAC Completion ch.8) software interrupt status bit 285" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) software interrupt status bit 282" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[280] ,IRQ (DMAC Completion ch.7) software interrupt status bit 280" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[279] ,IRQ (DMAC Completion ch.6) software interrupt status bit 279" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[278] ,IRQ (DMAC Completion ch.5) software interrupt status bit 278" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[277] ,IRQ (DMAC Completion ch.4) software interrupt status bit 277" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[276] ,IRQ (DMAC Completion ch.3) software interrupt status bit 276" "No interrupt,Interrupt" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[275] ,IRQ (DMAC Completion ch.2) software interrupt status bit 275" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[274] ,IRQ (DMAC Completion ch.1) software interrupt status bit 274" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[273] ,IRQ (DMAC Completion ch.0) software interrupt status bit 273" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[272] ,IRQ (DMA Error) software interrupt status bit 272" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[266] ,IRQ (IRQ1 of Output Compare 10) software interrupt status bit 266" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[265] ,IRQ (IRQ1 of Output Compare 9) software interrupt status bit 265" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[264] ,IRQ (IRQ1 of Output Compare 8) software interrupt status bit 264" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[258] ,IRQ (IRQ1 of Output Compare 2) software interrupt status bit 258" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[257] ,IRQ (IRQ1 of Output Compare 1) software interrupt status bit 257" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[256] ,IRQ (IRQ1 of Output Compare 0) software interrupt status bit 256" "No interrupt,Interrupt" endif group.long 0xB64++0x3 line.long 0x00 "IRQSIS9_SET/CLR,IRC IRQ software interrupt status register" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[312] ,IRQ (CR5 Performance Monitor Unit IRQ) software interrupt status bit 312" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[311] ,IRQ (SCT Sub OSC IRQ) software interrupt status bit 311" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[310] ,IRQ (SCT Main OSC IRQ) software interrupt status bit 310" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[309] ,IRQ (SCT SRC IRQ) software interrupt status bit 309" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[308] ,IRQ (SCT CR IRQ) software interrupt status bit 308" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[292] ,IRQ (DMAC Completion ch.15) software interrupt status bit 292" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[291] ,IRQ (DMAC Completion ch.14) software interrupt status bit 291" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[290] ,IRQ (DMAC Completion ch.13) software interrupt status bit 290" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[289] ,IRQ (DMAC Completion ch.12) software interrupt status bit 289" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[288] ,IRQ (DMAC Completion ch.11) software interrupt status bit 288" "No interrupt,Interrupt" group.long 0xB68++0x3 line.long 0x00 "IRQSIS10_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J33*")) setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[350] ,IRQ (SG ch.3) software interrupt status bit 350" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[349] ,IRQ (SG ch.2) software interrupt status bit 349" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[348] ,IRQ (SG ch.1) software interrupt status bit 348" "No interrupt,Interrupt" setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[347] ,IRQ (SG ch.0) software interrupt status bit 347" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[344] ,IRQ (SMC ch.5) software interrupt status bit 344" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[343] ,IRQ (SMC ch.4) software interrupt status bit 343" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[342] ,IRQ (SMC ch.3) software interrupt status bit 342" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[341] ,IRQ (SMC ch.2) software interrupt status bit 341" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[340] ,IRQ (SMC ch.1) software interrupt status bit 340" "No interrupt,Interrupt" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[339] ,IRQ (SMC ch.0) software interrupt status bit 339" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[337] ,IRQ (MFS ch.17 Error) software interrupt status bit 337" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[336] ,IRQ (MFS ch.16 Error) software interrupt status bit 336" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[332] ,IRQ (MFS ch.12 Error) software interrupt status bit 332" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[331] ,IRQ (MFS ch.11 Error) software interrupt status bit 331" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[330] ,IRQ (MFS ch.10 Error) software interrupt status bit 330" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[329] ,IRQ (MFS ch.9 Error) software interrupt status bit 329" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[328] ,IRQ (MFS ch.8 Error) software interrupt status bit 328" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[324] ,IRQ (MFS ch.4 Error) software interrupt status bit 324" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[323] ,IRQ (MFS ch.3 Error) software interrupt status bit 323" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[322] ,IRQ (MFS ch.2 Error) software interrupt status bit 322" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[321] ,IRQ (MFS ch.1 Error) software interrupt status bit 321" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[320] ,IRQ (MFS ch.0 Error) software interrupt status bit 320" "No interrupt,Interrupt" else sif (!cpuis("S6J335*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[351] ,IRQ (SG ch.4) software interrupt status bit 350" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[350] ,IRQ (SG ch.3) software interrupt status bit 350" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[349] ,IRQ (SG ch.2) software interrupt status bit 349" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[348] ,IRQ (SG ch.1) software interrupt status bit 348" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[347] ,IRQ (SG ch.0) software interrupt status bit 347" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[337] ,IRQ (MFS ch.17 Error) software interrupt status bit 337" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[336] ,IRQ (MFS ch.16 Error) software interrupt status bit 336" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[332] ,IRQ (MFS ch.12 Error) software interrupt status bit 332" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[331] ,IRQ (MFS ch.11 Error) software interrupt status bit 331" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[330] ,IRQ (MFS ch.10 Error) software interrupt status bit 330" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[329] ,IRQ (MFS ch.9 Error) software interrupt status bit 329" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[328] ,IRQ (MFS ch.8 Error) software interrupt status bit 328" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[324] ,IRQ (MFS ch.4 Error) software interrupt status bit 324" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[323] ,IRQ (MFS ch.3 Error) software interrupt status bit 323" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[322] ,IRQ (MFS ch.2 Error) software interrupt status bit 322" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[321] ,IRQ (MFS ch.1 Error) software interrupt status bit 321" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[320] ,IRQ (MFS ch.0 Error) software interrupt status bit 320" "No interrupt,Interrupt" else setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[337] ,IRQ (MFS ch.17 Error) software interrupt status bit 337" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[336] ,IRQ (MFS ch.16 Error) software interrupt status bit 336" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[332] ,IRQ (MFS ch.12 Error) software interrupt status bit 332" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[331] ,IRQ (MFS ch.11 Error) software interrupt status bit 331" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[330] ,IRQ (MFS ch.10 Error) software interrupt status bit 330" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[329] ,IRQ (MFS ch.9 Error) software interrupt status bit 329" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[328] ,IRQ (MFS ch.8 Error) software interrupt status bit 328" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[324] ,IRQ (MFS ch.4 Error) software interrupt status bit 324" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[323] ,IRQ (MFS ch.3 Error) software interrupt status bit 323" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[322] ,IRQ (MFS ch.2 Error) software interrupt status bit 322" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[321] ,IRQ (MFS ch.1 Error) software interrupt status bit 321" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[320] ,IRQ (MFS ch.0 Error) software interrupt status bit 320" "No interrupt,Interrupt" endif endif group.long 0xB6C++0x3 line.long 0x00 "IRQSIS11_SET/CLR,IRC IRQ software interrupt status register" sif (!cpuis("S6J334*")) sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[378] ,IRQ (I2S1_IRQ) software interrupt status bit 378" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[377] ,IRQ (I2S0_IRQ) software interrupt status bit 377" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[376] ,IRQ (AUDIO_DAC_DMAE_IRQ) software interrupt status bit 376" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[375] ,IRQ (AUDIO_DAC_UDRN_IRQ) software interrupt status bit 375" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[374] ,IRQ (AUDIO_DAC_OVFL_IRQ) software interrupt status bit 374" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[373] ,IRQ (AUDIO_DAC_DREQ) software interrupt status bit 373" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[372] ,IRQ (PCMPWM_DMAE) software interrupt status bit 372" "No interrupt,Interrupt" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[371] ,IRQ (PCMPWM_UDRN) software interrupt status bit 371" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[370] ,IRQ (PCMPWM_OVFL) software interrupt status bit 370" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[369] ,IRQ (PCMPWM_DREQ) software interrupt status bit 369" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[368] ,IRQ (Indicator PWM) software interrupt status bit 368" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[364] ,IRQ (ETHERNET Q3 IRQ) software interrupt status bit 364" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[363] ,IRQ (ETHERNET Q2 IRQ) software interrupt status bit 363" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[362] ,IRQ (ETHERNET Q1 IRQ) software interrupt status bit 362" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[361] ,IRQ (ETHERNET IRQ) software interrupt status bit 361" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[360] ,IRQ (MLB system interrupt) software interrupt status bit 360" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[359] ,IRQ (MLB channel interrupt) software interrupt status bit 359" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[357] ,IRQ (RPGCRC) software interrupt status bit 357" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[356] ,IRQ (ADC12B RCO) software interrupt status bit 356" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[355] ,IRQ (ADC12B pulse detection function) software interrupt status bit 355" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[354] ,IRQ (ADC12B Group interrupt) software interrupt status bit 354" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[353] ,IRQ (ADC12B Conversion Done) software interrupt status bit 353" "No interrupt,Interrupt" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[378] ,IRQ (I2S1_IRQ) software interrupt status bit 378" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[377] ,IRQ (I2S0_IRQ) software interrupt status bit 377" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[368] ,IRQ (Indicator PWM) software interrupt status bit 368" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[364] ,IRQ (ETHERNET Q3 IRQ) software interrupt status bit 364" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[363] ,IRQ (ETHERNET Q2 IRQ) software interrupt status bit 363" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[362] ,IRQ (ETHERNET Q1 IRQ) software interrupt status bit 362" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[361] ,IRQ (ETHERNET IRQ) software interrupt status bit 361" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[360] ,IRQ (MLB system interrupt) software interrupt status bit 360" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[359] ,IRQ (MLB channel interrupt) software interrupt status bit 359" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[357] ,IRQ (RPGCRC) software interrupt status bit 357" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[356] ,IRQ (ADC12B RCO) software interrupt status bit 356" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[355] ,IRQ (ADC12B pulse detection function) software interrupt status bit 355" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[354] ,IRQ (ADC12B Group interrupt) software interrupt status bit 354" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[353] ,IRQ (ADC12B Conversion Done) software interrupt status bit 353" "No interrupt,Interrupt" endif else setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[368] ,IRQ (Indicator PWM) software interrupt status bit 368" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[357] ,IRQ (RPGCRC) software interrupt status bit 357" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[356] ,IRQ (ADC12B RCO) software interrupt status bit 356" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[355] ,IRQ (ADC12B pulse detection function) software interrupt status bit 355" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[354] ,IRQ (ADC12B Group interrupt) software interrupt status bit 354" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[353] ,IRQ (ADC12B Conversion Done) software interrupt status bit 353" "No interrupt,Interrupt" endif group.long 0xB70++0x3 line.long 0x00 "IRQSIS12_SET/CLR,IRC IRQ software interrupt status register" sif (cpuis("S6J33*")) setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[409] ,IRQ (2D Graphics Core Display0 Sync1) software interrupt status bit 409" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[408] ,IRQ (2D Graphics Core Display0 Sync0) software interrupt status bit 408" "No interrupt,Interrupt" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[407] ,IRQ (2D Graphics Core Signature0) software interrupt status bit 407" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[406] ,IRQ (2D Graphics Core Display Stream0) software interrupt status bit 406" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[405] ,IRQ (2D Graphics Core Safety Stream0) software interrupt status bit 405" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[404] ,IRQ (2D Graphics Core Content Stream0) software interrupt status bit 404" "No interrupt,Interrupt" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[403] ,IRQ (2D Graphics Core Drawing Engine) software interrupt status bit 403" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[402] ,IRQ (2D Graphics Core Blit Engine) software interrupt status bit 402" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[401] ,IRQ (2D Graphics Core Command Sequencer) software interrupt status bit 401" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[395] ,IRQ (Base Timer ch.31) software interrupt status bit 395" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[394] ,IRQ (Base Timer ch.30) software interrupt status bit 394" "No interrupt,Interrupt" setclrfld.long 0x00 9. -0x80 9. -0x40 9. " IRQSIS[393] ,IRQ (Base Timer ch.29) software interrupt status bit 393" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. -0x80 8. -0x40 8. " IRQSIS[392] ,IRQ (Base Timer ch.28) software interrupt status bit 392" "No interrupt,Interrupt" setclrfld.long 0x00 7. -0x80 7. -0x40 7. " IRQSIS[391] ,IRQ (Base Timer ch.27) software interrupt status bit 391" "No interrupt,Interrupt" setclrfld.long 0x00 6. -0x80 6. -0x40 6. " IRQSIS[390] ,IRQ (Base Timer ch.26) software interrupt status bit 390" "No interrupt,Interrupt" setclrfld.long 0x00 5. -0x80 5. -0x40 5. " IRQSIS[389] ,IRQ (Base Timer ch.25) software interrupt status bit 389" "No interrupt,Interrupt" textline " " sif (cpuis("S6J335*")) setclrfld.long 0x00 4. -0x80 4. -0x40 4. " IRQSIS[388] ,IRQ (Base Timer ch.24/32/33/34/35) software interrupt status bit 401" "No interrupt,Interrupt" else setclrfld.long 0x00 4. -0x80 4. -0x40 4. " IRQSIS[388] ,IRQ (Base Timer ch.24) software interrupt status bit 401" "No interrupt,Interrupt" endif else setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[415] ,IRQ (2D Graphics Core Display1 Sync1) software interrupt status bit 415" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[414] ,IRQ (2D Graphics Core Display1 Sync0) software interrupt status bit 414" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[413] ,IRQ (2D Graphics Core Signature1) software interrupt status bit 413" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[412] ,IRQ (2D Graphics Core Display Stream1) software interrupt status bit 412" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[411] ,IRQ (2D Graphics Core Safety Stream1) software interrupt status bit 411" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[410] ,IRQ (2D Graphics Core Content Stream1) software interrupt status bit 410" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[409] ,IRQ (2D Graphics Core Display0 Sync1) software interrupt status bit 409" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[408] ,IRQ (2D Graphics Core Display0 Sync0) software interrupt status bit 408" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[407] ,IRQ (2D Graphics Core Signature0) software interrupt status bit 407" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[406] ,IRQ (2D Graphics Core Display Stream0) software interrupt status bit 406" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[405] ,IRQ (2D Graphics Core Safety Stream0) software interrupt status bit 405" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[404] ,IRQ (2D Graphics Core Content Stream0) software interrupt status bit 404" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[403] ,IRQ (2D Graphics Core Drawing Engine) software interrupt status bit 403" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[402] ,IRQ (2D Graphics Core Blit Engine) software interrupt status bit 402" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[401] ,IRQ (2D Graphics Core Command Sequencer) software interrupt status bit 401" "No interrupt,Interrupt" endif group.long 0xB74++0x3 line.long 0x00 "IRQSIS13_SET/CLR,IRC IRQ software interrupt status register" sif (cpuis("S6J33*")) sif (!cpuis("S6J335*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[447] ,IRQ (MX_OVFL_IRQ4) software interrupt status bit 447" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[446] ,IRQ (MX_OVFL_IRQ3) software interrupt status bit 446" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[445] ,IRQ (MX_OVFL_IRQ2) software interrupt status bit 445" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[444] ,IRQ (MX_OVFL_IRQ1) software interrupt status bit 444" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[443] ,IRQ (MX_OVFL_IRQ0) software interrupt status bit 443" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[442] ,IRQ (MX_DATA_REQ_IRQ4) software interrupt status bit 442" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[441] ,IRQ (MX_DATA_REQ_IRQ3) software interrupt status bit 441" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[440] ,IRQ (MX_DATA_REQ_IRQ2) software interrupt status bit 440" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[439] ,IRQ (MX_DATA_REQ_IRQ1) software interrupt status bit 439" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[438] ,IRQ (MX_DATA_REQ_IRQ0) software interrupt status bit 438" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[437] ,IRQ (WG_AHB_ERR_IRQ) software interrupt status bit 437" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[436] ,IRQ (WG_END_IRQ4) software interrupt status bit 436" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[435] ,IRQ (WG_END_IRQ3) software interrupt status bit 435" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[434] ,IRQ (WG_END_IRQ2) software interrupt status bit 434" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[433] ,IRQ (WG_END_IRQ1) software interrupt status bit 433" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[432] ,IRQ (WG_END_IRQ0) software interrupt status bit 432" "No interrupt,Interrupt" textline " " endif setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[423] ,IRQ (2D Graphics Core LCDBusIf_Control) software interrupt status bit 423" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[422] ,IRQ (2D Graphics Core LCDBusIf_InstrFifo) software interrupt status bit 422" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[421] ,IRQ (2D Graphics Core LCDBusIf_Control) software interrupt status bit 421" "No interrupt,Interrupt" else setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[447] ,IRQ (MX_OVFL_IRQ4) software interrupt status bit 447" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[446] ,IRQ (MX_OVFL_IRQ3) software interrupt status bit 446" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[445] ,IRQ (MX_OVFL_IRQ2) software interrupt status bit 445" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[444] ,IRQ (MX_OVFL_IRQ1) software interrupt status bit 444" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[443] ,IRQ (MX_OVFL_IRQ0) software interrupt status bit 443" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[442] ,IRQ (MX_DATA_REQ_IRQ4) software interrupt status bit 442" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[441] ,IRQ (MX_DATA_REQ_IRQ3) software interrupt status bit 441" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[440] ,IRQ (MX_DATA_REQ_IRQ2) software interrupt status bit 440" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[439] ,IRQ (MX_DATA_REQ_IRQ1) software interrupt status bit 439" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[438] ,IRQ (MX_DATA_REQ_IRQ0) software interrupt status bit 438" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[437] ,IRQ (WG_AHB_ERR_IRQ) software interrupt status bit 437" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[436] ,IRQ (WG_END_IRQ4) software interrupt status bit 436" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[435] ,IRQ (WG_END_IRQ3) software interrupt status bit 435" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[434] ,IRQ (WG_END_IRQ2) software interrupt status bit 434" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[433] ,IRQ (WG_END_IRQ1) software interrupt status bit 433" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[432] ,IRQ (WG_END_IRQ0) software interrupt status bit 432" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[428] ,IRQ (3D Graphics Core SBEI) software interrupt status bit 428" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQSIS[427] ,IRQ (3D Graphics Core BEI) software interrupt status bit 427" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[426] ,IRQ (3D Graphics Core CAEI) software interrupt status bit 426" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[425] ,IRQ (3D Graphics Core DEI) software interrupt status bit 425" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[424] ,IRQ (3D Graphics Core DLEI) software interrupt status bit 424" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[423] ,IRQ (3D Graphics Core DFI) software interrupt status bit 423" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[422] ,IRQ (3D Graphics Core LINI) software interrupt status bit 422" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[421] ,IRQ (3D Graphics Core SRUI) software interrupt status bit 421" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQSIS[420] ,IRQ (2D Graphics Core DDRHSSPI) software interrupt status bit 420" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[419] ,IRQ (2D Graphics Core Histogram) software interrupt status bit 419" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[418] ,IRQ (2D Graphics Core Storage Stream0) software interrupt status bit 418" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[417] ,IRQ (2D Graphics Core Display Plane0) software interrupt status bit 417" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQSIS[416] ,IRQ (2D Graphics Core Capture Plane0) software interrupt status bit 416" "No interrupt,Interrupt" endif group.long 0xB78++0x3 line.long 0x00 "IRQSIS14_SET/CLR,IRC IRQ software interrupt status register" sif (cpuis("S6J33*")) sif (cpuis("S6J331*")) setclrfld.long 0x00 13. -0x80 13. -0x40 13. " IRQSIS[461] ,IRQ (ARH IRQ2) software interrupt status bit 461" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQSIS[460] ,IRQ (ARH IRQ1) software interrupt status bit 460" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[458] ,IRQ (MX_AHB_ERR_IRQ) software interrupt status bit 458" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[457] ,IRQ (MX_DMA_ERR_IRQ4) software interrupt status bit 457" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[456] ,IRQ (MX_DMA_ERR_IRQ3) software interrupt status bit 456" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[455] ,IRQ (MX_DMA_ERR_IRQ2) software interrupt status bit 455" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[454] ,IRQ (MX_DMA_ERR_IRQ1) software interrupt status bit 454" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[453] ,IRQ (MX_DMA_ERR_IRQ0) software interrupt status bit 453" "No interrupt,Interrupt" elif (cpuis("S6J333*")) setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQSIS[467] ,IRQ (ADC12B1 RCO) software interrupt status bit 467" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQSIS[466] ,IRQ (ADC12B1 pulse detection function) software interrupt status bit 466" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQSIS[465] ,IRQ (ADC12B1 Group interrupt) software interrupt status bit 465" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[464] ,IRQ (ADC12B1 Conversion Done) software interrupt status bit 464" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[458] ,IRQ (MX_AHB_ERR_IRQ) software interrupt status bit 458" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[457] ,IRQ (MX_DMA_ERR_IRQ4) software interrupt status bit 457" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[456] ,IRQ (MX_DMA_ERR_IRQ3) software interrupt status bit 456" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[455] ,IRQ (MX_DMA_ERR_IRQ2) software interrupt status bit 455" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[454] ,IRQ (MX_DMA_ERR_IRQ1) software interrupt status bit 454" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[453] ,IRQ (MX_DMA_ERR_IRQ0) software interrupt status bit 453" "No interrupt,Interrupt" elif (cpuis("S6J335*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[479] ,IRQ (Base Timer ch.51) software interrupt status bit 479" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[478] ,IRQ (Base Timer ch.50) software interrupt status bit 478" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[477] ,IRQ (Base Timer ch.49) software interrupt status bit 477" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[476] ,IRQ (Base Timer ch.48/56/57/58/59) software interrupt status bit 476" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[475] ,IRQ (Base Timer ch.43) software interrupt status bit 475" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[474] ,IRQ (Base Timer ch.42) software interrupt status bit 474" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[473] ,IRQ (Base Timer ch.41) software interrupt status bit 473" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[472] ,IRQ (Base Timer ch.40) software interrupt status bit 472" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQSIS[471] ,IRQ (Base Timer ch.39) software interrupt status bit 471" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQSIS[470] ,IRQ (Base Timer ch.38) software interrupt status bit 470" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQSIS[469] ,IRQ (Base Timer ch.37) software interrupt status bit 469" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[468] ,IRQ (Base Timer ch.36/44/45/46/47) software interrupt status bit 468" "No interrupt,Interrupt" else setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[458] ,IRQ (MX_AHB_ERR_IRQ) software interrupt status bit 458" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[457] ,IRQ (MX_DMA_ERR_IRQ4) software interrupt status bit 457" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[456] ,IRQ (MX_DMA_ERR_IRQ3) software interrupt status bit 456" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[455] ,IRQ (MX_DMA_ERR_IRQ2) software interrupt status bit 455" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[454] ,IRQ (MX_DMA_ERR_IRQ1) software interrupt status bit 454" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[453] ,IRQ (MX_DMA_ERR_IRQ0) software interrupt status bit 453" "No interrupt,Interrupt" endif else setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[458] ,IRQ (MX_AHB_ERR_IRQ) software interrupt status bit 458" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQSIS[457] ,IRQ (MX_DMA_ERR_IRQ4) software interrupt status bit 457" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[456] ,IRQ (MX_DMA_ERR_IRQ3) software interrupt status bit 456" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQSIS[455] ,IRQ (MX_DMA_ERR_IRQ2) software interrupt status bit 455" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQSIS[454] ,IRQ (MX_DMA_ERR_IRQ1) software interrupt status bit 454" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQSIS[453] ,IRQ (MX_DMA_ERR_IRQ0) software interrupt status bit 453" "No interrupt,Interrupt" endif sif (cpuis("S6J335*")) group.long 0xB7C++0x3 line.long 0x00 "IRQSIS15_SET/CLR,IRC IRQ software interrupt status register" setclrfld.long 0x00 7. -0x80 7. -0x40 7. " IRQSIS[487] ,IRQ (Base Timer ch.63) software interrupt status bit 487" "No interrupt,Interrupt" setclrfld.long 0x00 6. -0x80 6. -0x40 6. " IRQSIS[486] ,IRQ (Base Timer ch.62) software interrupt status bit 486" "No interrupt,Interrupt" setclrfld.long 0x00 5. -0x80 5. -0x40 5. " IRQSIS[485] ,IRQ (Base Timer ch.61) software interrupt status bit 485" "No interrupt,Interrupt" setclrfld.long 0x00 4. -0x80 4. -0x40 4. " IRQSIS[484] ,IRQ (Base Timer ch.60) software interrupt status bit 484" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. -0x80 3. -0x40 3. " IRQSIS[483] ,IRQ (Base Timer ch.55) software interrupt status bit 483" "No interrupt,Interrupt" setclrfld.long 0x00 2. -0x80 2. -0x40 2. " IRQSIS[482] ,IRQ (Base Timer ch.54) software interrupt status bit 482" "No interrupt,Interrupt" setclrfld.long 0x00 1. -0x80 1. -0x40 1. " IRQSIS[481] ,IRQ (Base Timer ch.53) software interrupt status bit 481" "No interrupt,Interrupt" setclrfld.long 0x00 0. -0x80 0. -0x40 0. " IRQSIS[480] ,IRQ (Base Timer ch.52) software interrupt status bit 480" "No interrupt,Interrupt" endif tree.end width 17. tree "IRC IRQ channel enable registers" group.long 0xC00++0x3 line.long 0x00 "IRQCE0_SET/CLR,IRC IRQ channel enable setting register 0" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[31] ,IRQ (External Interrupt Request ch.7) channel enable setting bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[30] ,IRQ (External Interrupt Request ch.6) channel enable setting bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[29] ,IRQ (External Interrupt Request ch.5) channel enable setting bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[28] ,IRQ (External Interrupt Request ch.4) channel enable setting bit 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[27] ,IRQ (External Interrupt Request ch.3) channel enable setting bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[26] ,IRQ (External Interrupt Request ch.2) channel enable setting bit 26" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[25] ,IRQ (External Interrupt Request ch.1) channel enable setting bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[24] ,IRQ (External Interrupt Request ch.0) channel enable setting bit 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[23] ,IRQ (EICU) channel enable setting bit 23" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[20] ,IRQ (Work FLASH Write Completion) channel enable setting bit 20" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[16] ,IRQ (IRC Vector Address RAM Single Bit Error) channel enable setting bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. -0x80 15. -0x40 15. " IRQCE[15] ,IRQ (Backup RAM / CAN FD RAM(ch.0,1,5,6) Single Bit Error) channel enable setting bit 15" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQCE[14] ,IRQ (System RAM Single Bit Error) channel enable setting bit 14" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[10] ,IRQ (Work FLASH Single Bit Error) channel enable setting bit 10" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[8] ,IRQ (TCFLASH Single Bit Error) channel enable setting bit 08" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[3] ,IRQ (SW-WDT Pre-warning) channel enable setting bit 03" "Disabled,Enabled" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[2] ,IRQ (HW-WDT Pre-warning) channel enable setting bit 02" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[1] ,IRQ (System Control Status) channel enable setting bit 01" "Disabled,Enabled" group.long 0xC04++0x3 line.long 0x00 "IRQCE1_SET/CLR,IRC IRQ channel enable setting register 1" sif (cpuis("S6J335*")) setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[60] ,IRQ (CAN FD ch.4) channel enable setting bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[59] ,IRQ (CAN FD ch.3) channel enable setting bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[58] ,IRQ (CAN FD ch.2) channel enable setting bit 58" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[57] ,IRQ (CAN FD ch.1) channel enable setting bit 57" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[56] ,IRQ (CAN FD ch.0) channel enable setting bit 56" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[50] ,IRQ (CAN FD ch.7) channel enable setting bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[49] ,IRQ (CAN FD ch.6) channel enable setting bit 49" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[48] ,IRQ (CAN FD ch.5) channel enable setting bit 48" "Disabled,Enabled" elif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[60] ,IRQ (CAN FD ch.4) channel enable setting bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[59] ,IRQ (CAN FD ch.3) channel enable setting bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[58] ,IRQ (CAN FD ch.2) channel enable setting bit 58" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[57] ,IRQ (CAN FD ch.1) channel enable setting bit 57" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[56] ,IRQ (CAN FD ch.0) channel enable setting bit 56" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[48] ,IRQ (CAN FD ch.5) channel enable setting bit 48" "Disabled,Enabled" else setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[57] ,IRQ (CAN FD ch.1) channel enable setting bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[56] ,IRQ (CAN FD ch.0) channel enable setting bit 56" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[49] ,IRQ (CAN FD ch.6) channel enable setting bit 49" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[48] ,IRQ (CAN FD ch.5) channel enable setting bit 48" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQCE[46] ,IRQ (Reload Timer ch.48,49 OR-ed) channel enable setting bit 46" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[43] ,IRQ (MFS TX ch.17) channel enable setting bit 43" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[42] ,IRQ (MFS RX ch.17) channel enable setting bit 42" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[41] ,IRQ (MFS TX ch.16) channel enable setting bit 41" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[40] ,IRQ (MFS RX ch.16) channel enable setting bit 40" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[39] ,IRQ (External Interrupt Request ch.15) channel enable setting bit 39" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[38] ,IRQ (External Interrupt Request ch.14) channel enable setting bit 38" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[37] ,IRQ (External Interrupt Request ch.13) channel enable setting bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[36] ,IRQ (External Interrupt Request ch.12) channel enable setting bit 36" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[35] ,IRQ (External Interrupt Request ch.11) channel enable setting bit 35" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[34] ,IRQ (External Interrupt Request ch.10) channel enable setting bit 34" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[33] ,IRQ (External Interrupt Request ch.9) channel enable setting bit 33" "Disabled,Enabled" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[32] ,IRQ (External Interrupt Request ch.8) channel enable setting bit 32" "Disabled,Enabled" group.long 0xC08++0x3 line.long 0x00 "IRQCE2_SET/CLR,IRC IRQ channel enable setting register 2" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[89] ,IRQ (MFS TX ch.12) channel enable setting bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[88] ,IRQ (MFS RX ch.12) channel enable setting bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[87] ,IRQ (MFS TX ch.11) channel enable setting bit 87" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[86] ,IRQ (MFS RX ch.11) channel enable setting bit 86" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[85] ,IRQ (MFS TX ch.10) channel enable setting bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[84] ,IRQ (MFS RX ch.10) channel enable setting bit 84" "Disabled,Enabled" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[83] ,IRQ (MFS TX ch.9) channel enable setting bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[82] ,IRQ (MFS RX ch.9) channel enable setting bit 82" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[81] ,IRQ (MFS TX ch.8) channel enable setting bit 81" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[80] ,IRQ (MFS RX ch.8) channel enable setting bit 80" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[73] ,IRQ (MFS TX ch.4) channel enable setting bit 73" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[72] ,IRQ (MFS RX ch.4) channel enable setting bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[71] ,IRQ (MFS TX ch.3) channel enable setting bit 71" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[70] ,IRQ (MFS RX ch.3) channel enable setting bit 70" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[69] ,IRQ (MFS TX ch.2) channel enable setting bit 69" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[68] ,IRQ (MFS RX ch.2) channel enable setting bit 68" "Disabled,Enabled" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[67] ,IRQ (MFS TX ch.1) channel enable setting bit 67" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[66] ,IRQ (MFS RX ch.1) channel enable setting bit 66" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[65] ,IRQ (MFS TX ch.0) channel enable setting bit 65" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[64] ,IRQ (MFS RX ch.0) channel enable setting bit 64" "Disabled,Enabled" group.long 0xC0C++0x3 line.long 0x00 "IRQCE3_SET/CLR,IRC IRQ channel enable setting register 3" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[117] ,IRQ (CR CARIBRATION) channel enable setting bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[116] ,IRQ (RTC) channel enable setting bit 116" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[112] ,IRQ (BACKUP RAM) channel enable setting bit 112" "Disabled,Enabled" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQCE[110] ,IRQ (TCRAM) channel enable setting bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[103] ,IRQ (DDR HSSPI TX) channel enable setting bit 103" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[102] ,IRQ (DDR HSSPI RX) channel enable setting bit 102" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[101] ,IRQ (SHE) channel enable setting bit 101" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[100] ,IRQ (SHE Error) channel enable setting bit 100" "Disabled,Enabled" group.long 0xC10++0x3 line.long 0x00 "IRQCE4_SET/CLR,IRC IRQ channel enable setting register 4" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[155] ,IRQ (Reload Timer ch.3) channel enable setting bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[154] ,IRQ (Reload Timer ch.2) channel enable setting bit 154" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[153] ,IRQ (Reload Timer ch.1) channel enable setting bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[152] ,IRQ (Reload Timer ch.0) channel enable setting bit 152" "Disabled,Enabled" else setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[153] ,IRQ (Reload Timer ch.1) channel enable setting bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[152] ,IRQ (Reload Timer ch.0) channel enable setting bit 152" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 15. -0x80 15. -0x40 15. " IRQCE[143] ,IRQ (Base Timer ch.19) channel enable setting bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQCE[142] ,IRQ (Base Timer ch.18) channel enable setting bit 142" "Disabled,Enabled" setclrfld.long 0x00 13. -0x80 13. -0x40 13. " IRQCE[141] ,IRQ (Base Timer ch.17) channel enable setting bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[140] ,IRQ (Base Timer ch.16) channel enable setting bit 140" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[139] ,IRQ (Base Timer ch.15) channel enable setting bit 139" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[138] ,IRQ (Base Timer ch.14) channel enable setting bit 138" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[137] ,IRQ (Base Timer ch.13) channel enable setting bit 137" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[136] ,IRQ (Base Timer ch.12/20/21/22/23) channel enable setting bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[135] ,IRQ (Base Timer ch.7) channel enable setting bit 135" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[134] ,IRQ (Base Timer ch.6) channel enable setting bit 134" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[133] ,IRQ (Base Timer ch.5) channel enable setting bit 133" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[132] ,IRQ (Base Timer ch.4) channel enable setting bit 132" "Disabled,Enabled" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[131] ,IRQ (Base Timer ch.3) channel enable setting bit 131" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[130] ,IRQ (Base Timer ch.2) channel enable setting bit 130" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[129] ,IRQ (Base Timer ch.1) channel enable setting bit 129" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[128] ,IRQ (Base Timer ch.0/8/9/10/11) channel enable setting bit 128" "Disabled,Enabled" group.long 0xC14++0x3 line.long 0x00 "IRQCE5_SET/CLR,IRC IRQ channel enable setting register 5" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[187] ,IRQ (FRT ch.11) channel enable setting bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[186] ,IRQ (FRT ch.10) channel enable setting bit 186" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[185] ,IRQ (FRT ch.9) channel enable setting bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[184] ,IRQ (FRT ch.8) channel enable setting bit 184" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[183] ,IRQ (FRT ch.7) channel enable setting bit 183" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[182] ,IRQ (FRT ch.6) channel enable setting bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[181] ,IRQ (FRT ch.5) channel enable setting bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[180] ,IRQ (FRT ch.4) channel enable setting bit 180" "Disabled,Enabled" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[186] ,IRQ (FRT ch.10) channel enable setting bit 186" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[185] ,IRQ (FRT ch.9) channel enable setting bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[184] ,IRQ (FRT ch.8) channel enable setting bit 184" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[180] ,IRQ (FRT ch.4) channel enable setting bit 180" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[179] ,IRQ (FRT ch.3) channel enable setting bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[178] ,IRQ (FRT ch.2) channel enable setting bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[177] ,IRQ (FRT ch.1) channel enable setting bit 177" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[176] ,IRQ (FRT ch.0) channel enable setting bit 176" "Disabled,Enabled" textline " " sif (!cpuis("S6J33*")) setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[171] ,IRQ (Reload Timer ch.35) channel enable setting bit 171" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[170] ,IRQ (Reload Timer ch.34) channel enable setting bit 170" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[169] ,IRQ (Reload Timer ch.33) channel enable setting bit 169" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[168] ,IRQ (Reload Timer ch.32) channel enable setting bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[163] ,IRQ (Reload Timer ch.19) channel enable setting bit 163" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[162] ,IRQ (Reload Timer ch.18) channel enable setting bit 162" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[161] ,IRQ (Reload Timer ch.17) channel enable setting bit 161" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[160] ,IRQ (Reload Timer ch.16) channel enable setting bit 160" "Disabled,Enabled" else setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[161] ,IRQ (Reload Timer ch.17) channel enable setting bit 161" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[160] ,IRQ (Reload Timer ch.16) channel enable setting bit 160" "Disabled,Enabled" endif group.long 0xC18++0x3 line.long 0x00 "IRQCE6_SET/CLR,IRC IRQ channel enable setting register 6" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[219] ,IRQ (IRQ0 of Output Compare 11) channel enable setting bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[218] ,IRQ (IRQ0 of Output Compare 10) channel enable setting bit 218" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[217] ,IRQ (IRQ0 of Output Compare 9) channel enable setting bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[216] ,IRQ (IRQ0 of Output Compare 8) channel enable setting bit 216" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[215] ,IRQ (IRQ0 of Output Compare 7) channel enable setting bit 215" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[214] ,IRQ (IRQ0 of Output Compare 6) channel enable setting bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[213] ,IRQ (IRQ0 of Output Compare 5) channel enable setting bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[212] ,IRQ (IRQ0 of Output Compare 4) channel enable setting bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[211] ,IRQ (IRQ0 of Output Compare 3) channel enable setting bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[210] ,IRQ (IRQ0 of Output Compare 2) channel enable setting bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[209] ,IRQ (IRQ0 of Output Compare 1) channel enable setting bit 209" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[208] ,IRQ (IRQ0 of Output Compare 0) channel enable setting bit 208" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[203] ,IRQ (IRQ0 of Input Capture 11) channel enable setting bit 203" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[202] ,IRQ (IRQ0 of Input Capture 10) channel enable setting bit 202" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[201] ,IRQ (IRQ0 of Input Capture 9) channel enable setting bit 201" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[200] ,IRQ (IRQ0 of Input Capture 8) channel enable setting bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[199] ,IRQ (IRQ0 of Input Capture 7) channel enable setting bit 199" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[198] ,IRQ (IRQ0 of Input Capture 6) channel enable setting bit 198" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[197] ,IRQ (IRQ0 of Input Capture 5) channel enable setting bit 197" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[196] ,IRQ (IRQ0 of Input Capture 4) channel enable setting bit 196" "Disabled,Enabled" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[195] ,IRQ (IRQ0 of Input Capture 3) channel enable setting bit 195" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[194] ,IRQ (IRQ0 of Input Capture 2) channel enable setting bit 194" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[193] ,IRQ (IRQ0 of Input Capture 1) channel enable setting bit 193" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[192] ,IRQ (IRQ0 of Input Capture 0) channel enable setting bit 192" "Disabled,Enabled" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[218] ,IRQ (IRQ0 of Output Compare 10) channel enable setting bit 218" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[217] ,IRQ (IRQ0 of Output Compare 9) channel enable setting bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[216] ,IRQ (IRQ0 of Output Compare 8) channel enable setting bit 216" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[210] ,IRQ (IRQ0 of Output Compare 2) channel enable setting bit 210" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[209] ,IRQ (IRQ0 of Output Compare 1) channel enable setting bit 209" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[208] ,IRQ (IRQ0 of Output Compare 0) channel enable setting bit 208" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[202] ,IRQ (IRQ0 of Input Capture 10) channel enable setting bit 202" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[201] ,IRQ (IRQ0 of Input Capture 9) channel enable setting bit 201" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[200] ,IRQ (IRQ0 of Input Capture 8) channel enable setting bit 200" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[194] ,IRQ (IRQ0 of Input Capture 2) channel enable setting bit 194" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[193] ,IRQ (IRQ0 of Input Capture 1) channel enable setting bit 193" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[192] ,IRQ (IRQ0 of Input Capture 0) channel enable setting bit 192" "Disabled,Enabled" endif group.long 0xC1C++0x3 line.long 0x00 "IRQCE7_SET/CLR,IRC IRQ channel enable setting register 7" sif (!cpuis("S6J33*")) setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[251] ,IRQ (IRQ1 of Input Capture 11) channel enable setting bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[250] ,IRQ (IRQ1 of Input Capture 10) channel enable setting bit 250" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[249] ,IRQ (IRQ1 of Input Capture 9) channel enable setting bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[248] ,IRQ (IRQ1 of Input Capture 8) channel enable setting bit 248" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[247] ,IRQ (IRQ1 of Input Capture 7) channel enable setting bit 248" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[246] ,IRQ (IRQ1 of Input Capture 6) channel enable setting bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[245] ,IRQ (IRQ1 of Input Capture 5) channel enable setting bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[244] ,IRQ (IRQ1 of Input Capture 4) channel enable setting bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[243] ,IRQ (IRQ1 of Input Capture 3) channel enable setting bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[242] ,IRQ (IRQ1 of Input Capture 2) channel enable setting bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[241] ,IRQ (IRQ1 of Input Capture 1) channel enable setting bit 241" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[240] ,IRQ (IRQ1 of Input Capture 0) channel enable setting bit 240" "Disabled,Enabled" textline " " setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[233] ,IRQ (QPRC ch.9) channel enable setting bit 233" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[232] ,IRQ (QPRC ch.8) channel enable setting bit 232" "Disabled,Enabled" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[250] ,IRQ (IRQ1 of Input Capture 10) channel enable setting bit 250" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[249] ,IRQ (IRQ1 of Input Capture 9) channel enable setting bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[248] ,IRQ (IRQ1 of Input Capture 8) channel enable setting bit 248" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[242] ,IRQ (IRQ1 of Input Capture 2) channel enable setting bit 242" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[241] ,IRQ (IRQ1 of Input Capture 1) channel enable setting bit 241" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[240] ,IRQ (IRQ1 of Input Capture 0) channel enable setting bit 240" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[233] ,IRQ (QPRC ch.9) channel enable setting bit 233" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[232] ,IRQ (QPRC ch.8) channel enable setting bit 232" "Disabled,Enabled" endif group.long 0xC20++0x3 line.long 0x00 "IRQCE8_SET/CLR,IRC IRQ channel enable setting register 8" sif (!cpuis("S6J33*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[287] ,IRQ (DMAC Completion ch.10) channel enable setting bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[286] ,IRQ (DMAC Completion ch.9) channel enable setting bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[285] ,IRQ (DMAC Completion ch.8) channel enable setting bit 285" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) channel enable setting bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[280] ,IRQ (DMAC Completion ch.7) channel enable setting bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[279] ,IRQ (DMAC Completion ch.6) channel enable setting bit 279" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[278] ,IRQ (DMAC Completion ch.5) channel enable setting bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[277] ,IRQ (DMAC Completion ch.4) channel enable setting bit 277" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[276] ,IRQ (DMAC Completion ch.3) channel enable setting bit 276" "Disabled,Enabled" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[275] ,IRQ (DMAC Completion ch.2) channel enable setting bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[274] ,IRQ (DMAC Completion ch.1) channel enable setting bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[273] ,IRQ (DMAC Completion ch.0) channel enable setting bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[272] ,IRQ (DMA Error) channel enable setting bit 272" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[267] ,IRQ (IRQ1 of Output Compare 11) channel enable setting bit 267" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[266] ,IRQ (IRQ1 of Output Compare 10) channel enable setting bit 266" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[265] ,IRQ (IRQ1 of Output Compare 9) channel enable setting bit 265" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[264] ,IRQ (IRQ1 of Output Compare 8) channel enable setting bit 264" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[263] ,IRQ (IRQ1 of Output Compare 7) channel enable setting bit 263" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[262] ,IRQ (IRQ1 of Output Compare 6) channel enable setting bit 262" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[261] ,IRQ (IRQ1 of Output Compare 5) channel enable setting bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[260] ,IRQ (IRQ1 of Output Compare 4) channel enable setting bit 260" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[259] ,IRQ (IRQ1 of Output Compare 3) channel enable setting bit 259" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[258] ,IRQ (IRQ1 of Output Compare 2) channel enable setting bit 258" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[257] ,IRQ (IRQ1 of Output Compare 1) channel enable setting bit 257" "Disabled,Enabled" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[256] ,IRQ (IRQ1 of Output Compare 0) channel enable setting bit 256" "Disabled,Enabled" else setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[287] ,IRQ (DMAC Completion ch.10) channel enable setting bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[286] ,IRQ (DMAC Completion ch.9) channel enable setting bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[285] ,IRQ (DMAC Completion ch.8) channel enable setting bit 285" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) channel enable setting bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[280] ,IRQ (DMAC Completion ch.7) channel enable setting bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[279] ,IRQ (DMAC Completion ch.6) channel enable setting bit 279" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[278] ,IRQ (DMAC Completion ch.5) channel enable setting bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[277] ,IRQ (DMAC Completion ch.4) channel enable setting bit 277" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[276] ,IRQ (DMAC Completion ch.3) channel enable setting bit 276" "Disabled,Enabled" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[275] ,IRQ (DMAC Completion ch.2) channel enable setting bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[274] ,IRQ (DMAC Completion ch.1) channel enable setting bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[273] ,IRQ (DMAC Completion ch.0) channel enable setting bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[272] ,IRQ (DMA Error) channel enable setting bit 272" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[266] ,IRQ (IRQ1 of Output Compare 10) channel enable setting bit 266" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[265] ,IRQ (IRQ1 of Output Compare 9) channel enable setting bit 265" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[264] ,IRQ (IRQ1 of Output Compare 8) channel enable setting bit 264" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[258] ,IRQ (IRQ1 of Output Compare 2) channel enable setting bit 258" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[257] ,IRQ (IRQ1 of Output Compare 1) channel enable setting bit 257" "Disabled,Enabled" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[256] ,IRQ (IRQ1 of Output Compare 0) channel enable setting bit 256" "Disabled,Enabled" endif group.long 0xC24++0x3 line.long 0x00 "IRQCE9_SET/CLR,IRC IRQ channel enable setting register 9" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[312] ,IRQ (CR5 Performance Monitor Unit IRQ) channel enable setting bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[311] ,IRQ (SCT Sub OSC IRQ) channel enable setting bit 311" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[310] ,IRQ (SCT Main OSC IRQ) channel enable setting bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[309] ,IRQ (SCT SRC IRQ) channel enable setting bit 309" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[308] ,IRQ (SCT CR IRQ) channel enable setting bit 308" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[292] ,IRQ (DMAC Completion ch.15) channel enable setting bit 292" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[291] ,IRQ (DMAC Completion ch.14) channel enable setting bit 291" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[290] ,IRQ (DMAC Completion ch.13) channel enable setting bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[289] ,IRQ (DMAC Completion ch.12) channel enable setting bit 289" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[288] ,IRQ (DMAC Completion ch.11) channel enable setting bit 288" "Disabled,Enabled" group.long 0xC28++0x3 line.long 0x00 "IRQCE10_SET/CLR,IRC IRQ channel enable setting register 10" sif (!cpuis("S6J33*")) setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[350] ,IRQ (SG ch.3) channel enable setting bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[349] ,IRQ (SG ch.2) channel enable setting bit 349" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[348] ,IRQ (SG ch.1) channel enable setting bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[347] ,IRQ (SG ch.0) channel enable setting bit 347" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[344] ,IRQ (SMC ch.5) channel enable setting bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[343] ,IRQ (SMC ch.4) channel enable setting bit 343" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[342] ,IRQ (SMC ch.3) channel enable setting bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[341] ,IRQ (SMC ch.2) channel enable setting bit 341" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[340] ,IRQ (SMC ch.1) channel enable setting bit 340" "Disabled,Enabled" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[339] ,IRQ (SMC ch.0) channel enable setting bit 339" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[337] ,IRQ (MFS ch.17 Error) channel enable setting bit 337" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[336] ,IRQ (MFS ch.16 Error) channel enable setting bit 336" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[332] ,IRQ (MFS ch.12 Error) channel enable setting bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[331] ,IRQ (MFS ch.11 Error) channel enable setting bit 331" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[330] ,IRQ (MFS ch.10 Error) channel enable setting bit 330" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[329] ,IRQ (MFS ch.9 Error) channel enable setting bit 329" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[328] ,IRQ (MFS ch.8 Error) channel enable setting bit 328" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[324] ,IRQ (MFS ch.4 Error) channel enable setting bit 324" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[323] ,IRQ (MFS ch.3 Error) channel enable setting bit 323" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[322] ,IRQ (MFS ch.2 Error) channel enable setting bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[321] ,IRQ (MFS ch.1 Error) channel enable setting bit 321" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[320] ,IRQ (MFS ch.0 Error) channel enable setting bit 320" "Disabled,Enabled" else sif (!cpuis("S6J335*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[351] ,IRQ (SG ch.4) channel enable setting bit 350" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[350] ,IRQ (SG ch.3) channel enable setting bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[349] ,IRQ (SG ch.2) channel enable setting bit 349" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[348] ,IRQ (SG ch.1) channel enable setting bit 348" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[347] ,IRQ (SG ch.0) channel enable setting bit 347" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[337] ,IRQ (MFS ch.17 Error) channel enable setting bit 337" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[336] ,IRQ (MFS ch.16 Error) channel enable setting bit 336" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[332] ,IRQ (MFS ch.12 Error) channel enable setting bit 332" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[331] ,IRQ (MFS ch.11 Error) channel enable setting bit 331" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[330] ,IRQ (MFS ch.10 Error) channel enable setting bit 330" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[329] ,IRQ (MFS ch.9 Error) channel enable setting bit 329" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[328] ,IRQ (MFS ch.8 Error) channel enable setting bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[324] ,IRQ (MFS ch.4 Error) channel enable setting bit 324" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[323] ,IRQ (MFS ch.3 Error) channel enable setting bit 323" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[322] ,IRQ (MFS ch.2 Error) channel enable setting bit 322" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[321] ,IRQ (MFS ch.1 Error) channel enable setting bit 321" "Disabled,Enabled" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[320] ,IRQ (MFS ch.0 Error) channel enable setting bit 320" "Disabled,Enabled" else setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[337] ,IRQ (MFS ch.17 Error) channel enable setting bit 337" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[336] ,IRQ (MFS ch.16 Error) channel enable setting bit 336" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[332] ,IRQ (MFS ch.12 Error) channel enable setting bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[331] ,IRQ (MFS ch.11 Error) channel enable setting bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[330] ,IRQ (MFS ch.10 Error) channel enable setting bit 330" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[329] ,IRQ (MFS ch.9 Error) channel enable setting bit 329" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[328] ,IRQ (MFS ch.8 Error) channel enable setting bit 328" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[324] ,IRQ (MFS ch.4 Error) channel enable setting bit 324" "Disabled,Enabled" textline " " setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[323] ,IRQ (MFS ch.3 Error) channel enable setting bit 323" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[322] ,IRQ (MFS ch.2 Error) channel enable setting bit 322" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[321] ,IRQ (MFS ch.1 Error) channel enable setting bit 321" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[320] ,IRQ (MFS ch.0 Error) channel enable setting bit 320" "Disabled,Enabled" endif endif group.long 0xC2C++0x3 line.long 0x00 "IRQCE11_SET/CLR,IRC IRQ channel enable setting register 11" sif (!cpuis("S6J334*")) sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[378] ,IRQ (I2S1_IRQ) channel enable setting bit 378" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[377] ,IRQ (I2S0_IRQ) channel enable setting bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[376] ,IRQ (AUDIO_DAC_DMAE_IRQ) channel enable setting bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[375] ,IRQ (AUDIO_DAC_UDRN_IRQ) channel enable setting bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[374] ,IRQ (AUDIO_DAC_OVFL_IRQ) channel enable setting bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[373] ,IRQ (AUDIO_DAC_DREQ) channel enable setting bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[372] ,IRQ (PCMPWM_DMAE) channel enable setting bit 372" "Disabled,Enabled" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[371] ,IRQ (PCMPWM_UDRN) channel enable setting bit 371" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[370] ,IRQ (PCMPWM_OVFL) channel enable setting bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[369] ,IRQ (PCMPWM_DREQ) channel enable setting bit 369" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[368] ,IRQ (Indicator PWM) channel enable setting bit 368" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[364] ,IRQ (ETHERNET Q3 IRQ) channel enable setting bit 364" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[363] ,IRQ (ETHERNET Q2 IRQ) channel enable setting bit 363" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[362] ,IRQ (ETHERNET Q1 IRQ) channel enable setting bit 362" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[361] ,IRQ (ETHERNET IRQ) channel enable setting bit 361" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[360] ,IRQ (MLB system interrupt) channel enable setting bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[359] ,IRQ (MLB channel interrupt) channel enable setting bit 359" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[357] ,IRQ (RPGCRC) channel enable setting bit 357" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[356] ,IRQ (ADC12B RCO) channel enable setting bit 356" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[355] ,IRQ (ADC12B pulse detection function) channel enable setting bit 355" "Disabled,Enabled" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[354] ,IRQ (ADC12B Group interrupt) channel enable setting bit 354" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[353] ,IRQ (ADC12B Conversion Done) channel enable setting bit 353" "Disabled,Enabled" else setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[378] ,IRQ (I2S1_IRQ) channel enable setting bit 378" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[377] ,IRQ (I2S0_IRQ) channel enable setting bit 377" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[368] ,IRQ (Indicator PWM) channel enable setting bit 368" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[364] ,IRQ (ETHERNET Q3 IRQ) channel enable setting bit 364" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[363] ,IRQ (ETHERNET Q2 IRQ) channel enable setting bit 363" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[362] ,IRQ (ETHERNET Q1 IRQ) channel enable setting bit 362" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[361] ,IRQ (ETHERNET IRQ) channel enable setting bit 361" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[360] ,IRQ (MLB system interrupt) channel enable setting bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[359] ,IRQ (MLB channel interrupt) channel enable setting bit 359" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[357] ,IRQ (RPGCRC) channel enable setting bit 357" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[356] ,IRQ (ADC12B RCO) channel enable setting bit 356" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[355] ,IRQ (ADC12B pulse detection function) channel enable setting bit 355" "Disabled,Enabled" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[354] ,IRQ (ADC12B Group interrupt) channel enable setting bit 354" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[353] ,IRQ (ADC12B Conversion Done) channel enable setting bit 353" "Disabled,Enabled" endif else setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[368] ,IRQ (Indicator PWM) channel enable setting bit 368" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[357] ,IRQ (RPGCRC) channel enable setting bit 357" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[356] ,IRQ (ADC12B RCO) channel enable setting bit 356" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[355] ,IRQ (ADC12B pulse detection function) channel enable setting bit 355" "Disabled,Enabled" textline " " setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[354] ,IRQ (ADC12B Group interrupt) channel enable setting bit 354" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[353] ,IRQ (ADC12B Conversion Done) channel enable setting bit 353" "Disabled,Enabled" endif group.long 0xC30++0x3 line.long 0x00 "IRQCE12_SET/CLR,IRC IRQ channel enable setting register 12" sif (cpuis("S6J33*")) setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[409] ,IRQ (2D Graphics Core Display0 Sync1) channel enable setting bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[408] ,IRQ (2D Graphics Core Display0 Sync0) channel enable setting bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[407] ,IRQ (2D Graphics Core Signature0) channel enable setting bit 407" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[406] ,IRQ (2D Graphics Core Display Stream0) channel enable setting bit 406" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[405] ,IRQ (2D Graphics Core Safety Stream0) channel enable setting bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[404] ,IRQ (2D Graphics Core Content Stream0) channel enable setting bit 404" "Disabled,Enabled" setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[403] ,IRQ (2D Graphics Core Drawing Engine) channel enable setting bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[402] ,IRQ (2D Graphics Core Blit Engine) channel enable setting bit 402" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[401] ,IRQ (2D Graphics Core Command Sequencer) channel enable setting bit 401" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[395] ,IRQ (Base Timer ch.31) channel enable setting bit 395" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[394] ,IRQ (Base Timer ch.30) channel enable setting bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. -0x80 9. -0x40 9. " IRQCE[393] ,IRQ (Base Timer ch.29) channel enable setting bit 393" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. -0x80 8. -0x40 8. " IRQCE[392] ,IRQ (Base Timer ch.28) channel enable setting bit 392" "Disabled,Enabled" setclrfld.long 0x00 7. -0x80 7. -0x40 7. " IRQCE[391] ,IRQ (Base Timer ch.27) channel enable setting bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. -0x80 6. -0x40 6. " IRQCE[390] ,IRQ (Base Timer ch.26) channel enable setting bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. -0x80 5. -0x40 5. " IRQCE[389] ,IRQ (Base Timer ch.25) channel enable setting bit 389" "Disabled,Enabled" textline " " sif (cpuis("S6J335*")) setclrfld.long 0x00 4. -0x80 4. -0x40 4. " IRQCE[388] ,IRQ (Base Timer ch.24/32/33/34/35) channel enable setting bit 401" "Disabled,Enabled" else setclrfld.long 0x00 4. -0x80 4. -0x40 4. " IRQCE[388] ,IRQ (Base Timer ch.24) channel enable setting bit 401" "Disabled,Enabled" endif else setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[415] ,IRQ (2D Graphics Core Display1 Sync1) channel enable setting bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[414] ,IRQ (2D Graphics Core Display1 Sync0) channel enable setting bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[413] ,IRQ (2D Graphics Core Signature1) channel enable setting bit 413" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[412] ,IRQ (2D Graphics Core Display Stream1) channel enable setting bit 412" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[411] ,IRQ (2D Graphics Core Safety Stream1) channel enable setting bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[410] ,IRQ (2D Graphics Core Content Stream1) channel enable setting bit 410" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[409] ,IRQ (2D Graphics Core Display0 Sync1) channel enable setting bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[408] ,IRQ (2D Graphics Core Display0 Sync0) channel enable setting bit 408" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[407] ,IRQ (2D Graphics Core Signature0) channel enable setting bit 407" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[406] ,IRQ (2D Graphics Core Display Stream0) channel enable setting bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[405] ,IRQ (2D Graphics Core Safety Stream0) channel enable setting bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[404] ,IRQ (2D Graphics Core Content Stream0) channel enable setting bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[403] ,IRQ (2D Graphics Core Drawing Engine) channel enable setting bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[402] ,IRQ (2D Graphics Core Blit Engine) channel enable setting bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[401] ,IRQ (2D Graphics Core Command Sequencer) channel enable setting bit 401" "Disabled,Enabled" endif group.long 0xC34++0x3 line.long 0x00 "IRQCE13_SET/CLR,IRC IRQ channel enable setting register 13" sif (cpuis("S6J33*")) sif (!cpuis("S6J335*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[447] ,IRQ (MX_OVFL_IRQ4) channel enable setting bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[446] ,IRQ (MX_OVFL_IRQ3) channel enable setting bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[445] ,IRQ (MX_OVFL_IRQ2) channel enable setting bit 445" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[444] ,IRQ (MX_OVFL_IRQ1) channel enable setting bit 444" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[443] ,IRQ (MX_OVFL_IRQ0) channel enable setting bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[442] ,IRQ (MX_DATA_REQ_IRQ4) channel enable setting bit 442" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[441] ,IRQ (MX_DATA_REQ_IRQ3) channel enable setting bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[440] ,IRQ (MX_DATA_REQ_IRQ2) channel enable setting bit 440" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[439] ,IRQ (MX_DATA_REQ_IRQ1) channel enable setting bit 439" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[438] ,IRQ (MX_DATA_REQ_IRQ0) channel enable setting bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[437] ,IRQ (WG_AHB_ERR_IRQ) channel enable setting bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[436] ,IRQ (WG_END_IRQ4) channel enable setting bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[435] ,IRQ (WG_END_IRQ3) channel enable setting bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[434] ,IRQ (WG_END_IRQ2) channel enable setting bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[433] ,IRQ (WG_END_IRQ1) channel enable setting bit 433" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[432] ,IRQ (WG_END_IRQ0) channel enable setting bit 432" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[423] ,IRQ (2D Graphics Core LCDBusIf_Control) channel enable setting bit 423" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[422] ,IRQ (2D Graphics Core LCDBusIf_InstrFifo) channel enable setting bit 422" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[421] ,IRQ (2D Graphics Core LCDBusIf_Control) channel enable setting bit 421" "Disabled,Enabled" else setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[447] ,IRQ (MX_OVFL_IRQ4) channel enable setting bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[446] ,IRQ (MX_OVFL_IRQ3) channel enable setting bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[445] ,IRQ (MX_OVFL_IRQ2) channel enable setting bit 445" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[444] ,IRQ (MX_OVFL_IRQ1) channel enable setting bit 444" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[443] ,IRQ (MX_OVFL_IRQ0) channel enable setting bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[442] ,IRQ (MX_DATA_REQ_IRQ4) channel enable setting bit 442" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[441] ,IRQ (MX_DATA_REQ_IRQ3) channel enable setting bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[440] ,IRQ (MX_DATA_REQ_IRQ2) channel enable setting bit 440" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[439] ,IRQ (MX_DATA_REQ_IRQ1) channel enable setting bit 439" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[438] ,IRQ (MX_DATA_REQ_IRQ0) channel enable setting bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[437] ,IRQ (WG_AHB_ERR_IRQ) channel enable setting bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[436] ,IRQ (WG_END_IRQ4) channel enable setting bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[435] ,IRQ (WG_END_IRQ3) channel enable setting bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[434] ,IRQ (WG_END_IRQ2) channel enable setting bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[433] ,IRQ (WG_END_IRQ1) channel enable setting bit 433" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[432] ,IRQ (WG_END_IRQ0) channel enable setting bit 432" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[428] ,IRQ (3D Graphics Core SBEI) channel enable setting bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " IRQCE[427] ,IRQ (3D Graphics Core BEI) channel enable setting bit 427" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[426] ,IRQ (3D Graphics Core CAEI) channel enable setting bit 426" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[425] ,IRQ (3D Graphics Core DEI) channel enable setting bit 425" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[424] ,IRQ (3D Graphics Core DLEI) channel enable setting bit 424" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[423] ,IRQ (3D Graphics Core DFI) channel enable setting bit 423" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[422] ,IRQ (3D Graphics Core LINI) channel enable setting bit 422" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[421] ,IRQ (3D Graphics Core SRUI) channel enable setting bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 04. -0x80 04. -0x40 04. " IRQCE[420] ,IRQ (2D Graphics Core DDRHSSPI) channel enable setting bit 420" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[419] ,IRQ (2D Graphics Core Histogram) channel enable setting bit 419" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[418] ,IRQ (2D Graphics Core Storage Stream0) channel enable setting bit 418" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[417] ,IRQ (2D Graphics Core Display Plane0) channel enable setting bit 417" "Disabled,Enabled" textline " " setclrfld.long 0x00 00. -0x80 00. -0x40 00. " IRQCE[416] ,IRQ (2D Graphics Core Capture Plane0) channel enable setting bit 416" "Disabled,Enabled" endif group.long 0xC38++0x3 line.long 0x00 "IRQCE14_SET/CLR,IRC IRQ channel enable setting register 14" sif (cpuis("S6J33*")) sif (cpuis("S6J331*")) setclrfld.long 0x00 13. -0x80 13. -0x40 13. " IRQCE[461] ,IRQ (ARH IRQ2) channel enable setting bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " IRQCE[460] ,IRQ (ARH IRQ1) channel enable setting bit 460" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[458] ,IRQ (MX_AHB_ERR_IRQ) channel enable setting bit 458" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[457] ,IRQ (MX_DMA_ERR_IRQ4) channel enable setting bit 457" "Disabled,Enabled" textline " " setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[456] ,IRQ (MX_DMA_ERR_IRQ3) channel enable setting bit 456" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[455] ,IRQ (MX_DMA_ERR_IRQ2) channel enable setting bit 455" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[454] ,IRQ (MX_DMA_ERR_IRQ1) channel enable setting bit 454" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[453] ,IRQ (MX_DMA_ERR_IRQ0) channel enable setting bit 453" "Disabled,Enabled" elif (cpuis("S6J333*")) setclrfld.long 0x00 19. -0x80 19. -0x40 19. " IRQCE[467] ,IRQ (ADC12B1 RCO) channel enable setting bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " IRQCE[466] ,IRQ (ADC12B1 pulse detection function) channel enable setting bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " IRQCE[465] ,IRQ (ADC12B1 Group interrupt) channel enable setting bit 465" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[464] ,IRQ (ADC12B1 Conversion Done) channel enable setting bit 464" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[458] ,IRQ (MX_AHB_ERR_IRQ) channel enable setting bit 458" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[457] ,IRQ (MX_DMA_ERR_IRQ4) channel enable setting bit 457" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[456] ,IRQ (MX_DMA_ERR_IRQ3) channel enable setting bit 456" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[455] ,IRQ (MX_DMA_ERR_IRQ2) channel enable setting bit 455" "Disabled,Enabled" textline " " setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[454] ,IRQ (MX_DMA_ERR_IRQ1) channel enable setting bit 454" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[453] ,IRQ (MX_DMA_ERR_IRQ0) channel enable setting bit 453" "Disabled,Enabled" elif (cpuis("S6J335*")) setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[479] ,IRQ (Base Timer ch.51) channel enable setting bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[478] ,IRQ (Base Timer ch.50) channel enable setting bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[477] ,IRQ (Base Timer ch.49) channel enable setting bit 477" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[476] ,IRQ (Base Timer ch.48/56/57/58/59) channel enable setting bit 476" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[475] ,IRQ (Base Timer ch.43) channel enable setting bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[474] ,IRQ (Base Timer ch.42) channel enable setting bit 474" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[473] ,IRQ (Base Timer ch.41) channel enable setting bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[472] ,IRQ (Base Timer ch.40) channel enable setting bit 472" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x80 23. -0x40 23. " IRQCE[471] ,IRQ (Base Timer ch.39) channel enable setting bit 471" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " IRQCE[470] ,IRQ (Base Timer ch.38) channel enable setting bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " IRQCE[469] ,IRQ (Base Timer ch.37) channel enable setting bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[468] ,IRQ (Base Timer ch.36/44/45/46/47) channel enable setting bit 468" "Disabled,Enabled" else setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[458] ,IRQ (MX_AHB_ERR_IRQ) channel enable setting bit 458" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[457] ,IRQ (MX_DMA_ERR_IRQ4) channel enable setting bit 457" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[456] ,IRQ (MX_DMA_ERR_IRQ3) channel enable setting bit 456" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[455] ,IRQ (MX_DMA_ERR_IRQ2) channel enable setting bit 455" "Disabled,Enabled" textline " " setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[454] ,IRQ (MX_DMA_ERR_IRQ1) channel enable setting bit 454" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[453] ,IRQ (MX_DMA_ERR_IRQ0) channel enable setting bit 453" "Disabled,Enabled" endif else setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[458] ,IRQ (MX_AHB_ERR_IRQ) channel enable setting bit 458" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " IRQCE[457] ,IRQ (MX_DMA_ERR_IRQ4) channel enable setting bit 457" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[456] ,IRQ (MX_DMA_ERR_IRQ3) channel enable setting bit 456" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " IRQCE[455] ,IRQ (MX_DMA_ERR_IRQ2) channel enable setting bit 455" "Disabled,Enabled" textline " " setclrfld.long 0x00 06. -0x80 06. -0x40 06. " IRQCE[454] ,IRQ (MX_DMA_ERR_IRQ1) channel enable setting bit 454" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " IRQCE[453] ,IRQ (MX_DMA_ERR_IRQ0) channel enable setting bit 453" "Disabled,Enabled" endif sif (cpuis("S6J335*")) group.long 0xC3C++0x3 line.long 0x00 "IRQCE15_SET/CLR,IRC IRQ channel enable setting register 15" setclrfld.long 0x00 7. -0x80 7. -0x40 7. " IRQCE[487] ,IRQ (Base Timer ch.63) channel enable setting bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. -0x80 6. -0x40 6. " IRQCE[486] ,IRQ (Base Timer ch.62) channel enable setting bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. -0x80 5. -0x40 5. " IRQCE[485] ,IRQ (Base Timer ch.61) channel enable setting bit 485" "Disabled,Enabled" setclrfld.long 0x00 4. -0x80 4. -0x40 4. " IRQCE[484] ,IRQ (Base Timer ch.60) channel enable setting bit 484" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x80 3. -0x40 3. " IRQCE[483] ,IRQ (Base Timer ch.55) channel enable setting bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. -0x80 2. -0x40 2. " IRQCE[482] ,IRQ (Base Timer ch.54) channel enable setting bit 482" "Disabled,Enabled" setclrfld.long 0x00 1. -0x80 1. -0x40 1. " IRQCE[481] ,IRQ (Base Timer ch.53) channel enable setting bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. -0x80 0. -0x40 0. " IRQCE[480] ,IRQ (Base Timer ch.52) channel enable setting bit 480" "Disabled,Enabled" endif tree.end textline " " width 15. group.long 0xC40++0x3 line.long 0x00 "NMIHC,IRC NMI Hold Clear Register" bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif (cpuis("S6J33*")) rgroup.long 0xC44++0x3 line.long 0x00 "NMIHS,IRC NMI Hold Status Register" sif (!cpuis("S6J335*")) sif (!cpuis("S6J334*")) bitfld.long 0x00 23. " NMIHS[23] ,NMI23 (ETHERNET_MPU_NMI) hold status bit" "Not applied,Applied" bitfld.long 0x00 22. " NMIHS[22] ,NMI22 (MLB_MPU_NMI) hold status bit" "Not applied,Applied" bitfld.long 0x00 21. " NMIHS[21] ,NMI21 (2D Graphics Core_NMI[1]) hold status bit" "Not applied,Applied" bitfld.long 0x00 20. " NMIHS[20] ,NMI20 (2D Graphics Core_NMI[0]) hold status bit" "Not applied,Applied" else bitfld.long 0x00 21. " NMIHS[21] ,NMI21 (2D Graphics Core_NMI[1]) hold status bit" "Not applied,Applied" bitfld.long 0x00 20. " NMIHS[20] ,NMI20 (2D Graphics Core_NMI[0]) hold status bit" "Not applied,Applied" endif textline " " endif bitfld.long 0x00 18. " NMIHS[18] ,NMI18 (TPU protection violation) hold status bit" "Not applied,Applied" bitfld.long 0x00 15. " NMIHS[15] ,NMI15 (SHE MPU) hold status bit" "Not applied,Applied" bitfld.long 0x00 13. " NMIHS[13] ,NMI13 (DMAC MPU #0 protection violation) hold status bit" "Not applied,Applied" textline " " bitfld.long 0x00 12. " NMIHS[12] ,NMI12 (M-CAN RAMs 2-bit ECC error detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 11. " NMIHS[11] ,NMI11 (Backup RAM 2-bit ECC error detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 08. " NMIHS[08] ,NMI8 (IRC 2-bit ECC err detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 07. " NMIHS[07] ,NMI7 (SW-WDT) hold status bit" "Not applied,Applied" textline " " bitfld.long 0x00 06. " NMIHS[06] ,NMI6 (HW-WDT) hold status bit" "Not applied,Applied" bitfld.long 0x00 05. " NMIHS[05] ,NMI5 (CSV, Profile) hold status bit" "Not applied,Applied" bitfld.long 0x00 04. " NMIHS[04] ,NMI4 (LVDs IRQ) hold status bit" "Not applied,Applied" bitfld.long 0x00 00. " NMIHS[00] ,NMI0 (NMIX pin(Ext-IRC)) hold status bit" "Not applied,Applied" else group.long 0xC44++0x3 line.long 0x00 "NMIHS_SET/CLR,IRC NMI Hold Status Register" setclrfld.long 0x00 23. -0x08 23. -0x04 23. " NMIHS[23] ,NMI23 (ETHERNET_MPU_NMI) hold status bit" "Not applied,Applied" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " NMIHS[22] ,NMI22 (MLB_MPU_NMI) hold status bit" "Not applied,Applied" setclrfld.long 0x00 21. -0x08 21. -0x04 21. " NMIHS[21] ,NMI21 (2D Graphics Core_NMI[1]) hold status bit" "Not applied,Applied" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " NMIHS[20] ,NMI20 (2D Graphics Core_NMI[0]) hold status bit" "Not applied,Applied" textline " " setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMIHS[18] ,NMI18 (TPU protection violation) hold status bit" "Not applied,Applied" setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NMIHS[15] ,NMI15 (SHE MPU) hold status bit" "Not applied,Applied" textline " " sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU") setclrfld.long 0x00 14. -0x08 14. -0x04 14. " NMIHS[14] ,NMI14 (DMAC MPU #1 protection violation) hold status bit" "Not applied,Applied" textline " " endif setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMIHS[13] ,NMI13 (DMAC MPU #0 protection violation) hold status bit" "Not applied,Applied" textline " " setclrfld.long 0x00 12. -0x08 12. -0x04 12. " NMIHS[12] ,NMI12 (M-CAN RAMs 2-bit ECC error detection) hold status bit" "Not applied,Applied" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " NMIHS[11] ,NMI11 (Backup RAM 2-bit ECC error detection) hold status bit" "Not applied,Applied" setclrfld.long 0x00 08. -0x08 08. -0x04 08. " NMIHS[08] ,NMI8 (IRC 2-bit ECC err detection) hold status bit" "Not applied,Applied" setclrfld.long 0x00 07. -0x08 07. -0x04 07. " NMIHS[07] ,NMI7 (SW-WDT) hold status bit" "Not applied,Applied" textline " " setclrfld.long 0x00 06. -0x08 06. -0x04 06. " NMIHS[06] ,NMI6 (HW-WDT) hold status bit" "Not applied,Applied" setclrfld.long 0x00 05. -0x08 05. -0x04 05. " NMIHS[05] ,NMI5 (CSV, Profile) hold status bit" "Not applied,Applied" setclrfld.long 0x00 04. -0x08 04. -0x04 04. " NMIHS[04] ,NMI4 (LVDs IRQ) hold status bit" "Not applied,Applied" setclrfld.long 0x00 00. -0x08 01. -0x04 00. " NMIHS[00] ,NMI0 (NMIX pin(Ext-IRC)) hold status bit" "Not applied,Applied" endif textline " " group.long 0xC48++0x3 line.long 0x00 "IRQHC,IRC IRQ Hold Clear Register" hexmask.long.word 0x00 0.--8. 1. " IRQHCN ,Bits for IRQ channel number for which holds to be cleared" width 9. tree "IRQHS IRC IRQ Hold Status Registers" rgroup.long 0xC50++0x3 line.long 0x00 "IRQHS0,IRC IRQ Hold Status Register 0" bitfld.long 0x00 31. " IRQHS[31] ,IRQ (External Interrupt Request ch.7) hold status bit 31" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[30] ,IRQ (External Interrupt Request ch.6) hold status bit 30" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[29] ,IRQ (External Interrupt Request ch.5) hold status bit 29" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[28] ,IRQ (External Interrupt Request ch.4) hold status bit 28" "Not applied,Applied" textline " " bitfld.long 0x00 27. " IRQHS[27] ,IRQ (External Interrupt Request ch.3) hold status bit 27" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[26] ,IRQ (External Interrupt Request ch.2) hold status bit 26" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[25] ,IRQ (External Interrupt Request ch.1) hold status bit 25" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[24] ,IRQ (External Interrupt Request ch.0) hold status bit 24" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[23] ,IRQ (EICU) hold status bit 23" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[20] ,IRQ (Work FLASH Write Completion) hold status bit 20" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[16] ,IRQ (IRC Vector Address RAM Single Bit Error) hold status bit 16" "Not applied,Applied" bitfld.long 0x00 15. " IRQHS[15] ,IRQ (Backup RAM / CAN FD RAM(ch.0,1,5,6) Single Bit Error) hold status bit 15" "Not applied,Applied" textline " " bitfld.long 0x00 14. " IRQHS[14] ,IRQ (System RAM Single Bit Error) hold status bit 14" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[10] ,IRQ (Work FLASH Single Bit Error) hold status bit 10" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[8] ,IRQ (TCFLASH Single Bit Error) hold status bit 08" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[3] ,IRQ (SW-WDT Pre-warning) hold status bit 03" "Not applied,Applied" textline " " bitfld.long 0x00 02. " IRQHS[2] ,IRQ (HW-WDT Pre-warning) hold status bit 02" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[1] ,IRQ (System Control Status) hold status bit 01" "Not applied,Applied" rgroup.long 0xC54++0x3 line.long 0x00 "IRQHS1,IRC IRQ Hold Status Register 1" sif (cpuis("S6J335*")) bitfld.long 0x00 28. " IRQHS[60] ,IRQ (CAN FD ch.4) hold status bit 60" "Not applied,Applied" bitfld.long 0x00 27. " IRQHS[59] ,IRQ (CAN FD ch.3) hold status bit 59" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[58] ,IRQ (CAN FD ch.2) hold status bit 58" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[57] ,IRQ (CAN FD ch.1) hold status bit 57" "Not applied,Applied" textline " " bitfld.long 0x00 24. " IRQHS[56] ,IRQ (CAN FD ch.0) hold status bit 56" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[50] ,IRQ (CAN FD ch.7) hold status bit 50" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[49] ,IRQ (CAN FD ch.6) hold status bit 49" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[48] ,IRQ (CAN FD ch.5) hold status bit 48" "Not applied,Applied" elif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) bitfld.long 0x00 28. " IRQHS[60] ,IRQ (CAN FD ch.4) hold status bit 60" "Not applied,Applied" bitfld.long 0x00 27. " IRQHS[59] ,IRQ (CAN FD ch.3) hold status bit 59" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[58] ,IRQ (CAN FD ch.2) hold status bit 58" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[57] ,IRQ (CAN FD ch.1) hold status bit 57" "Not applied,Applied" textline " " bitfld.long 0x00 24. " IRQHS[56] ,IRQ (CAN FD ch.0) hold status bit 56" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[48] ,IRQ (CAN FD ch.5) hold status bit 48" "Not applied,Applied" else bitfld.long 0x00 25. " IRQHS[57] ,IRQ (CAN FD ch.1) hold status bit 57" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[56] ,IRQ (CAN FD ch.0) hold status bit 56" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[49] ,IRQ (CAN FD ch.6) hold status bit 49" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[48] ,IRQ (CAN FD ch.5) hold status bit 48" "Not applied,Applied" endif textline " " bitfld.long 0x00 14. " IRQHS[46] ,IRQ (Reload Timer ch.48,49 OR-ed) hold status bit 46" "Not applied,Applied" bitfld.long 0x00 11. " IRQHS[43] ,IRQ (MFS TX ch.17) hold status bit 43" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[42] ,IRQ (MFS RX ch.17) hold status bit 42" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[41] ,IRQ (MFS TX ch.16) hold status bit 41" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[40] ,IRQ (MFS RX ch.16) hold status bit 40" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[39] ,IRQ (External Interrupt Request ch.15) hold status bit 39" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[38] ,IRQ (External Interrupt Request ch.14) hold status bit 38" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[37] ,IRQ (External Interrupt Request ch.13) hold status bit 37" "Not applied,Applied" textline " " bitfld.long 0x00 04. " IRQHS[36] ,IRQ (External Interrupt Request ch.12) hold status bit 36" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[35] ,IRQ (External Interrupt Request ch.11) hold status bit 35" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[34] ,IRQ (External Interrupt Request ch.10) hold status bit 34" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[33] ,IRQ (External Interrupt Request ch.9) hold status bit 33" "Not applied,Applied" textline " " bitfld.long 0x00 00. " IRQHS[32] ,IRQ (External Interrupt Request ch.8) hold status bit 32" "Not applied,Applied" rgroup.long 0xC58++0x3 line.long 0x00 "IRQHS2,IRC IRQ Hold Status Register 2" bitfld.long 0x00 25. " IRQHS[89] ,IRQ (MFS TX ch.12) hold status bit 89" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[88] ,IRQ (MFS RX ch.12) hold status bit 88" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[87] ,IRQ (MFS TX ch.11) hold status bit 87" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[86] ,IRQ (MFS RX ch.11) hold status bit 86" "Not applied,Applied" textline " " bitfld.long 0x00 21. " IRQHS[85] ,IRQ (MFS TX ch.10) hold status bit 85" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[84] ,IRQ (MFS RX ch.10) hold status bit 84" "Not applied,Applied" bitfld.long 0x00 19. " IRQHS[83] ,IRQ (MFS TX ch.9) hold status bit 83" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[82] ,IRQ (MFS RX ch.9) hold status bit 82" "Not applied,Applied" textline " " bitfld.long 0x00 17. " IRQHS[81] ,IRQ (MFS TX ch.8) hold status bit 81" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[80] ,IRQ (MFS RX ch.8) hold status bit 80" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[73] ,IRQ (MFS TX ch.4) hold status bit 73" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[72] ,IRQ (MFS RX ch.4) hold status bit 72" "Not applied,Applied" textline " " bitfld.long 0x00 07. " IRQHS[71] ,IRQ (MFS TX ch.3) hold status bit 71" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[70] ,IRQ (MFS RX ch.3) hold status bit 70" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[69] ,IRQ (MFS TX ch.2) hold status bit 69" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[68] ,IRQ (MFS RX ch.2) hold status bit 68" "Not applied,Applied" textline " " bitfld.long 0x00 03. " IRQHS[67] ,IRQ (MFS TX ch.1) hold status bit 67" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[66] ,IRQ (MFS RX ch.1) hold status bit 66" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[65] ,IRQ (MFS TX ch.0) hold status bit 65" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[64] ,IRQ (MFS RX ch.0) hold status bit 64" "Not applied,Applied" rgroup.long 0xC5C++0x3 line.long 0x00 "IRQHS3,IRC IRQ Hold Status Register 3" bitfld.long 0x00 21. " IRQHS[117] ,IRQ (CR CARIBRATION) hold status bit 117" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[116] ,IRQ (RTC) hold status bit 116" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[112] ,IRQ (BACKUP RAM) hold status bit 112" "Not applied,Applied" bitfld.long 0x00 14. " IRQHS[110] ,IRQ (TCRAM) hold status bit 110" "Not applied,Applied" textline " " bitfld.long 0x00 07. " IRQHS[103] ,IRQ (DDR HSSPI TX) hold status bit 103" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[102] ,IRQ (DDR HSSPI RX) hold status bit 102" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[101] ,IRQ (SHE) hold status bit 101" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[100] ,IRQ (SHE Error) hold status bit 100" "Not applied,Applied" rgroup.long 0xC60++0x3 line.long 0x00 "IRQHS4,IRC IRQ Hold Status Register 4" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQHS[155] ,IRQ (Reload Timer ch.3) hold status bit 155" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[154] ,IRQ (Reload Timer ch.2) hold status bit 154" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[153] ,IRQ (Reload Timer ch.1) hold status bit 153" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[152] ,IRQ (Reload Timer ch.0) hold status bit 152" "Not applied,Applied" else bitfld.long 0x00 25. " IRQHS[153] ,IRQ (Reload Timer ch.1) hold status bit 153" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[152] ,IRQ (Reload Timer ch.0) hold status bit 152" "Not applied,Applied" endif textline " " bitfld.long 0x00 15. " IRQHS[143] ,IRQ (Base Timer ch.19) hold status bit 143" "Not applied,Applied" bitfld.long 0x00 14. " IRQHS[142] ,IRQ (Base Timer ch.18) hold status bit 142" "Not applied,Applied" bitfld.long 0x00 13. " IRQHS[141] ,IRQ (Base Timer ch.17) hold status bit 141" "Not applied,Applied" bitfld.long 0x00 12. " IRQHS[140] ,IRQ (Base Timer ch.16) hold status bit 140" "Not applied,Applied" textline " " bitfld.long 0x00 11. " IRQHS[139] ,IRQ (Base Timer ch.15) hold status bit 139" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[138] ,IRQ (Base Timer ch.14) hold status bit 138" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[137] ,IRQ (Base Timer ch.13) hold status bit 137" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[136] ,IRQ (Base Timer ch.12/20/21/22/23) hold status bit 136" "Not applied,Applied" textline " " bitfld.long 0x00 07. " IRQHS[135] ,IRQ (Base Timer ch.7) hold status bit 135" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[134] ,IRQ (Base Timer ch.6) hold status bit 134" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[133] ,IRQ (Base Timer ch.5) hold status bit 133" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[132] ,IRQ (Base Timer ch.4) hold status bit 132" "Not applied,Applied" textline " " bitfld.long 0x00 03. " IRQHS[131] ,IRQ (Base Timer ch.3) hold status bit 131" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[130] ,IRQ (Base Timer ch.2) hold status bit 130" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[129] ,IRQ (Base Timer ch.1) hold status bit 129" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[128] ,IRQ (Base Timer ch.0/8/9/10/11) hold status bit 128" "Not applied,Applied" rgroup.long 0xC64++0x3 line.long 0x00 "IRQHS5,IRC IRQ Hold Status Register 5" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQHS[187] ,IRQ (FRT ch.11) hold status bit 187" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[186] ,IRQ (FRT ch.10) hold status bit 186" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[185] ,IRQ (FRT ch.9) hold status bit 185" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[184] ,IRQ (FRT ch.8) hold status bit 184" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[183] ,IRQ (FRT ch.7) hold status bit 183" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[182] ,IRQ (FRT ch.6) hold status bit 182" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[181] ,IRQ (FRT ch.5) hold status bit 181" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[180] ,IRQ (FRT ch.4) hold status bit 180" "Not applied,Applied" else bitfld.long 0x00 26. " IRQHS[186] ,IRQ (FRT ch.10) hold status bit 186" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[185] ,IRQ (FRT ch.9) hold status bit 185" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[184] ,IRQ (FRT ch.8) hold status bit 184" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[180] ,IRQ (FRT ch.4) hold status bit 180" "Not applied,Applied" endif textline " " bitfld.long 0x00 19. " IRQHS[179] ,IRQ (FRT ch.3) hold status bit 179" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[178] ,IRQ (FRT ch.2) hold status bit 178" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[177] ,IRQ (FRT ch.1) hold status bit 177" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[176] ,IRQ (FRT ch.0) hold status bit 176" "Not applied,Applied" textline " " sif (!cpuis("S6J33*")) bitfld.long 0x00 11. " IRQHS[171] ,IRQ (Reload Timer ch.35) hold status bit 171" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[170] ,IRQ (Reload Timer ch.34) hold status bit 170" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[169] ,IRQ (Reload Timer ch.33) hold status bit 169" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[168] ,IRQ (Reload Timer ch.32) hold status bit 168" "Not applied,Applied" textline " " bitfld.long 0x00 03. " IRQHS[163] ,IRQ (Reload Timer ch.19) hold status bit 163" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[162] ,IRQ (Reload Timer ch.18) hold status bit 162" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[161] ,IRQ (Reload Timer ch.17) hold status bit 161" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[160] ,IRQ (Reload Timer ch.16) hold status bit 160" "Not applied,Applied" else bitfld.long 0x00 01. " IRQHS[161] ,IRQ (Reload Timer ch.17) hold status bit 161" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[160] ,IRQ (Reload Timer ch.16) hold status bit 160" "Not applied,Applied" endif rgroup.long 0xC68++0x3 line.long 0x00 "IRQHS6,IRC IRQ Hold Status Register 6" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQHS[219] ,IRQ (IRQ0 of Output Compare 11) hold status bit 219" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[218] ,IRQ (IRQ0 of Output Compare 10) hold status bit 218" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[217] ,IRQ (IRQ0 of Output Compare 9) hold status bit 217" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[216] ,IRQ (IRQ0 of Output Compare 8) hold status bit 216" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[215] ,IRQ (IRQ0 of Output Compare 7) hold status bit 215" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[214] ,IRQ (IRQ0 of Output Compare 6) hold status bit 214" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[213] ,IRQ (IRQ0 of Output Compare 5) hold status bit 213" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[212] ,IRQ (IRQ0 of Output Compare 4) hold status bit 212" "Not applied,Applied" textline " " bitfld.long 0x00 19. " IRQHS[211] ,IRQ (IRQ0 of Output Compare 3) hold status bit 211" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[210] ,IRQ (IRQ0 of Output Compare 2) hold status bit 210" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[209] ,IRQ (IRQ0 of Output Compare 1) hold status bit 209" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[208] ,IRQ (IRQ0 of Output Compare 0) hold status bit 208" "Not applied,Applied" textline " " bitfld.long 0x00 11. " IRQHS[203] ,IRQ (IRQ0 of Input Capture 11) hold status bit 203" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[202] ,IRQ (IRQ0 of Input Capture 10) hold status bit 202" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[201] ,IRQ (IRQ0 of Input Capture 9) hold status bit 201" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[200] ,IRQ (IRQ0 of Input Capture 8) hold status bit 200" "Not applied,Applied" textline " " bitfld.long 0x00 07. " IRQHS[199] ,IRQ (IRQ0 of Input Capture 7) hold status bit 199" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[198] ,IRQ (IRQ0 of Input Capture 6) hold status bit 198" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[197] ,IRQ (IRQ0 of Input Capture 5) hold status bit 197" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[196] ,IRQ (IRQ0 of Input Capture 4) hold status bit 196" "Not applied,Applied" textline " " bitfld.long 0x00 03. " IRQHS[195] ,IRQ (IRQ0 of Input Capture 3) hold status bit 195" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[194] ,IRQ (IRQ0 of Input Capture 2) hold status bit 194" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[193] ,IRQ (IRQ0 of Input Capture 1) hold status bit 193" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[192] ,IRQ (IRQ0 of Input Capture 0) hold status bit 192" "Not applied,Applied" else bitfld.long 0x00 26. " IRQHS[218] ,IRQ (IRQ0 of Output Compare 10) hold status bit 218" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[217] ,IRQ (IRQ0 of Output Compare 9) hold status bit 217" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[216] ,IRQ (IRQ0 of Output Compare 8) hold status bit 216" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[210] ,IRQ (IRQ0 of Output Compare 2) hold status bit 210" "Not applied,Applied" textline " " bitfld.long 0x00 17. " IRQHS[209] ,IRQ (IRQ0 of Output Compare 1) hold status bit 209" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[208] ,IRQ (IRQ0 of Output Compare 0) hold status bit 208" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[202] ,IRQ (IRQ0 of Input Capture 10) hold status bit 202" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[201] ,IRQ (IRQ0 of Input Capture 9) hold status bit 201" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[200] ,IRQ (IRQ0 of Input Capture 8) hold status bit 200" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[194] ,IRQ (IRQ0 of Input Capture 2) hold status bit 194" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[193] ,IRQ (IRQ0 of Input Capture 1) hold status bit 193" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[192] ,IRQ (IRQ0 of Input Capture 0) hold status bit 192" "Not applied,Applied" endif rgroup.long 0xC6C++0x3 line.long 0x00 "IRQHS7,IRC IRQ Hold Status Register 7" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQHS[251] ,IRQ (IRQ1 of Input Capture 11) hold status bit 251" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[250] ,IRQ (IRQ1 of Input Capture 10) hold status bit 250" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[249] ,IRQ (IRQ1 of Input Capture 9) hold status bit 249" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[248] ,IRQ (IRQ1 of Input Capture 8) hold status bit 248" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[247] ,IRQ (IRQ1 of Input Capture 7) hold status bit 248" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[246] ,IRQ (IRQ1 of Input Capture 6) hold status bit 246" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[245] ,IRQ (IRQ1 of Input Capture 5) hold status bit 245" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[244] ,IRQ (IRQ1 of Input Capture 4) hold status bit 244" "Not applied,Applied" textline " " bitfld.long 0x00 19. " IRQHS[243] ,IRQ (IRQ1 of Input Capture 3) hold status bit 243" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[242] ,IRQ (IRQ1 of Input Capture 2) hold status bit 242" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[241] ,IRQ (IRQ1 of Input Capture 1) hold status bit 241" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[240] ,IRQ (IRQ1 of Input Capture 0) hold status bit 240" "Not applied,Applied" textline " " bitfld.long 0x00 09. " IRQHS[233] ,IRQ (QPRC ch.9) hold status bit 233" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[232] ,IRQ (QPRC ch.8) hold status bit 232" "Not applied,Applied" else bitfld.long 0x00 26. " IRQHS[250] ,IRQ (IRQ1 of Input Capture 10) hold status bit 250" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[249] ,IRQ (IRQ1 of Input Capture 9) hold status bit 249" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[248] ,IRQ (IRQ1 of Input Capture 8) hold status bit 248" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[242] ,IRQ (IRQ1 of Input Capture 2) hold status bit 242" "Not applied,Applied" textline " " bitfld.long 0x00 17. " IRQHS[241] ,IRQ (IRQ1 of Input Capture 1) hold status bit 241" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[240] ,IRQ (IRQ1 of Input Capture 0) hold status bit 240" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[233] ,IRQ (QPRC ch.9) hold status bit 233" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[232] ,IRQ (QPRC ch.8) hold status bit 232" "Not applied,Applied" endif rgroup.long 0xC70++0x3 line.long 0x00 "IRQHS8,IRC IRQ Hold Status Register 8" sif (!cpuis("S6J33*")) bitfld.long 0x00 31. " IRQHS[287] ,IRQ (DMAC Completion ch.10) hold status bit 287" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[286] ,IRQ (DMAC Completion ch.9) hold status bit 286" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[285] ,IRQ (DMAC Completion ch.8) hold status bit 285" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) hold status bit 282" "Not applied,Applied" textline " " bitfld.long 0x00 24. " IRQHS[280] ,IRQ (DMAC Completion ch.7) hold status bit 280" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[279] ,IRQ (DMAC Completion ch.6) hold status bit 279" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[278] ,IRQ (DMAC Completion ch.5) hold status bit 278" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[277] ,IRQ (DMAC Completion ch.4) hold status bit 277" "Not applied,Applied" textline " " bitfld.long 0x00 20. " IRQHS[276] ,IRQ (DMAC Completion ch.3) hold status bit 276" "Not applied,Applied" bitfld.long 0x00 19. " IRQHS[275] ,IRQ (DMAC Completion ch.2) hold status bit 275" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[274] ,IRQ (DMAC Completion ch.1) hold status bit 274" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[273] ,IRQ (DMAC Completion ch.0) hold status bit 273" "Not applied,Applied" textline " " bitfld.long 0x00 16. " IRQHS[272] ,IRQ (DMA Error) hold status bit 272" "Not applied,Applied" bitfld.long 0x00 11. " IRQHS[267] ,IRQ (IRQ1 of Output Compare 11) hold status bit 267" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[266] ,IRQ (IRQ1 of Output Compare 10) hold status bit 266" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[265] ,IRQ (IRQ1 of Output Compare 9) hold status bit 265" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[264] ,IRQ (IRQ1 of Output Compare 8) hold status bit 264" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[263] ,IRQ (IRQ1 of Output Compare 7) hold status bit 263" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[262] ,IRQ (IRQ1 of Output Compare 6) hold status bit 262" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[261] ,IRQ (IRQ1 of Output Compare 5) hold status bit 261" "Not applied,Applied" textline " " bitfld.long 0x00 04. " IRQHS[260] ,IRQ (IRQ1 of Output Compare 4) hold status bit 260" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[259] ,IRQ (IRQ1 of Output Compare 3) hold status bit 259" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[258] ,IRQ (IRQ1 of Output Compare 2) hold status bit 258" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[257] ,IRQ (IRQ1 of Output Compare 1) hold status bit 257" "Not applied,Applied" textline " " bitfld.long 0x00 00. " IRQHS[256] ,IRQ (IRQ1 of Output Compare 0) hold status bit 256" "Not applied,Applied" else bitfld.long 0x00 31. " IRQHS[287] ,IRQ (DMAC Completion ch.10) hold status bit 287" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[286] ,IRQ (DMAC Completion ch.9) hold status bit 286" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[285] ,IRQ (DMAC Completion ch.8) hold status bit 285" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) hold status bit 282" "Not applied,Applied" textline " " bitfld.long 0x00 24. " IRQHS[280] ,IRQ (DMAC Completion ch.7) hold status bit 280" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[279] ,IRQ (DMAC Completion ch.6) hold status bit 279" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[278] ,IRQ (DMAC Completion ch.5) hold status bit 278" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[277] ,IRQ (DMAC Completion ch.4) hold status bit 277" "Not applied,Applied" textline " " bitfld.long 0x00 20. " IRQHS[276] ,IRQ (DMAC Completion ch.3) hold status bit 276" "Not applied,Applied" bitfld.long 0x00 19. " IRQHS[275] ,IRQ (DMAC Completion ch.2) hold status bit 275" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[274] ,IRQ (DMAC Completion ch.1) hold status bit 274" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[273] ,IRQ (DMAC Completion ch.0) hold status bit 273" "Not applied,Applied" textline " " bitfld.long 0x00 16. " IRQHS[272] ,IRQ (DMA Error) hold status bit 272" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[266] ,IRQ (IRQ1 of Output Compare 10) hold status bit 266" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[265] ,IRQ (IRQ1 of Output Compare 9) hold status bit 265" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[264] ,IRQ (IRQ1 of Output Compare 8) hold status bit 264" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[258] ,IRQ (IRQ1 of Output Compare 2) hold status bit 258" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[257] ,IRQ (IRQ1 of Output Compare 1) hold status bit 257" "Not applied,Applied" textline " " bitfld.long 0x00 00. " IRQHS[256] ,IRQ (IRQ1 of Output Compare 0) hold status bit 256" "Not applied,Applied" endif rgroup.long 0xC74++0x3 line.long 0x00 "IRQHS9,IRC IRQ Hold Status Register 9" bitfld.long 0x00 24. " IRQHS[312] ,IRQ (CR5 Performance Monitor Unit IRQ) hold status bit 312" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[311] ,IRQ (SCT Sub OSC IRQ) hold status bit 311" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[310] ,IRQ (SCT Main OSC IRQ) hold status bit 310" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[309] ,IRQ (SCT SRC IRQ) hold status bit 309" "Not applied,Applied" textline " " bitfld.long 0x00 20. " IRQHS[308] ,IRQ (SCT CR IRQ) hold status bit 308" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[292] ,IRQ (DMAC Completion ch.15) hold status bit 292" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[291] ,IRQ (DMAC Completion ch.14) hold status bit 291" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[290] ,IRQ (DMAC Completion ch.13) hold status bit 290" "Not applied,Applied" textline " " bitfld.long 0x00 01. " IRQHS[289] ,IRQ (DMAC Completion ch.12) hold status bit 289" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[288] ,IRQ (DMAC Completion ch.11) hold status bit 288" "Not applied,Applied" rgroup.long 0xC78++0x3 line.long 0x00 "IRQHS10,IRC IRQ Hold Status Register 10" sif (!cpuis("S6J33*")) bitfld.long 0x00 30. " IRQHS[350] ,IRQ (SG ch.3) hold status bit 350" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[349] ,IRQ (SG ch.2) hold status bit 349" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[348] ,IRQ (SG ch.1) hold status bit 348" "Not applied,Applied" bitfld.long 0x00 27. " IRQHS[347] ,IRQ (SG ch.0) hold status bit 347" "Not applied,Applied" textline " " bitfld.long 0x00 24. " IRQHS[344] ,IRQ (SMC ch.5) hold status bit 344" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[343] ,IRQ (SMC ch.4) hold status bit 343" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[342] ,IRQ (SMC ch.3) hold status bit 342" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[341] ,IRQ (SMC ch.2) hold status bit 341" "Not applied,Applied" textline " " bitfld.long 0x00 20. " IRQHS[340] ,IRQ (SMC ch.1) hold status bit 340" "Not applied,Applied" bitfld.long 0x00 19. " IRQHS[339] ,IRQ (SMC ch.0) hold status bit 339" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[337] ,IRQ (MFS ch.17 Error) hold status bit 337" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[336] ,IRQ (MFS ch.16 Error) hold status bit 336" "Not applied,Applied" textline " " bitfld.long 0x00 12. " IRQHS[332] ,IRQ (MFS ch.12 Error) hold status bit 332" "Not applied,Applied" bitfld.long 0x00 11. " IRQHS[331] ,IRQ (MFS ch.11 Error) hold status bit 331" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[330] ,IRQ (MFS ch.10 Error) hold status bit 330" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[329] ,IRQ (MFS ch.9 Error) hold status bit 329" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[328] ,IRQ (MFS ch.8 Error) hold status bit 328" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[324] ,IRQ (MFS ch.4 Error) hold status bit 324" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[323] ,IRQ (MFS ch.3 Error) hold status bit 323" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[322] ,IRQ (MFS ch.2 Error) hold status bit 322" "Not applied,Applied" textline " " bitfld.long 0x00 01. " IRQHS[321] ,IRQ (MFS ch.1 Error) hold status bit 321" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[320] ,IRQ (MFS ch.0 Error) hold status bit 320" "Not applied,Applied" else sif (!cpuis("S6J335*")) bitfld.long 0x00 31. " IRQHS[351] ,IRQ (SG ch.4) hold status bit 350" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[350] ,IRQ (SG ch.3) hold status bit 350" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[349] ,IRQ (SG ch.2) hold status bit 349" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[348] ,IRQ (SG ch.1) hold status bit 348" "Not applied,Applied" textline " " bitfld.long 0x00 27. " IRQHS[347] ,IRQ (SG ch.0) hold status bit 347" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[337] ,IRQ (MFS ch.17 Error) hold status bit 337" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[336] ,IRQ (MFS ch.16 Error) hold status bit 336" "Not applied,Applied" bitfld.long 0x00 12. " IRQHS[332] ,IRQ (MFS ch.12 Error) hold status bit 332" "Not applied,Applied" textline " " bitfld.long 0x00 11. " IRQHS[331] ,IRQ (MFS ch.11 Error) hold status bit 331" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[330] ,IRQ (MFS ch.10 Error) hold status bit 330" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[329] ,IRQ (MFS ch.9 Error) hold status bit 329" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[328] ,IRQ (MFS ch.8 Error) hold status bit 328" "Not applied,Applied" textline " " bitfld.long 0x00 04. " IRQHS[324] ,IRQ (MFS ch.4 Error) hold status bit 324" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[323] ,IRQ (MFS ch.3 Error) hold status bit 323" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[322] ,IRQ (MFS ch.2 Error) hold status bit 322" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[321] ,IRQ (MFS ch.1 Error) hold status bit 321" "Not applied,Applied" textline " " bitfld.long 0x00 00. " IRQHS[320] ,IRQ (MFS ch.0 Error) hold status bit 320" "Not applied,Applied" else bitfld.long 0x00 17. " IRQHS[337] ,IRQ (MFS ch.17 Error) hold status bit 337" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[336] ,IRQ (MFS ch.16 Error) hold status bit 336" "Not applied,Applied" bitfld.long 0x00 12. " IRQHS[332] ,IRQ (MFS ch.12 Error) hold status bit 332" "Not applied,Applied" bitfld.long 0x00 11. " IRQHS[331] ,IRQ (MFS ch.11 Error) hold status bit 331" "Not applied,Applied" textline " " bitfld.long 0x00 10. " IRQHS[330] ,IRQ (MFS ch.10 Error) hold status bit 330" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[329] ,IRQ (MFS ch.9 Error) hold status bit 329" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[328] ,IRQ (MFS ch.8 Error) hold status bit 328" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[324] ,IRQ (MFS ch.4 Error) hold status bit 324" "Not applied,Applied" textline " " bitfld.long 0x00 03. " IRQHS[323] ,IRQ (MFS ch.3 Error) hold status bit 323" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[322] ,IRQ (MFS ch.2 Error) hold status bit 322" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[321] ,IRQ (MFS ch.1 Error) hold status bit 321" "Not applied,Applied" bitfld.long 0x00 00. " IRQHS[320] ,IRQ (MFS ch.0 Error) hold status bit 320" "Not applied,Applied" endif endif rgroup.long 0xC7C++0x3 line.long 0x00 "IRQHS11,IRC IRQ Hold Status Register 11" sif (!cpuis("S6J334*")) sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) bitfld.long 0x00 26. " IRQHS[378] ,IRQ (I2S1_IRQ) hold status bit 378" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[377] ,IRQ (I2S0_IRQ) hold status bit 377" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[376] ,IRQ (AUDIO_DAC_DMAE_IRQ) hold status bit 376" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[375] ,IRQ (AUDIO_DAC_UDRN_IRQ) hold status bit 375" "Not applied,Applied" textline " " bitfld.long 0x00 22. " IRQHS[374] ,IRQ (AUDIO_DAC_OVFL_IRQ) hold status bit 374" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[373] ,IRQ (AUDIO_DAC_DREQ) hold status bit 373" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[372] ,IRQ (PCMPWM_DMAE) hold status bit 372" "Not applied,Applied" bitfld.long 0x00 19. " IRQHS[371] ,IRQ (PCMPWM_UDRN) hold status bit 371" "Not applied,Applied" textline " " bitfld.long 0x00 18. " IRQHS[370] ,IRQ (PCMPWM_OVFL) hold status bit 370" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[369] ,IRQ (PCMPWM_DREQ) hold status bit 369" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[368] ,IRQ (Indicator PWM) hold status bit 368" "Not applied,Applied" bitfld.long 0x00 12. " IRQHS[364] ,IRQ (ETHERNET Q3 IRQ) hold status bit 364" "Not applied,Applied" textline " " bitfld.long 0x00 11. " IRQHS[363] ,IRQ (ETHERNET Q2 IRQ) hold status bit 363" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[362] ,IRQ (ETHERNET Q1 IRQ) hold status bit 362" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[361] ,IRQ (ETHERNET IRQ) hold status bit 361" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[360] ,IRQ (MLB system interrupt) hold status bit 360" "Not applied,Applied" textline " " bitfld.long 0x00 07. " IRQHS[359] ,IRQ (MLB channel interrupt) hold status bit 359" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[357] ,IRQ (RPGCRC) hold status bit 357" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[356] ,IRQ (ADC12B RCO) hold status bit 356" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[355] ,IRQ (ADC12B pulse detection function) hold status bit 355" "Not applied,Applied" textline " " bitfld.long 0x00 02. " IRQHS[354] ,IRQ (ADC12B Group interrupt) hold status bit 354" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[353] ,IRQ (ADC12B Conversion Done) hold status bit 353" "Not applied,Applied" else bitfld.long 0x00 26. " IRQHS[378] ,IRQ (I2S1_IRQ) hold status bit 378" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[377] ,IRQ (I2S0_IRQ) hold status bit 377" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[368] ,IRQ (Indicator PWM) hold status bit 368" "Not applied,Applied" bitfld.long 0x00 12. " IRQHS[364] ,IRQ (ETHERNET Q3 IRQ) hold status bit 364" "Not applied,Applied" textline " " bitfld.long 0x00 11. " IRQHS[363] ,IRQ (ETHERNET Q2 IRQ) hold status bit 363" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[362] ,IRQ (ETHERNET Q1 IRQ) hold status bit 362" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[361] ,IRQ (ETHERNET IRQ) hold status bit 361" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[360] ,IRQ (MLB system interrupt) hold status bit 360" "Not applied,Applied" textline " " bitfld.long 0x00 07. " IRQHS[359] ,IRQ (MLB channel interrupt) hold status bit 359" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[357] ,IRQ (RPGCRC) hold status bit 357" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[356] ,IRQ (ADC12B RCO) hold status bit 356" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[355] ,IRQ (ADC12B pulse detection function) hold status bit 355" "Not applied,Applied" textline " " bitfld.long 0x00 02. " IRQHS[354] ,IRQ (ADC12B Group interrupt) hold status bit 354" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[353] ,IRQ (ADC12B Conversion Done) hold status bit 353" "Not applied,Applied" endif else bitfld.long 0x00 16. " IRQHS[368] ,IRQ (Indicator PWM) hold status bit 368" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[357] ,IRQ (RPGCRC) hold status bit 357" "Not applied,Applied" bitfld.long 0x00 04. " IRQHS[356] ,IRQ (ADC12B RCO) hold status bit 356" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[355] ,IRQ (ADC12B pulse detection function) hold status bit 355" "Not applied,Applied" textline " " bitfld.long 0x00 02. " IRQHS[354] ,IRQ (ADC12B Group interrupt) hold status bit 354" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[353] ,IRQ (ADC12B Conversion Done) hold status bit 353" "Not applied,Applied" endif rgroup.long 0xC80++0x3 line.long 0x00 "IRQHS12,IRC IRQ Hold Status Register 12" sif (cpuis("S6J33*")) bitfld.long 0x00 25. " IRQHS[409] ,IRQ (2D Graphics Core Display0 Sync1) hold status bit 409" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[408] ,IRQ (2D Graphics Core Display0 Sync0) hold status bit 408" "Not applied,Applied" bitfld.long 0x00 23. " IRQHS[407] ,IRQ (2D Graphics Core Signature0) hold status bit 407" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[406] ,IRQ (2D Graphics Core Display Stream0) hold status bit 406" "Not applied,Applied" textline " " bitfld.long 0x00 21. " IRQHS[405] ,IRQ (2D Graphics Core Safety Stream0) hold status bit 405" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[404] ,IRQ (2D Graphics Core Content Stream0) hold status bit 404" "Not applied,Applied" bitfld.long 0x00 19. " IRQHS[403] ,IRQ (2D Graphics Core Drawing Engine) hold status bit 403" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[402] ,IRQ (2D Graphics Core Blit Engine) hold status bit 402" "Not applied,Applied" textline " " bitfld.long 0x00 17. " IRQHS[401] ,IRQ (2D Graphics Core Command Sequencer) hold status bit 401" "Not applied,Applied" bitfld.long 0x00 11. " IRQHS[395] ,IRQ (Base Timer ch.31) hold status bit 395" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[394] ,IRQ (Base Timer ch.30) hold status bit 394" "Not applied,Applied" bitfld.long 0x00 9. " IRQHS[393] ,IRQ (Base Timer ch.29) hold status bit 393" "Not applied,Applied" textline " " bitfld.long 0x00 8. " IRQHS[392] ,IRQ (Base Timer ch.28) hold status bit 392" "Not applied,Applied" bitfld.long 0x00 7. " IRQHS[391] ,IRQ (Base Timer ch.27) hold status bit 391" "Not applied,Applied" bitfld.long 0x00 6. " IRQHS[390] ,IRQ (Base Timer ch.26) hold status bit 390" "Not applied,Applied" bitfld.long 0x00 5. " IRQHS[389] ,IRQ (Base Timer ch.25) hold status bit 389" "Not applied,Applied" textline " " sif (cpuis("S6J335*")) bitfld.long 0x00 4. " IRQHS[388] ,IRQ (Base Timer ch.24/32/33/34/35) hold status bit 401" "Not applied,Applied" else bitfld.long 0x00 4. " IRQHS[388] ,IRQ (Base Timer ch.24) hold status bit 401" "Not applied,Applied" endif else bitfld.long 0x00 31. " IRQHS[415] ,IRQ (2D Graphics Core Display1 Sync1) hold status bit 415" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[414] ,IRQ (2D Graphics Core Display1 Sync0) hold status bit 414" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[413] ,IRQ (2D Graphics Core Signature1) hold status bit 413" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[412] ,IRQ (2D Graphics Core Display Stream1) hold status bit 412" "Not applied,Applied" textline " " bitfld.long 0x00 27. " IRQHS[411] ,IRQ (2D Graphics Core Safety Stream1) hold status bit 411" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[410] ,IRQ (2D Graphics Core Content Stream1) hold status bit 410" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[409] ,IRQ (2D Graphics Core Display0 Sync1) hold status bit 409" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[408] ,IRQ (2D Graphics Core Display0 Sync0) hold status bit 408" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[407] ,IRQ (2D Graphics Core Signature0) hold status bit 407" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[406] ,IRQ (2D Graphics Core Display Stream0) hold status bit 406" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[405] ,IRQ (2D Graphics Core Safety Stream0) hold status bit 405" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[404] ,IRQ (2D Graphics Core Content Stream0) hold status bit 404" "Not applied,Applied" textline " " bitfld.long 0x00 19. " IRQHS[403] ,IRQ (2D Graphics Core Drawing Engine) hold status bit 403" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[402] ,IRQ (2D Graphics Core Blit Engine) hold status bit 402" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[401] ,IRQ (2D Graphics Core Command Sequencer) hold status bit 401" "Not applied,Applied" endif rgroup.long 0xC84++0x3 line.long 0x00 "IRQHS13,IRC IRQ Hold Status Register 13" sif (cpuis("S6J33*")) sif (!cpuis("S6J335*")) bitfld.long 0x00 31. " IRQHS[447] ,IRQ (MX_OVFL_IRQ4) hold status bit 447" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[446] ,IRQ (MX_OVFL_IRQ3) hold status bit 446" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[445] ,IRQ (MX_OVFL_IRQ2) hold status bit 445" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[444] ,IRQ (MX_OVFL_IRQ1) hold status bit 444" "Not applied,Applied" textline " " bitfld.long 0x00 27. " IRQHS[443] ,IRQ (MX_OVFL_IRQ0) hold status bit 443" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[442] ,IRQ (MX_DATA_REQ_IRQ4) hold status bit 442" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[441] ,IRQ (MX_DATA_REQ_IRQ3) hold status bit 441" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[440] ,IRQ (MX_DATA_REQ_IRQ2) hold status bit 440" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[439] ,IRQ (MX_DATA_REQ_IRQ1) hold status bit 439" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[438] ,IRQ (MX_DATA_REQ_IRQ0) hold status bit 438" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[437] ,IRQ (WG_AHB_ERR_IRQ) hold status bit 437" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[436] ,IRQ (WG_END_IRQ4) hold status bit 436" "Not applied,Applied" textline " " bitfld.long 0x00 19. " IRQHS[435] ,IRQ (WG_END_IRQ3) hold status bit 435" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[434] ,IRQ (WG_END_IRQ2) hold status bit 434" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[433] ,IRQ (WG_END_IRQ1) hold status bit 433" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[432] ,IRQ (WG_END_IRQ0) hold status bit 432" "Not applied,Applied" textline " " endif bitfld.long 0x00 07. " IRQHS[423] ,IRQ (2D Graphics Core LCDBusIf_Control) hold status bit 423" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[422] ,IRQ (2D Graphics Core LCDBusIf_InstrFifo) hold status bit 422" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[421] ,IRQ (2D Graphics Core LCDBusIf_Control) hold status bit 421" "Not applied,Applied" else bitfld.long 0x00 31. " IRQHS[447] ,IRQ (MX_OVFL_IRQ4) hold status bit 447" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[446] ,IRQ (MX_OVFL_IRQ3) hold status bit 446" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[445] ,IRQ (MX_OVFL_IRQ2) hold status bit 445" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[444] ,IRQ (MX_OVFL_IRQ1) hold status bit 444" "Not applied,Applied" textline " " bitfld.long 0x00 27. " IRQHS[443] ,IRQ (MX_OVFL_IRQ0) hold status bit 443" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[442] ,IRQ (MX_DATA_REQ_IRQ4) hold status bit 442" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[441] ,IRQ (MX_DATA_REQ_IRQ3) hold status bit 441" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[440] ,IRQ (MX_DATA_REQ_IRQ2) hold status bit 440" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[439] ,IRQ (MX_DATA_REQ_IRQ1) hold status bit 439" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[438] ,IRQ (MX_DATA_REQ_IRQ0) hold status bit 438" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[437] ,IRQ (WG_AHB_ERR_IRQ) hold status bit 437" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[436] ,IRQ (WG_END_IRQ4) hold status bit 436" "Not applied,Applied" textline " " bitfld.long 0x00 19. " IRQHS[435] ,IRQ (WG_END_IRQ3) hold status bit 435" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[434] ,IRQ (WG_END_IRQ2) hold status bit 434" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[433] ,IRQ (WG_END_IRQ1) hold status bit 433" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[432] ,IRQ (WG_END_IRQ0) hold status bit 432" "Not applied,Applied" textline " " bitfld.long 0x00 12. " IRQHS[428] ,IRQ (3D Graphics Core SBEI) hold status bit 428" "Not applied,Applied" bitfld.long 0x00 11. " IRQHS[427] ,IRQ (3D Graphics Core BEI) hold status bit 427" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[426] ,IRQ (3D Graphics Core CAEI) hold status bit 426" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[425] ,IRQ (3D Graphics Core DEI) hold status bit 425" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[424] ,IRQ (3D Graphics Core DLEI) hold status bit 424" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[423] ,IRQ (3D Graphics Core DFI) hold status bit 423" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[422] ,IRQ (3D Graphics Core LINI) hold status bit 422" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[421] ,IRQ (3D Graphics Core SRUI) hold status bit 421" "Not applied,Applied" textline " " bitfld.long 0x00 04. " IRQHS[420] ,IRQ (2D Graphics Core DDRHSSPI) hold status bit 420" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[419] ,IRQ (2D Graphics Core Histogram) hold status bit 419" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[418] ,IRQ (2D Graphics Core Storage Stream0) hold status bit 418" "Not applied,Applied" bitfld.long 0x00 01. " IRQHS[417] ,IRQ (2D Graphics Core Display Plane0) hold status bit 417" "Not applied,Applied" textline " " bitfld.long 0x00 00. " IRQHS[416] ,IRQ (2D Graphics Core Capture Plane0) hold status bit 416" "Not applied,Applied" endif rgroup.long 0xC88++0x3 line.long 0x00 "IRQHS14,IRC IRQ Hold Status Register 14" sif (cpuis("S6J33*")) sif (cpuis("S6J331*")) bitfld.long 0x00 13. " IRQHS[461] ,IRQ (ARH IRQ2) hold status bit 461" "Not applied,Applied" bitfld.long 0x00 12. " IRQHS[460] ,IRQ (ARH IRQ1) hold status bit 460" "Not applied,Applied" bitfld.long 0x00 10. " IRQHS[458] ,IRQ (MX_AHB_ERR_IRQ) hold status bit 458" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[457] ,IRQ (MX_DMA_ERR_IRQ4) hold status bit 457" "Not applied,Applied" textline " " bitfld.long 0x00 08. " IRQHS[456] ,IRQ (MX_DMA_ERR_IRQ3) hold status bit 456" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[455] ,IRQ (MX_DMA_ERR_IRQ2) hold status bit 455" "Not applied,Applied" bitfld.long 0x00 06. " IRQHS[454] ,IRQ (MX_DMA_ERR_IRQ1) hold status bit 454" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[453] ,IRQ (MX_DMA_ERR_IRQ0) hold status bit 453" "Not applied,Applied" elif (cpuis("S6J333*")) bitfld.long 0x00 19. " IRQHS[467] ,IRQ (ADC12B1 RCO) hold status bit 467" "Not applied,Applied" bitfld.long 0x00 18. " IRQHS[466] ,IRQ (ADC12B1 pulse detection function) hold status bit 466" "Not applied,Applied" bitfld.long 0x00 17. " IRQHS[465] ,IRQ (ADC12B1 Group interrupt) hold status bit 465" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[464] ,IRQ (ADC12B1 Conversion Done) hold status bit 464" "Not applied,Applied" textline " " bitfld.long 0x00 10. " IRQHS[458] ,IRQ (MX_AHB_ERR_IRQ) hold status bit 458" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[457] ,IRQ (MX_DMA_ERR_IRQ4) hold status bit 457" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[456] ,IRQ (MX_DMA_ERR_IRQ3) hold status bit 456" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[455] ,IRQ (MX_DMA_ERR_IRQ2) hold status bit 455" "Not applied,Applied" textline " " bitfld.long 0x00 06. " IRQHS[454] ,IRQ (MX_DMA_ERR_IRQ1) hold status bit 454" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[453] ,IRQ (MX_DMA_ERR_IRQ0) hold status bit 453" "Not applied,Applied" elif (cpuis("S6J335*")) bitfld.long 0x00 31. " IRQHS[479] ,IRQ (Base Timer ch.51) hold status bit 479" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[478] ,IRQ (Base Timer ch.50) hold status bit 478" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[477] ,IRQ (Base Timer ch.49) hold status bit 477" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[476] ,IRQ (Base Timer ch.48/56/57/58/59) hold status bit 476" "Not applied,Applied" textline " " bitfld.long 0x00 27. " IRQHS[475] ,IRQ (Base Timer ch.43) hold status bit 475" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[474] ,IRQ (Base Timer ch.42) hold status bit 474" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[473] ,IRQ (Base Timer ch.41) hold status bit 473" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[472] ,IRQ (Base Timer ch.40) hold status bit 472" "Not applied,Applied" textline " " bitfld.long 0x00 23. " IRQHS[471] ,IRQ (Base Timer ch.39) hold status bit 471" "Not applied,Applied" bitfld.long 0x00 22. " IRQHS[470] ,IRQ (Base Timer ch.38) hold status bit 470" "Not applied,Applied" bitfld.long 0x00 21. " IRQHS[469] ,IRQ (Base Timer ch.37) hold status bit 469" "Not applied,Applied" bitfld.long 0x00 20. " IRQHS[468] ,IRQ (Base Timer ch.36/44/45/46/47) hold status bit 468" "Not applied,Applied" else bitfld.long 0x00 10. " IRQHS[458] ,IRQ (MX_AHB_ERR_IRQ) hold status bit 458" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[457] ,IRQ (MX_DMA_ERR_IRQ4) hold status bit 457" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[456] ,IRQ (MX_DMA_ERR_IRQ3) hold status bit 456" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[455] ,IRQ (MX_DMA_ERR_IRQ2) hold status bit 455" "Not applied,Applied" textline " " bitfld.long 0x00 06. " IRQHS[454] ,IRQ (MX_DMA_ERR_IRQ1) hold status bit 454" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[453] ,IRQ (MX_DMA_ERR_IRQ0) hold status bit 453" "Not applied,Applied" endif else bitfld.long 0x00 10. " IRQHS[458] ,IRQ (MX_AHB_ERR_IRQ) hold status bit 458" "Not applied,Applied" bitfld.long 0x00 09. " IRQHS[457] ,IRQ (MX_DMA_ERR_IRQ4) hold status bit 457" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[456] ,IRQ (MX_DMA_ERR_IRQ3) hold status bit 456" "Not applied,Applied" bitfld.long 0x00 07. " IRQHS[455] ,IRQ (MX_DMA_ERR_IRQ2) hold status bit 455" "Not applied,Applied" textline " " bitfld.long 0x00 06. " IRQHS[454] ,IRQ (MX_DMA_ERR_IRQ1) hold status bit 454" "Not applied,Applied" bitfld.long 0x00 05. " IRQHS[453] ,IRQ (MX_DMA_ERR_IRQ0) hold status bit 453" "Not applied,Applied" endif sif (cpuis("S6J335*")) rgroup.long 0xC8C++0x3 line.long 0x00 "IRQHS15,IRC IRQ Hold Status Register 15" bitfld.long 0x00 7. " IRQHS[487] ,IRQ (Base Timer ch.63) hold status bit 487" "Not applied,Applied" bitfld.long 0x00 6. " IRQHS[486] ,IRQ (Base Timer ch.62) hold status bit 486" "Not applied,Applied" bitfld.long 0x00 5. " IRQHS[485] ,IRQ (Base Timer ch.61) hold status bit 485" "Not applied,Applied" bitfld.long 0x00 4. " IRQHS[484] ,IRQ (Base Timer ch.60) hold status bit 484" "Not applied,Applied" textline " " bitfld.long 0x00 3. " IRQHS[483] ,IRQ (Base Timer ch.55) hold status bit 483" "Not applied,Applied" bitfld.long 0x00 2. " IRQHS[482] ,IRQ (Base Timer ch.54) hold status bit 482" "Not applied,Applied" bitfld.long 0x00 1. " IRQHS[481] ,IRQ (Base Timer ch.53) hold status bit 481" "Not applied,Applied" bitfld.long 0x00 0. " IRQHS[480] ,IRQ (Base Timer ch.52) hold status bit 480" "Not applied,Applied" endif tree.end textline " " width 9. group.long 0xC90++0x3 line.long 0x00 "IRQPLM,IRC IRQ Priority Level Mask Register" bitfld.long 0x00 0.--5. " IRQPLM ,IRQ priority level mask bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC98++0x3 line.long 0x00 "CSR,IRC Control/Status Register" rbitfld.long 0x00 16. " LST ,Interrupt controller lock status" "Unlocked,Locked" bitfld.long 0x00 0. " IRQEN ,IRQ processing block enable/disable setting bit" "Disabled,Enabled" textline " " rgroup.long 0xCA8++0x3 line.long 0x00 "NMIRS,IRC NMI RAW Status Register" sif (!cpuis("S6J335*")) sif (!cpuis("S6J334*")) bitfld.long 0x00 23. " NMIRS[23] ,RAW status bit for NMI23 (ETHERNET_MPU_NMI)" "No interrupt,Interrupt" bitfld.long 0x00 22. " NMIRS[22] ,RAW status bit for NMI22 (MLB_MPU_NMI)" "No interrupt,Interrupt" bitfld.long 0x00 21. " NMIRS[21] ,RAW status bit for NMI21 (2D Graphics Core_NMI[1])" "No interrupt,Interrupt" bitfld.long 0x00 20. " NMIRS[20] ,RAW status bit for NMI20 (2D Graphics Core_NMI[0])" "No interrupt,Interrupt" else bitfld.long 0x00 21. " NMIRS[21] ,RAW status bit for NMI21 (2D Graphics Core_NMI[1])" "No interrupt,Interrupt" bitfld.long 0x00 20. " NMIRS[20] ,RAW status bit for NMI20 (2D Graphics Core_NMI[0])" "No interrupt,Interrupt" endif textline " " endif bitfld.long 0x00 18. " NMIRS[18] ,RAW status bit for NMI18 (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x00 15. " NMIRS[15] ,RAW status bit for NMI15 (SHE MPU)" "No interrupt,Interrupt" textline " " sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 14. " NMIRS[14] ,RAW status bit for NMI14 (DMAC MPU #1 protection violation)" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 13. " NMIRS[13] ,RAW status bit for NMI13 (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " NMIRS[12] ,RAW status bit for NMI12 (M-CAN RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 11. " NMIRS[11] ,RAW status bit for NMI11 (Backup RAM 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 08. " NMIRS[08] ,RAW status bit for NMI8 (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x00 07. " NMIRS[07] ,RAW status bit for NMI7 (SW-WDT)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " NMIRS[06] ,RAW status bit for NMI6 (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x00 05. " NMIRS[05] ,RAW status bit for NMI5 (CSV, Profile)" "No interrupt,Interrupt" bitfld.long 0x00 04. " NMIRS[04] ,RAW status bit for NMI4 (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x00 00. " NMIRS[00] ,RAW status bit for NMI0 (NMIX pin(Ext-IRC))" "No interrupt,Interrupt" rgroup.long 0xCAC++0x3 line.long 0x00 "NMIPS,IRC NMI Preprocessed Status Register" sif (!cpuis("S6J335*")) sif (!cpuis("S6J334*")) bitfld.long 0x00 23. " NMIPS_[23] ,Preprocessed status bits for (ETHERNET_MPU_NMI)" "No interrupt,Interrupt" bitfld.long 0x00 22. " NMIPS[22] ,Preprocessed status bits for (MLB_MPU_NMI)" "No interrupt,Interrupt" bitfld.long 0x00 21. " NMIPS[21] ,Preprocessed status bits for (2D Graphics Core_NMI[1])" "No interrupt,Interrupt" bitfld.long 0x00 20. " NMIPS[20] ,Preprocessed status bits for (2D Graphics Core_NMI[0])" "No interrupt,Interrupt" else bitfld.long 0x00 21. " NMIPS[21] ,Preprocessed status bits for (2D Graphics Core_NMI[1])" "No interrupt,Interrupt" bitfld.long 0x00 20. " NMIPS[20] ,Preprocessed status bits for (2D Graphics Core_NMI[0])" "No interrupt,Interrupt" endif textline " " endif bitfld.long 0x00 18. " NMIPS[18] ,Preprocessed status bits for (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x00 15. " NMIPS[15] ,Preprocessed status bits for (SHE MPU)" "No interrupt,Interrupt" textline " " sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*") bitfld.long 0x00 14. " NMIPS[14] ,Preprocessed status bits for (DMAC MPU #1 protection violation)" "No interrupt,Interrupt" endif bitfld.long 0x00 13. " NMIPS[13] ,Preprocessed status bits for (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " NMIPS[12] ,Preprocessed status bits for (M-CAN RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 11. " NMIPS[11] ,Preprocessed status bits for (Backup RAM 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 08. " NMIPS[08] ,Preprocessed status bits for (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x00 07. " NMIPS[07] ,Preprocessed status bits for (SW-WDT)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " NMIPS[06] ,Preprocessed status bits for (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x00 05. " NMIPS[05] ,Preprocessed status bits for (CSV, Profile)" "No interrupt,Interrupt" bitfld.long 0x00 04. " NMIPS[04] ,Preprocessed status bits for (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x00 00. " NMIPS[00] ,Preprocessed status bits for (NMIX pin(Ext-IRC))" "No interrupt,Interrupt" tree "IRQRS IRC IRQ RAW Status Resisters" rgroup.long 0xCB0++0x3 line.long 0x00 "IRQRS0,IRC IRQ RAW Status Register 0" bitfld.long 0x00 31. " IRQRS[31] ,IRQ (External Interrupt Request ch.7) RAW status bit 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[30] ,IRQ (External Interrupt Request ch.6) RAW status bit 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[29] ,IRQ (External Interrupt Request ch.5) RAW status bit 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[28] ,IRQ (External Interrupt Request ch.4) RAW status bit 28" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQRS[27] ,IRQ (External Interrupt Request ch.3) RAW status bit 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[26] ,IRQ (External Interrupt Request ch.2) RAW status bit 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[25] ,IRQ (External Interrupt Request ch.1) RAW status bit 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[24] ,IRQ (External Interrupt Request ch.0) RAW status bit 24" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[23] ,IRQ (EICU) RAW status bit 23" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[20] ,IRQ (Work FLASH Write Completion) RAW status bit 20" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[16] ,IRQ (IRC Vector Address RAM Single Bit Error) RAW status bit 16" "No interrupt,Interrupt" bitfld.long 0x00 15. " IRQRS[15] ,IRQ (Backup RAM / CAN FD RAM(ch.0,1,5,6) Single Bit Error) RAW status bit 15" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " IRQRS[14] ,IRQ (System RAM Single Bit Error) RAW status bit 14" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[10] ,IRQ (Work FLASH Single Bit Error) RAW status bit 10" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[8] ,IRQ (TCFLASH Single Bit Error) RAW status bit 08" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[3] ,IRQ (SW-WDT Pre-warning) RAW status bit 03" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQRS[2] ,IRQ (HW-WDT Pre-warning) RAW status bit 02" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[1] ,IRQ (System Control Status) RAW status bit 01" "No interrupt,Interrupt" rgroup.long 0xCB4++0x3 line.long 0x00 "IRQRS1,IRC IRQ RAW Status Register 1" sif (cpuis("S6J335*")) bitfld.long 0x00 28. " IRQRS[60] ,IRQ (CAN FD ch.4) RAW status bit 60" "No interrupt,Interrupt" bitfld.long 0x00 27. " IRQRS[59] ,IRQ (CAN FD ch.3) RAW status bit 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[58] ,IRQ (CAN FD ch.2) RAW status bit 58" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[57] ,IRQ (CAN FD ch.1) RAW status bit 57" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQRS[56] ,IRQ (CAN FD ch.0) RAW status bit 56" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[50] ,IRQ (CAN FD ch.7) RAW status bit 50" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[49] ,IRQ (CAN FD ch.6) RAW status bit 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[48] ,IRQ (CAN FD ch.5) RAW status bit 48" "No interrupt,Interrupt" elif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) bitfld.long 0x00 28. " IRQRS[60] ,IRQ (CAN FD ch.4) RAW status bit 60" "No interrupt,Interrupt" bitfld.long 0x00 27. " IRQRS[59] ,IRQ (CAN FD ch.3) RAW status bit 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[58] ,IRQ (CAN FD ch.2) RAW status bit 58" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[57] ,IRQ (CAN FD ch.1) RAW status bit 57" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQRS[56] ,IRQ (CAN FD ch.0) RAW status bit 56" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[48] ,IRQ (CAN FD ch.5) RAW status bit 48" "No interrupt,Interrupt" else bitfld.long 0x00 25. " IRQRS[57] ,IRQ (CAN FD ch.1) RAW status bit 57" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[56] ,IRQ (CAN FD ch.0) RAW status bit 56" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[49] ,IRQ (CAN FD ch.6) RAW status bit 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[48] ,IRQ (CAN FD ch.5) RAW status bit 48" "No interrupt,Interrupt" endif textline " " bitfld.long 0x00 14. " IRQRS[46] ,IRQ (Reload Timer ch.48,49 OR-ed) RAW status bit 46" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQRS[43] ,IRQ (MFS TX ch.17) RAW status bit 43" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[42] ,IRQ (MFS RX ch.17) RAW status bit 42" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[41] ,IRQ (MFS TX ch.16) RAW status bit 41" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[40] ,IRQ (MFS RX ch.16) RAW status bit 40" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[39] ,IRQ (External Interrupt Request ch.15) RAW status bit 39" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[38] ,IRQ (External Interrupt Request ch.14) RAW status bit 38" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[37] ,IRQ (External Interrupt Request ch.13) RAW status bit 37" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQRS[36] ,IRQ (External Interrupt Request ch.12) RAW status bit 36" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[35] ,IRQ (External Interrupt Request ch.11) RAW status bit 35" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[34] ,IRQ (External Interrupt Request ch.10) RAW status bit 34" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[33] ,IRQ (External Interrupt Request ch.9) RAW status bit 33" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQRS[32] ,IRQ (External Interrupt Request ch.8) RAW status bit 32" "No interrupt,Interrupt" rgroup.long 0xCB8++0x3 line.long 0x00 "IRQRS2,IRC IRQ RAW Status Register 2" bitfld.long 0x00 25. " IRQRS[89] ,IRQ (MFS TX ch.12) RAW status bit 89" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[88] ,IRQ (MFS RX ch.12) RAW status bit 88" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[87] ,IRQ (MFS TX ch.11) RAW status bit 87" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[86] ,IRQ (MFS RX ch.11) RAW status bit 86" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " IRQRS[85] ,IRQ (MFS TX ch.10) RAW status bit 85" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[84] ,IRQ (MFS RX ch.10) RAW status bit 84" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQRS[83] ,IRQ (MFS TX ch.9) RAW status bit 83" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[82] ,IRQ (MFS RX ch.9) RAW status bit 82" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQRS[81] ,IRQ (MFS TX ch.8) RAW status bit 81" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[80] ,IRQ (MFS RX ch.8) RAW status bit 80" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[73] ,IRQ (MFS TX ch.4) RAW status bit 73" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[72] ,IRQ (MFS RX ch.4) RAW status bit 72" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQRS[71] ,IRQ (MFS TX ch.3) RAW status bit 71" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[70] ,IRQ (MFS RX ch.3) RAW status bit 70" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[69] ,IRQ (MFS TX ch.2) RAW status bit 69" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[68] ,IRQ (MFS RX ch.2) RAW status bit 68" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQRS[67] ,IRQ (MFS TX ch.1) RAW status bit 67" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[66] ,IRQ (MFS RX ch.1) RAW status bit 66" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[65] ,IRQ (MFS TX ch.0) RAW status bit 65" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[64] ,IRQ (MFS RX ch.0) RAW status bit 64" "No interrupt,Interrupt" rgroup.long 0xCBC++0x3 line.long 0x00 "IRQRS3,IRC IRQ RAW Status Register 3" bitfld.long 0x00 21. " IRQRS[117] ,IRQ (CR CARIBRATION) RAW status bit 117" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[116] ,IRQ (RTC) RAW status bit 116" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[112] ,IRQ (BACKUP RAM) RAW status bit 112" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQRS[110] ,IRQ (TCRAM) RAW status bit 110" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQRS[103] ,IRQ (DDR HSSPI TX) RAW status bit 103" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[102] ,IRQ (DDR HSSPI RX) RAW status bit 102" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[101] ,IRQ (SHE) RAW status bit 101" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[100] ,IRQ (SHE Error) RAW status bit 100" "No interrupt,Interrupt" rgroup.long 0xCC0++0x3 line.long 0x00 "IRQRS4,IRC IRQ RAW Status Register 4" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQRS[155] ,IRQ (Reload Timer ch.3) RAW status bit 155" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[154] ,IRQ (Reload Timer ch.2) RAW status bit 154" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[153] ,IRQ (Reload Timer ch.1) RAW status bit 153" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[152] ,IRQ (Reload Timer ch.0) RAW status bit 152" "No interrupt,Interrupt" else bitfld.long 0x00 25. " IRQRS[153] ,IRQ (Reload Timer ch.1) RAW status bit 153" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[152] ,IRQ (Reload Timer ch.0) RAW status bit 152" "No interrupt,Interrupt" endif textline " " bitfld.long 0x00 15. " IRQRS[143] ,IRQ (Base Timer ch.19) RAW status bit 143" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQRS[142] ,IRQ (Base Timer ch.18) RAW status bit 142" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQRS[141] ,IRQ (Base Timer ch.17) RAW status bit 141" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQRS[140] ,IRQ (Base Timer ch.16) RAW status bit 140" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQRS[139] ,IRQ (Base Timer ch.15) RAW status bit 139" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[138] ,IRQ (Base Timer ch.14) RAW status bit 138" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[137] ,IRQ (Base Timer ch.13) RAW status bit 137" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[136] ,IRQ (Base Timer ch.12/20/21/22/23) RAW status bit 136" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQRS[135] ,IRQ (Base Timer ch.7) RAW status bit 135" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[134] ,IRQ (Base Timer ch.6) RAW status bit 134" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[133] ,IRQ (Base Timer ch.5) RAW status bit 133" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[132] ,IRQ (Base Timer ch.4) RAW status bit 132" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQRS[131] ,IRQ (Base Timer ch.3) RAW status bit 131" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[130] ,IRQ (Base Timer ch.2) RAW status bit 130" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[129] ,IRQ (Base Timer ch.1) RAW status bit 129" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[128] ,IRQ (Base Timer ch.0/8/9/10/11) RAW status bit 128" "No interrupt,Interrupt" rgroup.long 0xCC4++0x3 line.long 0x00 "IRQRS5,IRC IRQ RAW Status Register 5" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQRS[187] ,IRQ (FRT ch.11) RAW status bit 187" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[186] ,IRQ (FRT ch.10) RAW status bit 186" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[185] ,IRQ (FRT ch.9) RAW status bit 185" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[184] ,IRQ (FRT ch.8) RAW status bit 184" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[183] ,IRQ (FRT ch.7) RAW status bit 183" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[182] ,IRQ (FRT ch.6) RAW status bit 182" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[181] ,IRQ (FRT ch.5) RAW status bit 181" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[180] ,IRQ (FRT ch.4) RAW status bit 180" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQRS[186] ,IRQ (FRT ch.10) RAW status bit 186" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[185] ,IRQ (FRT ch.9) RAW status bit 185" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[184] ,IRQ (FRT ch.8) RAW status bit 184" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[180] ,IRQ (FRT ch.4) RAW status bit 180" "No interrupt,Interrupt" endif textline " " bitfld.long 0x00 19. " IRQRS[179] ,IRQ (FRT ch.3) RAW status bit 179" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[178] ,IRQ (FRT ch.2) RAW status bit 178" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[177] ,IRQ (FRT ch.1) RAW status bit 177" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[176] ,IRQ (FRT ch.0) RAW status bit 176" "No interrupt,Interrupt" textline " " sif (!cpuis("S6J33*")) bitfld.long 0x00 11. " IRQRS[171] ,IRQ (Reload Timer ch.35) RAW status bit 171" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[170] ,IRQ (Reload Timer ch.34) RAW status bit 170" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[169] ,IRQ (Reload Timer ch.33) RAW status bit 169" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[168] ,IRQ (Reload Timer ch.32) RAW status bit 168" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQRS[163] ,IRQ (Reload Timer ch.19) RAW status bit 163" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[162] ,IRQ (Reload Timer ch.18) RAW status bit 162" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[161] ,IRQ (Reload Timer ch.17) RAW status bit 161" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[160] ,IRQ (Reload Timer ch.16) RAW status bit 160" "No interrupt,Interrupt" else bitfld.long 0x00 01. " IRQRS[161] ,IRQ (Reload Timer ch.17) RAW status bit 161" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[160] ,IRQ (Reload Timer ch.16) RAW status bit 160" "No interrupt,Interrupt" endif rgroup.long 0xCC8++0x3 line.long 0x00 "IRQRS6,IRC IRQ RAW Status Register 6" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQRS[219] ,IRQ (IRQ0 of Output Compare 11) RAW status bit 219" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[218] ,IRQ (IRQ0 of Output Compare 10) RAW status bit 218" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[217] ,IRQ (IRQ0 of Output Compare 9) RAW status bit 217" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[216] ,IRQ (IRQ0 of Output Compare 8) RAW status bit 216" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[215] ,IRQ (IRQ0 of Output Compare 7) RAW status bit 215" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[214] ,IRQ (IRQ0 of Output Compare 6) RAW status bit 214" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[213] ,IRQ (IRQ0 of Output Compare 5) RAW status bit 213" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[212] ,IRQ (IRQ0 of Output Compare 4) RAW status bit 212" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQRS[211] ,IRQ (IRQ0 of Output Compare 3) RAW status bit 211" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[210] ,IRQ (IRQ0 of Output Compare 2) RAW status bit 210" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[209] ,IRQ (IRQ0 of Output Compare 1) RAW status bit 209" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[208] ,IRQ (IRQ0 of Output Compare 0) RAW status bit 208" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQRS[203] ,IRQ (IRQ0 of Input Capture 11) RAW status bit 203" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[202] ,IRQ (IRQ0 of Input Capture 10) RAW status bit 202" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[201] ,IRQ (IRQ0 of Input Capture 9) RAW status bit 201" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[200] ,IRQ (IRQ0 of Input Capture 8) RAW status bit 200" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQRS[199] ,IRQ (IRQ0 of Input Capture 7) RAW status bit 199" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[198] ,IRQ (IRQ0 of Input Capture 6) RAW status bit 198" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[197] ,IRQ (IRQ0 of Input Capture 5) RAW status bit 197" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[196] ,IRQ (IRQ0 of Input Capture 4) RAW status bit 196" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQRS[195] ,IRQ (IRQ0 of Input Capture 3) RAW status bit 195" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[194] ,IRQ (IRQ0 of Input Capture 2) RAW status bit 194" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[193] ,IRQ (IRQ0 of Input Capture 1) RAW status bit 193" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[192] ,IRQ (IRQ0 of Input Capture 0) RAW status bit 192" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQRS[218] ,IRQ (IRQ0 of Output Compare 10) RAW status bit 218" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[217] ,IRQ (IRQ0 of Output Compare 9) RAW status bit 217" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[216] ,IRQ (IRQ0 of Output Compare 8) RAW status bit 216" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[210] ,IRQ (IRQ0 of Output Compare 2) RAW status bit 210" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQRS[209] ,IRQ (IRQ0 of Output Compare 1) RAW status bit 209" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[208] ,IRQ (IRQ0 of Output Compare 0) RAW status bit 208" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[202] ,IRQ (IRQ0 of Input Capture 10) RAW status bit 202" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[201] ,IRQ (IRQ0 of Input Capture 9) RAW status bit 201" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[200] ,IRQ (IRQ0 of Input Capture 8) RAW status bit 200" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[194] ,IRQ (IRQ0 of Input Capture 2) RAW status bit 194" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[193] ,IRQ (IRQ0 of Input Capture 1) RAW status bit 193" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[192] ,IRQ (IRQ0 of Input Capture 0) RAW status bit 192" "No interrupt,Interrupt" endif rgroup.long 0xCCC++0x3 line.long 0x00 "IRQRS7,IRC IRQ RAW Status Register 7" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQRS[251] ,IRQ (IRQ1 of Input Capture 11) RAW status bit 251" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[250] ,IRQ (IRQ1 of Input Capture 10) RAW status bit 250" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[249] ,IRQ (IRQ1 of Input Capture 9) RAW status bit 249" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[248] ,IRQ (IRQ1 of Input Capture 8) RAW status bit 248" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[247] ,IRQ (IRQ1 of Input Capture 7) RAW status bit 248" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[246] ,IRQ (IRQ1 of Input Capture 6) RAW status bit 246" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[245] ,IRQ (IRQ1 of Input Capture 5) RAW status bit 245" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[244] ,IRQ (IRQ1 of Input Capture 4) RAW status bit 244" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQRS[243] ,IRQ (IRQ1 of Input Capture 3) RAW status bit 243" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[242] ,IRQ (IRQ1 of Input Capture 2) RAW status bit 242" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[241] ,IRQ (IRQ1 of Input Capture 1) RAW status bit 241" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[240] ,IRQ (IRQ1 of Input Capture 0) RAW status bit 240" "No interrupt,Interrupt" textline " " bitfld.long 0x00 09. " IRQRS[233] ,IRQ (QPRC ch.9) RAW status bit 233" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[232] ,IRQ (QPRC ch.8) RAW status bit 232" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQRS[250] ,IRQ (IRQ1 of Input Capture 10) RAW status bit 250" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[249] ,IRQ (IRQ1 of Input Capture 9) RAW status bit 249" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[248] ,IRQ (IRQ1 of Input Capture 8) RAW status bit 248" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[242] ,IRQ (IRQ1 of Input Capture 2) RAW status bit 242" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQRS[241] ,IRQ (IRQ1 of Input Capture 1) RAW status bit 241" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[240] ,IRQ (IRQ1 of Input Capture 0) RAW status bit 240" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[233] ,IRQ (QPRC ch.9) RAW status bit 233" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[232] ,IRQ (QPRC ch.8) RAW status bit 232" "No interrupt,Interrupt" endif rgroup.long 0xCD0++0x3 line.long 0x00 "IRQRS8,IRC IRQ RAW Status Register 8" sif (!cpuis("S6J33*")) bitfld.long 0x00 31. " IRQRS[287] ,IRQ (DMAC Completion ch.10) RAW status bit 287" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[286] ,IRQ (DMAC Completion ch.9) RAW status bit 286" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[285] ,IRQ (DMAC Completion ch.8) RAW status bit 285" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) RAW status bit 282" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQRS[280] ,IRQ (DMAC Completion ch.7) RAW status bit 280" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[279] ,IRQ (DMAC Completion ch.6) RAW status bit 279" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[278] ,IRQ (DMAC Completion ch.5) RAW status bit 278" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[277] ,IRQ (DMAC Completion ch.4) RAW status bit 277" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQRS[276] ,IRQ (DMAC Completion ch.3) RAW status bit 276" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQRS[275] ,IRQ (DMAC Completion ch.2) RAW status bit 275" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[274] ,IRQ (DMAC Completion ch.1) RAW status bit 274" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[273] ,IRQ (DMAC Completion ch.0) RAW status bit 273" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " IRQRS[272] ,IRQ (DMA Error) RAW status bit 272" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQRS[267] ,IRQ (IRQ1 of Output Compare 11) RAW status bit 267" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[266] ,IRQ (IRQ1 of Output Compare 10) RAW status bit 266" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[265] ,IRQ (IRQ1 of Output Compare 9) RAW status bit 265" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[264] ,IRQ (IRQ1 of Output Compare 8) RAW status bit 264" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[263] ,IRQ (IRQ1 of Output Compare 7) RAW status bit 263" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[262] ,IRQ (IRQ1 of Output Compare 6) RAW status bit 262" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[261] ,IRQ (IRQ1 of Output Compare 5) RAW status bit 261" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQRS[260] ,IRQ (IRQ1 of Output Compare 4) RAW status bit 260" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[259] ,IRQ (IRQ1 of Output Compare 3) RAW status bit 259" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[258] ,IRQ (IRQ1 of Output Compare 2) RAW status bit 258" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[257] ,IRQ (IRQ1 of Output Compare 1) RAW status bit 257" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQRS[256] ,IRQ (IRQ1 of Output Compare 0) RAW status bit 256" "No interrupt,Interrupt" else bitfld.long 0x00 31. " IRQRS[287] ,IRQ (DMAC Completion ch.10) RAW status bit 287" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[286] ,IRQ (DMAC Completion ch.9) RAW status bit 286" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[285] ,IRQ (DMAC Completion ch.8) RAW status bit 285" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) RAW status bit 282" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQRS[280] ,IRQ (DMAC Completion ch.7) RAW status bit 280" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[279] ,IRQ (DMAC Completion ch.6) RAW status bit 279" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[278] ,IRQ (DMAC Completion ch.5) RAW status bit 278" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[277] ,IRQ (DMAC Completion ch.4) RAW status bit 277" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQRS[276] ,IRQ (DMAC Completion ch.3) RAW status bit 276" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQRS[275] ,IRQ (DMAC Completion ch.2) RAW status bit 275" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[274] ,IRQ (DMAC Completion ch.1) RAW status bit 274" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[273] ,IRQ (DMAC Completion ch.0) RAW status bit 273" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " IRQRS[272] ,IRQ (DMA Error) RAW status bit 272" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[266] ,IRQ (IRQ1 of Output Compare 10) RAW status bit 266" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[265] ,IRQ (IRQ1 of Output Compare 9) RAW status bit 265" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[264] ,IRQ (IRQ1 of Output Compare 8) RAW status bit 264" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[258] ,IRQ (IRQ1 of Output Compare 2) RAW status bit 258" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[257] ,IRQ (IRQ1 of Output Compare 1) RAW status bit 257" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQRS[256] ,IRQ (IRQ1 of Output Compare 0) RAW status bit 256" "No interrupt,Interrupt" endif rgroup.long 0xCD4++0x3 line.long 0x00 "IRQRS9,IRC IRQ RAW Status Register 9" bitfld.long 0x00 24. " IRQRS[312] ,IRQ (CR5 Performance Monitor Unit IRQ) RAW status bit 312" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[311] ,IRQ (SCT Sub OSC IRQ) RAW status bit 311" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[310] ,IRQ (SCT Main OSC IRQ) RAW status bit 310" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[309] ,IRQ (SCT SRC IRQ) RAW status bit 309" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQRS[308] ,IRQ (SCT CR IRQ) RAW status bit 308" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[292] ,IRQ (DMAC Completion ch.15) RAW status bit 292" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[291] ,IRQ (DMAC Completion ch.14) RAW status bit 291" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[290] ,IRQ (DMAC Completion ch.13) RAW status bit 290" "No interrupt,Interrupt" textline " " bitfld.long 0x00 01. " IRQRS[289] ,IRQ (DMAC Completion ch.12) RAW status bit 289" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[288] ,IRQ (DMAC Completion ch.11) RAW status bit 288" "No interrupt,Interrupt" rgroup.long 0xCD8++0x3 line.long 0x00 "IRQRS10,IRC IRQ RAW Status Register 10" sif (!cpuis("S6J33*")) bitfld.long 0x00 30. " IRQRS[350] ,IRQ (SG ch.3) RAW status bit 350" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[349] ,IRQ (SG ch.2) RAW status bit 349" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[348] ,IRQ (SG ch.1) RAW status bit 348" "No interrupt,Interrupt" bitfld.long 0x00 27. " IRQRS[347] ,IRQ (SG ch.0) RAW status bit 347" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQRS[344] ,IRQ (SMC ch.5) RAW status bit 344" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[343] ,IRQ (SMC ch.4) RAW status bit 343" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[342] ,IRQ (SMC ch.3) RAW status bit 342" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[341] ,IRQ (SMC ch.2) RAW status bit 341" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQRS[340] ,IRQ (SMC ch.1) RAW status bit 340" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQRS[339] ,IRQ (SMC ch.0) RAW status bit 339" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[337] ,IRQ (MFS ch.17 Error) RAW status bit 337" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[336] ,IRQ (MFS ch.16 Error) RAW status bit 336" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " IRQRS[332] ,IRQ (MFS ch.12 Error) RAW status bit 332" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQRS[331] ,IRQ (MFS ch.11 Error) RAW status bit 331" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[330] ,IRQ (MFS ch.10 Error) RAW status bit 330" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[329] ,IRQ (MFS ch.9 Error) RAW status bit 329" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[328] ,IRQ (MFS ch.8 Error) RAW status bit 328" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[324] ,IRQ (MFS ch.4 Error) RAW status bit 324" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[323] ,IRQ (MFS ch.3 Error) RAW status bit 323" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[322] ,IRQ (MFS ch.2 Error) RAW status bit 322" "No interrupt,Interrupt" textline " " bitfld.long 0x00 01. " IRQRS[321] ,IRQ (MFS ch.1 Error) RAW status bit 321" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[320] ,IRQ (MFS ch.0 Error) RAW status bit 320" "No interrupt,Interrupt" else sif (!cpuis("S6J335*")) bitfld.long 0x00 31. " IRQRS[351] ,IRQ (SG ch.4) RAW status bit 350" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[350] ,IRQ (SG ch.3) RAW status bit 350" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[349] ,IRQ (SG ch.2) RAW status bit 349" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[348] ,IRQ (SG ch.1) RAW status bit 348" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQRS[347] ,IRQ (SG ch.0) RAW status bit 347" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[337] ,IRQ (MFS ch.17 Error) RAW status bit 337" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[336] ,IRQ (MFS ch.16 Error) RAW status bit 336" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQRS[332] ,IRQ (MFS ch.12 Error) RAW status bit 332" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQRS[331] ,IRQ (MFS ch.11 Error) RAW status bit 331" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[330] ,IRQ (MFS ch.10 Error) RAW status bit 330" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[329] ,IRQ (MFS ch.9 Error) RAW status bit 329" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[328] ,IRQ (MFS ch.8 Error) RAW status bit 328" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQRS[324] ,IRQ (MFS ch.4 Error) RAW status bit 324" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[323] ,IRQ (MFS ch.3 Error) RAW status bit 323" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[322] ,IRQ (MFS ch.2 Error) RAW status bit 322" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[321] ,IRQ (MFS ch.1 Error) RAW status bit 321" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQRS[320] ,IRQ (MFS ch.0 Error) RAW status bit 320" "No interrupt,Interrupt" else bitfld.long 0x00 17. " IRQRS[337] ,IRQ (MFS ch.17 Error) RAW status bit 337" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[336] ,IRQ (MFS ch.16 Error) RAW status bit 336" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQRS[332] ,IRQ (MFS ch.12 Error) RAW status bit 332" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQRS[331] ,IRQ (MFS ch.11 Error) RAW status bit 331" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " IRQRS[330] ,IRQ (MFS ch.10 Error) RAW status bit 330" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[329] ,IRQ (MFS ch.9 Error) RAW status bit 329" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[328] ,IRQ (MFS ch.8 Error) RAW status bit 328" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[324] ,IRQ (MFS ch.4 Error) RAW status bit 324" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQRS[323] ,IRQ (MFS ch.3 Error) RAW status bit 323" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[322] ,IRQ (MFS ch.2 Error) RAW status bit 322" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[321] ,IRQ (MFS ch.1 Error) RAW status bit 321" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQRS[320] ,IRQ (MFS ch.0 Error) RAW status bit 320" "No interrupt,Interrupt" endif endif rgroup.long 0xCDC++0x3 line.long 0x00 "IRQRS11,IRC IRQ RAW Status Register 11" sif (!cpuis("S6J334*")) sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) bitfld.long 0x00 26. " IRQRS[378] ,IRQ (I2S1_IRQ) RAW status bit 378" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[377] ,IRQ (I2S0_IRQ) RAW status bit 377" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[376] ,IRQ (AUDIO_DAC_DMAE_IRQ) RAW status bit 376" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[375] ,IRQ (AUDIO_DAC_UDRN_IRQ) RAW status bit 375" "No interrupt,Interrupt" textline " " bitfld.long 0x00 22. " IRQRS[374] ,IRQ (AUDIO_DAC_OVFL_IRQ) RAW status bit 374" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[373] ,IRQ (AUDIO_DAC_DREQ) RAW status bit 373" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[372] ,IRQ (PCMPWM_DMAE) RAW status bit 372" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQRS[371] ,IRQ (PCMPWM_UDRN) RAW status bit 371" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " IRQRS[370] ,IRQ (PCMPWM_OVFL) RAW status bit 370" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[369] ,IRQ (PCMPWM_DREQ) RAW status bit 369" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[368] ,IRQ (Indicator PWM) RAW status bit 368" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQRS[364] ,IRQ (ETHERNET Q3 IRQ) RAW status bit 364" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQRS[363] ,IRQ (ETHERNET Q2 IRQ) RAW status bit 363" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[362] ,IRQ (ETHERNET Q1 IRQ) RAW status bit 362" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[361] ,IRQ (ETHERNET IRQ) RAW status bit 361" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[360] ,IRQ (MLB system interrupt) RAW status bit 360" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQRS[359] ,IRQ (MLB channel interrupt) RAW status bit 359" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[357] ,IRQ (RPGCRC) RAW status bit 357" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[356] ,IRQ (ADC12B RCO) RAW status bit 356" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[355] ,IRQ (ADC12B pulse detection function) RAW status bit 355" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQRS[354] ,IRQ (ADC12B Group interrupt) RAW status bit 354" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[353] ,IRQ (ADC12B Conversion Done) RAW status bit 353" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQRS[378] ,IRQ (I2S1_IRQ) RAW status bit 378" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[377] ,IRQ (I2S0_IRQ) RAW status bit 377" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[368] ,IRQ (Indicator PWM) RAW status bit 368" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQRS[364] ,IRQ (ETHERNET Q3 IRQ) RAW status bit 364" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQRS[363] ,IRQ (ETHERNET Q2 IRQ) RAW status bit 363" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[362] ,IRQ (ETHERNET Q1 IRQ) RAW status bit 362" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[361] ,IRQ (ETHERNET IRQ) RAW status bit 361" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[360] ,IRQ (MLB system interrupt) RAW status bit 360" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQRS[359] ,IRQ (MLB channel interrupt) RAW status bit 359" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[357] ,IRQ (RPGCRC) RAW status bit 357" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[356] ,IRQ (ADC12B RCO) RAW status bit 356" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[355] ,IRQ (ADC12B pulse detection function) RAW status bit 355" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQRS[354] ,IRQ (ADC12B Group interrupt) RAW status bit 354" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[353] ,IRQ (ADC12B Conversion Done) RAW status bit 353" "No interrupt,Interrupt" endif else bitfld.long 0x00 16. " IRQRS[368] ,IRQ (Indicator PWM) RAW status bit 368" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[357] ,IRQ (RPGCRC) RAW status bit 357" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQRS[356] ,IRQ (ADC12B RCO) RAW status bit 356" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[355] ,IRQ (ADC12B pulse detection function) RAW status bit 355" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQRS[354] ,IRQ (ADC12B Group interrupt) RAW status bit 354" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[353] ,IRQ (ADC12B Conversion Done) RAW status bit 353" "No interrupt,Interrupt" endif rgroup.long 0xCE0++0x3 line.long 0x00 "IRQRS12,IRC IRQ RAW Status Register 12" sif (cpuis("S6J33*")) bitfld.long 0x00 25. " IRQRS[409] ,IRQ (2D Graphics Core Display0 Sync1) RAW status bit 409" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[408] ,IRQ (2D Graphics Core Display0 Sync0) RAW status bit 408" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQRS[407] ,IRQ (2D Graphics Core Signature0) RAW status bit 407" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[406] ,IRQ (2D Graphics Core Display Stream0) RAW status bit 406" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " IRQRS[405] ,IRQ (2D Graphics Core Safety Stream0) RAW status bit 405" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[404] ,IRQ (2D Graphics Core Content Stream0) RAW status bit 404" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQRS[403] ,IRQ (2D Graphics Core Drawing Engine) RAW status bit 403" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[402] ,IRQ (2D Graphics Core Blit Engine) RAW status bit 402" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQRS[401] ,IRQ (2D Graphics Core Command Sequencer) RAW status bit 401" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQRS[395] ,IRQ (Base Timer ch.31) RAW status bit 395" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[394] ,IRQ (Base Timer ch.30) RAW status bit 394" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQRS[393] ,IRQ (Base Timer ch.29) RAW status bit 393" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " IRQRS[392] ,IRQ (Base Timer ch.28) RAW status bit 392" "No interrupt,Interrupt" bitfld.long 0x00 7. " IRQRS[391] ,IRQ (Base Timer ch.27) RAW status bit 391" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQRS[390] ,IRQ (Base Timer ch.26) RAW status bit 390" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQRS[389] ,IRQ (Base Timer ch.25) RAW status bit 389" "No interrupt,Interrupt" textline " " sif (cpuis("S6J335*")) bitfld.long 0x00 4. " IRQRS[388] ,IRQ (Base Timer ch.24/32/33/34/35) RAW status bit 401" "No interrupt,Interrupt" else bitfld.long 0x00 4. " IRQRS[388] ,IRQ (Base Timer ch.24) RAW status bit 401" "No interrupt,Interrupt" endif else bitfld.long 0x00 31. " IRQRS[415] ,IRQ (2D Graphics Core Display1 Sync1) RAW status bit 415" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[414] ,IRQ (2D Graphics Core Display1 Sync0) RAW status bit 414" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[413] ,IRQ (2D Graphics Core Signature1) RAW status bit 413" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[412] ,IRQ (2D Graphics Core Display Stream1) RAW status bit 412" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQRS[411] ,IRQ (2D Graphics Core Safety Stream1) RAW status bit 411" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[410] ,IRQ (2D Graphics Core Content Stream1) RAW status bit 410" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[409] ,IRQ (2D Graphics Core Display0 Sync1) RAW status bit 409" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[408] ,IRQ (2D Graphics Core Display0 Sync0) RAW status bit 408" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[407] ,IRQ (2D Graphics Core Signature0) RAW status bit 407" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[406] ,IRQ (2D Graphics Core Display Stream0) RAW status bit 406" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[405] ,IRQ (2D Graphics Core Safety Stream0) RAW status bit 405" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[404] ,IRQ (2D Graphics Core Content Stream0) RAW status bit 404" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQRS[403] ,IRQ (2D Graphics Core Drawing Engine) RAW status bit 403" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[402] ,IRQ (2D Graphics Core Blit Engine) RAW status bit 402" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[401] ,IRQ (2D Graphics Core Command Sequencer) RAW status bit 401" "No interrupt,Interrupt" endif rgroup.long 0xCE4++0x3 line.long 0x00 "IRQRS13,IRC IRQ RAW Status Register 13" sif (cpuis("S6J33*")) sif (!cpuis("S6J335*")) bitfld.long 0x00 31. " IRQRS[447] ,IRQ (MX_OVFL_IRQ4) RAW status bit 447" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[446] ,IRQ (MX_OVFL_IRQ3) RAW status bit 446" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[445] ,IRQ (MX_OVFL_IRQ2) RAW status bit 445" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[444] ,IRQ (MX_OVFL_IRQ1) RAW status bit 444" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQRS[443] ,IRQ (MX_OVFL_IRQ0) RAW status bit 443" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[442] ,IRQ (MX_DATA_REQ_IRQ4) RAW status bit 442" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[441] ,IRQ (MX_DATA_REQ_IRQ3) RAW status bit 441" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[440] ,IRQ (MX_DATA_REQ_IRQ2) RAW status bit 440" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[439] ,IRQ (MX_DATA_REQ_IRQ1) RAW status bit 439" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[438] ,IRQ (MX_DATA_REQ_IRQ0) RAW status bit 438" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[437] ,IRQ (WG_AHB_ERR_IRQ) RAW status bit 437" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[436] ,IRQ (WG_END_IRQ4) RAW status bit 436" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQRS[435] ,IRQ (WG_END_IRQ3) RAW status bit 435" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[434] ,IRQ (WG_END_IRQ2) RAW status bit 434" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[433] ,IRQ (WG_END_IRQ1) RAW status bit 433" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[432] ,IRQ (WG_END_IRQ0) RAW status bit 432" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 07. " IRQRS[423] ,IRQ (2D Graphics Core LCDBusIf_Control) RAW status bit 423" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[422] ,IRQ (2D Graphics Core LCDBusIf_InstrFifo) RAW status bit 422" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[421] ,IRQ (2D Graphics Core LCDBusIf_Control) RAW status bit 421" "No interrupt,Interrupt" else bitfld.long 0x00 31. " IRQRS[447] ,IRQ (MX_OVFL_IRQ4) RAW status bit 447" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[446] ,IRQ (MX_OVFL_IRQ3) RAW status bit 446" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[445] ,IRQ (MX_OVFL_IRQ2) RAW status bit 445" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[444] ,IRQ (MX_OVFL_IRQ1) RAW status bit 444" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQRS[443] ,IRQ (MX_OVFL_IRQ0) RAW status bit 443" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[442] ,IRQ (MX_DATA_REQ_IRQ4) RAW status bit 442" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[441] ,IRQ (MX_DATA_REQ_IRQ3) RAW status bit 441" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[440] ,IRQ (MX_DATA_REQ_IRQ2) RAW status bit 440" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[439] ,IRQ (MX_DATA_REQ_IRQ1) RAW status bit 439" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[438] ,IRQ (MX_DATA_REQ_IRQ0) RAW status bit 438" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[437] ,IRQ (WG_AHB_ERR_IRQ) RAW status bit 437" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[436] ,IRQ (WG_END_IRQ4) RAW status bit 436" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQRS[435] ,IRQ (WG_END_IRQ3) RAW status bit 435" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[434] ,IRQ (WG_END_IRQ2) RAW status bit 434" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[433] ,IRQ (WG_END_IRQ1) RAW status bit 433" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[432] ,IRQ (WG_END_IRQ0) RAW status bit 432" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " IRQRS[428] ,IRQ (3D Graphics Core SBEI) RAW status bit 428" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQRS[427] ,IRQ (3D Graphics Core BEI) RAW status bit 427" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[426] ,IRQ (3D Graphics Core CAEI) RAW status bit 426" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[425] ,IRQ (3D Graphics Core DEI) RAW status bit 425" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[424] ,IRQ (3D Graphics Core DLEI) RAW status bit 424" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[423] ,IRQ (3D Graphics Core DFI) RAW status bit 423" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[422] ,IRQ (3D Graphics Core LINI) RAW status bit 422" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[421] ,IRQ (3D Graphics Core SRUI) RAW status bit 421" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQRS[420] ,IRQ (2D Graphics Core DDRHSSPI) RAW status bit 420" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[419] ,IRQ (2D Graphics Core Histogram) RAW status bit 419" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[418] ,IRQ (2D Graphics Core Storage Stream0) RAW status bit 418" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQRS[417] ,IRQ (2D Graphics Core Display Plane0) RAW status bit 417" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQRS[416] ,IRQ (2D Graphics Core Capture Plane0) RAW status bit 416" "No interrupt,Interrupt" endif rgroup.long 0xCE8++0x3 line.long 0x00 "IRQRS14,IRC IRQ RAW Status Register 14" sif (cpuis("S6J33*")) sif (cpuis("S6J331*")) bitfld.long 0x00 13. " IRQRS[461] ,IRQ (ARH IRQ2) RAW status bit 461" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQRS[460] ,IRQ (ARH IRQ1) RAW status bit 460" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQRS[458] ,IRQ (MX_AHB_ERR_IRQ) RAW status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[457] ,IRQ (MX_DMA_ERR_IRQ4) RAW status bit 457" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQRS[456] ,IRQ (MX_DMA_ERR_IRQ3) RAW status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[455] ,IRQ (MX_DMA_ERR_IRQ2) RAW status bit 455" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQRS[454] ,IRQ (MX_DMA_ERR_IRQ1) RAW status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[453] ,IRQ (MX_DMA_ERR_IRQ0) RAW status bit 453" "No interrupt,Interrupt" elif (cpuis("S6J333*")) bitfld.long 0x00 19. " IRQRS[467] ,IRQ (ADC12B1 RCO) RAW status bit 467" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQRS[466] ,IRQ (ADC12B1 pulse detection function) RAW status bit 466" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQRS[465] ,IRQ (ADC12B1 Group interrupt) RAW status bit 465" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[464] ,IRQ (ADC12B1 Conversion Done) RAW status bit 464" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " IRQRS[458] ,IRQ (MX_AHB_ERR_IRQ) RAW status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[457] ,IRQ (MX_DMA_ERR_IRQ4) RAW status bit 457" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[456] ,IRQ (MX_DMA_ERR_IRQ3) RAW status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[455] ,IRQ (MX_DMA_ERR_IRQ2) RAW status bit 455" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " IRQRS[454] ,IRQ (MX_DMA_ERR_IRQ1) RAW status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[453] ,IRQ (MX_DMA_ERR_IRQ0) RAW status bit 453" "No interrupt,Interrupt" elif (cpuis("S6J335*")) bitfld.long 0x00 31. " IRQRS[479] ,IRQ (Base Timer ch.51) RAW status bit 479" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[478] ,IRQ (Base Timer ch.50) RAW status bit 478" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[477] ,IRQ (Base Timer ch.49) RAW status bit 477" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[476] ,IRQ (Base Timer ch.48/56/57/58/59) RAW status bit 476" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQRS[475] ,IRQ (Base Timer ch.43) RAW status bit 475" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[474] ,IRQ (Base Timer ch.42) RAW status bit 474" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[473] ,IRQ (Base Timer ch.41) RAW status bit 473" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[472] ,IRQ (Base Timer ch.40) RAW status bit 472" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQRS[471] ,IRQ (Base Timer ch.39) RAW status bit 471" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQRS[470] ,IRQ (Base Timer ch.38) RAW status bit 470" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQRS[469] ,IRQ (Base Timer ch.37) RAW status bit 469" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQRS[468] ,IRQ (Base Timer ch.36/44/45/46/47) RAW status bit 468" "No interrupt,Interrupt" else bitfld.long 0x00 10. " IRQRS[458] ,IRQ (MX_AHB_ERR_IRQ) RAW status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[457] ,IRQ (MX_DMA_ERR_IRQ4) RAW status bit 457" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[456] ,IRQ (MX_DMA_ERR_IRQ3) RAW status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[455] ,IRQ (MX_DMA_ERR_IRQ2) RAW status bit 455" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " IRQRS[454] ,IRQ (MX_DMA_ERR_IRQ1) RAW status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[453] ,IRQ (MX_DMA_ERR_IRQ0) RAW status bit 453" "No interrupt,Interrupt" endif else bitfld.long 0x00 10. " IRQRS[458] ,IRQ (MX_AHB_ERR_IRQ) RAW status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQRS[457] ,IRQ (MX_DMA_ERR_IRQ4) RAW status bit 457" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[456] ,IRQ (MX_DMA_ERR_IRQ3) RAW status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQRS[455] ,IRQ (MX_DMA_ERR_IRQ2) RAW status bit 455" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " IRQRS[454] ,IRQ (MX_DMA_ERR_IRQ1) RAW status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQRS[453] ,IRQ (MX_DMA_ERR_IRQ0) RAW status bit 453" "No interrupt,Interrupt" endif sif (cpuis("S6J335*")) rgroup.long 0xCEC++0x3 line.long 0x00 "IRQRS15,IRC IRQ RAW Status Register 15" bitfld.long 0x00 7. " IRQRS[487] ,IRQ (Base Timer ch.63) RAW status bit 487" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQRS[486] ,IRQ (Base Timer ch.62) RAW status bit 486" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQRS[485] ,IRQ (Base Timer ch.61) RAW status bit 485" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQRS[484] ,IRQ (Base Timer ch.60) RAW status bit 484" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQRS[483] ,IRQ (Base Timer ch.55) RAW status bit 483" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQRS[482] ,IRQ (Base Timer ch.54) RAW status bit 482" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQRS[481] ,IRQ (Base Timer ch.53) RAW status bit 481" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQRS[480] ,IRQ (Base Timer ch.52) RAW status bit 480" "No interrupt,Interrupt" endif tree.end tree "IRQPS IRC IRQ Preprocessed Status Registers" rgroup.long 0xCF0++0x3 line.long 0x00 "IRQPS0,IRC IRQ Preprocessed Status Register 0" bitfld.long 0x00 31. " IRQPS[31] ,IRQ (External Interrupt Request ch.7) preprocessed status bit 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[30] ,IRQ (External Interrupt Request ch.6) preprocessed status bit 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[29] ,IRQ (External Interrupt Request ch.5) preprocessed status bit 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[28] ,IRQ (External Interrupt Request ch.4) preprocessed status bit 28" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQPS[27] ,IRQ (External Interrupt Request ch.3) preprocessed status bit 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[26] ,IRQ (External Interrupt Request ch.2) preprocessed status bit 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[25] ,IRQ (External Interrupt Request ch.1) preprocessed status bit 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[24] ,IRQ (External Interrupt Request ch.0) preprocessed status bit 24" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[23] ,IRQ (EICU) preprocessed status bit 23" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[20] ,IRQ (Work FLASH Write Completion) preprocessed status bit 20" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[16] ,IRQ (IRC Vector Address RAM Single Bit Error) preprocessed status bit 16" "No interrupt,Interrupt" bitfld.long 0x00 15. " IRQPS[15] ,IRQ (Backup RAM / CAN FD RAM(ch.0,1,5,6) Single Bit Error) preprocessed status bit 15" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " IRQPS[14] ,IRQ (System RAM Single Bit Error) preprocessed status bit 14" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[10] ,IRQ (Work FLASH Single Bit Error) preprocessed status bit 10" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[8] ,IRQ (TCFLASH Single Bit Error) preprocessed status bit 08" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[3] ,IRQ (SW-WDT Pre-warning) preprocessed status bit 03" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQPS[2] ,IRQ (HW-WDT Pre-warning) preprocessed status bit 02" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[1] ,IRQ (System Control Status) preprocessed status bit 01" "No interrupt,Interrupt" rgroup.long 0xCF4++0x3 line.long 0x00 "IRQPS1,IRC IRQ Preprocessed Status Register 1" sif (cpuis("S6J335*")) bitfld.long 0x00 28. " IRQPS[60] ,IRQ (CAN FD ch.4) preprocessed status bit 60" "No interrupt,Interrupt" bitfld.long 0x00 27. " IRQPS[59] ,IRQ (CAN FD ch.3) preprocessed status bit 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[58] ,IRQ (CAN FD ch.2) preprocessed status bit 58" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[57] ,IRQ (CAN FD ch.1) preprocessed status bit 57" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQPS[56] ,IRQ (CAN FD ch.0) preprocessed status bit 56" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[50] ,IRQ (CAN FD ch.7) preprocessed status bit 50" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[49] ,IRQ (CAN FD ch.6) preprocessed status bit 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[48] ,IRQ (CAN FD ch.5) preprocessed status bit 48" "No interrupt,Interrupt" elif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")) bitfld.long 0x00 28. " IRQPS[60] ,IRQ (CAN FD ch.4) preprocessed status bit 60" "No interrupt,Interrupt" bitfld.long 0x00 27. " IRQPS[59] ,IRQ (CAN FD ch.3) preprocessed status bit 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[58] ,IRQ (CAN FD ch.2) preprocessed status bit 58" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[57] ,IRQ (CAN FD ch.1) preprocessed status bit 57" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQPS[56] ,IRQ (CAN FD ch.0) preprocessed status bit 56" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[48] ,IRQ (CAN FD ch.5) preprocessed status bit 48" "No interrupt,Interrupt" else bitfld.long 0x00 25. " IRQPS[57] ,IRQ (CAN FD ch.1) preprocessed status bit 57" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[56] ,IRQ (CAN FD ch.0) preprocessed status bit 56" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[49] ,IRQ (CAN FD ch.6) preprocessed status bit 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[48] ,IRQ (CAN FD ch.5) preprocessed status bit 48" "No interrupt,Interrupt" endif textline " " bitfld.long 0x00 14. " IRQPS[46] ,IRQ (Reload Timer ch.48,49 OR-ed) preprocessed status bit 46" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQPS[43] ,IRQ (MFS TX ch.17) preprocessed status bit 43" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[42] ,IRQ (MFS RX ch.17) preprocessed status bit 42" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[41] ,IRQ (MFS TX ch.16) preprocessed status bit 41" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[40] ,IRQ (MFS RX ch.16) preprocessed status bit 40" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[39] ,IRQ (External Interrupt Request ch.15) preprocessed status bit 39" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[38] ,IRQ (External Interrupt Request ch.14) preprocessed status bit 38" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[37] ,IRQ (External Interrupt Request ch.13) preprocessed status bit 37" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQPS[36] ,IRQ (External Interrupt Request ch.12) preprocessed status bit 36" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[35] ,IRQ (External Interrupt Request ch.11) preprocessed status bit 35" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[34] ,IRQ (External Interrupt Request ch.10) preprocessed status bit 34" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[33] ,IRQ (External Interrupt Request ch.9) preprocessed status bit 33" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQPS[32] ,IRQ (External Interrupt Request ch.8) preprocessed status bit 32" "No interrupt,Interrupt" rgroup.long 0xCF8++0x3 line.long 0x00 "IRQPS2,IRC IRQ Preprocessed Status Register 2" bitfld.long 0x00 25. " IRQPS[89] ,IRQ (MFS TX ch.12) preprocessed status bit 89" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[88] ,IRQ (MFS RX ch.12) preprocessed status bit 88" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[87] ,IRQ (MFS TX ch.11) preprocessed status bit 87" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[86] ,IRQ (MFS RX ch.11) preprocessed status bit 86" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " IRQPS[85] ,IRQ (MFS TX ch.10) preprocessed status bit 85" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[84] ,IRQ (MFS RX ch.10) preprocessed status bit 84" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQPS[83] ,IRQ (MFS TX ch.9) preprocessed status bit 83" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[82] ,IRQ (MFS RX ch.9) preprocessed status bit 82" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQPS[81] ,IRQ (MFS TX ch.8) preprocessed status bit 81" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[80] ,IRQ (MFS RX ch.8) preprocessed status bit 80" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[73] ,IRQ (MFS TX ch.4) preprocessed status bit 73" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[72] ,IRQ (MFS RX ch.4) preprocessed status bit 72" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQPS[71] ,IRQ (MFS TX ch.3) preprocessed status bit 71" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[70] ,IRQ (MFS RX ch.3) preprocessed status bit 70" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[69] ,IRQ (MFS TX ch.2) preprocessed status bit 69" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[68] ,IRQ (MFS RX ch.2) preprocessed status bit 68" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQPS[67] ,IRQ (MFS TX ch.1) preprocessed status bit 67" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[66] ,IRQ (MFS RX ch.1) preprocessed status bit 66" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[65] ,IRQ (MFS TX ch.0) preprocessed status bit 65" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[64] ,IRQ (MFS RX ch.0) preprocessed status bit 64" "No interrupt,Interrupt" rgroup.long 0xCFC++0x3 line.long 0x00 "IRQPS3,IRC IRQ Preprocessed Status Register 3" bitfld.long 0x00 21. " IRQPS[117] ,IRQ (CR CARIBRATION) preprocessed status bit 117" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[116] ,IRQ (RTC) preprocessed status bit 116" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[112] ,IRQ (BACKUP RAM) preprocessed status bit 112" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQPS[110] ,IRQ (TCRAM) preprocessed status bit 110" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQPS[103] ,IRQ (DDR HSSPI TX) preprocessed status bit 103" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[102] ,IRQ (DDR HSSPI RX) preprocessed status bit 102" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[101] ,IRQ (SHE) preprocessed status bit 101" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[100] ,IRQ (SHE Error) preprocessed status bit 100" "No interrupt,Interrupt" rgroup.long 0xD00++0x3 line.long 0x00 "IRQPS4,IRC IRQ Preprocessed Status Register 4" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQPS[155] ,IRQ (Reload Timer ch.3) preprocessed status bit 155" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[154] ,IRQ (Reload Timer ch.2) preprocessed status bit 154" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[153] ,IRQ (Reload Timer ch.1) preprocessed status bit 153" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[152] ,IRQ (Reload Timer ch.0) preprocessed status bit 152" "No interrupt,Interrupt" else bitfld.long 0x00 25. " IRQPS[153] ,IRQ (Reload Timer ch.1) preprocessed status bit 153" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[152] ,IRQ (Reload Timer ch.0) preprocessed status bit 152" "No interrupt,Interrupt" endif textline " " bitfld.long 0x00 15. " IRQPS[143] ,IRQ (Base Timer ch.19) preprocessed status bit 143" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQPS[142] ,IRQ (Base Timer ch.18) preprocessed status bit 142" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQPS[141] ,IRQ (Base Timer ch.17) preprocessed status bit 141" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQPS[140] ,IRQ (Base Timer ch.16) preprocessed status bit 140" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQPS[139] ,IRQ (Base Timer ch.15) preprocessed status bit 139" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[138] ,IRQ (Base Timer ch.14) preprocessed status bit 138" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[137] ,IRQ (Base Timer ch.13) preprocessed status bit 137" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[136] ,IRQ (Base Timer ch.12/20/21/22/23) preprocessed status bit 136" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQPS[135] ,IRQ (Base Timer ch.7) preprocessed status bit 135" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[134] ,IRQ (Base Timer ch.6) preprocessed status bit 134" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[133] ,IRQ (Base Timer ch.5) preprocessed status bit 133" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[132] ,IRQ (Base Timer ch.4) preprocessed status bit 132" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQPS[131] ,IRQ (Base Timer ch.3) preprocessed status bit 131" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[130] ,IRQ (Base Timer ch.2) preprocessed status bit 130" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[129] ,IRQ (Base Timer ch.1) preprocessed status bit 129" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[128] ,IRQ (Base Timer ch.0/8/9/10/11) preprocessed status bit 128" "No interrupt,Interrupt" rgroup.long 0xD04++0x3 line.long 0x00 "IRQPS5,IRC IRQ Preprocessed Status Register 5" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQPS[187] ,IRQ (FRT ch.11) preprocessed status bit 187" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[186] ,IRQ (FRT ch.10) preprocessed status bit 186" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[185] ,IRQ (FRT ch.9) preprocessed status bit 185" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[184] ,IRQ (FRT ch.8) preprocessed status bit 184" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[183] ,IRQ (FRT ch.7) preprocessed status bit 183" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[182] ,IRQ (FRT ch.6) preprocessed status bit 182" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[181] ,IRQ (FRT ch.5) preprocessed status bit 181" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[180] ,IRQ (FRT ch.4) preprocessed status bit 180" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQPS[186] ,IRQ (FRT ch.10) preprocessed status bit 186" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[185] ,IRQ (FRT ch.9) preprocessed status bit 185" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[184] ,IRQ (FRT ch.8) preprocessed status bit 184" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[180] ,IRQ (FRT ch.4) preprocessed status bit 180" "No interrupt,Interrupt" endif textline " " bitfld.long 0x00 19. " IRQPS[179] ,IRQ (FRT ch.3) preprocessed status bit 179" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[178] ,IRQ (FRT ch.2) preprocessed status bit 178" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[177] ,IRQ (FRT ch.1) preprocessed status bit 177" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[176] ,IRQ (FRT ch.0) preprocessed status bit 176" "No interrupt,Interrupt" textline " " sif (!cpuis("S6J33*")) bitfld.long 0x00 11. " IRQPS[171] ,IRQ (Reload Timer ch.35) preprocessed status bit 171" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[170] ,IRQ (Reload Timer ch.34) preprocessed status bit 170" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[169] ,IRQ (Reload Timer ch.33) preprocessed status bit 169" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[168] ,IRQ (Reload Timer ch.32) preprocessed status bit 168" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQPS[163] ,IRQ (Reload Timer ch.19) preprocessed status bit 163" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[162] ,IRQ (Reload Timer ch.18) preprocessed status bit 162" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[161] ,IRQ (Reload Timer ch.17) preprocessed status bit 161" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[160] ,IRQ (Reload Timer ch.16) preprocessed status bit 160" "No interrupt,Interrupt" else bitfld.long 0x00 01. " IRQPS[161] ,IRQ (Reload Timer ch.17) preprocessed status bit 161" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[160] ,IRQ (Reload Timer ch.16) preprocessed status bit 160" "No interrupt,Interrupt" endif rgroup.long 0xD08++0x3 line.long 0x00 "IRQPS6,IRC IRQ Preprocessed Status Register 6" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQPS[219] ,IRQ (IRQ0 of Output Compare 11) preprocessed status bit 219" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[218] ,IRQ (IRQ0 of Output Compare 10) preprocessed status bit 218" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[217] ,IRQ (IRQ0 of Output Compare 9) preprocessed status bit 217" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[216] ,IRQ (IRQ0 of Output Compare 8) preprocessed status bit 216" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[215] ,IRQ (IRQ0 of Output Compare 7) preprocessed status bit 215" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[214] ,IRQ (IRQ0 of Output Compare 6) preprocessed status bit 214" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[213] ,IRQ (IRQ0 of Output Compare 5) preprocessed status bit 213" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[212] ,IRQ (IRQ0 of Output Compare 4) preprocessed status bit 212" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQPS[211] ,IRQ (IRQ0 of Output Compare 3) preprocessed status bit 211" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[210] ,IRQ (IRQ0 of Output Compare 2) preprocessed status bit 210" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[209] ,IRQ (IRQ0 of Output Compare 1) preprocessed status bit 209" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[208] ,IRQ (IRQ0 of Output Compare 0) preprocessed status bit 208" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQPS[203] ,IRQ (IRQ0 of Input Capture 11) preprocessed status bit 203" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[202] ,IRQ (IRQ0 of Input Capture 10) preprocessed status bit 202" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[201] ,IRQ (IRQ0 of Input Capture 9) preprocessed status bit 201" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[200] ,IRQ (IRQ0 of Input Capture 8) preprocessed status bit 200" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQPS[199] ,IRQ (IRQ0 of Input Capture 7) preprocessed status bit 199" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[198] ,IRQ (IRQ0 of Input Capture 6) preprocessed status bit 198" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[197] ,IRQ (IRQ0 of Input Capture 5) preprocessed status bit 197" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[196] ,IRQ (IRQ0 of Input Capture 4) preprocessed status bit 196" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQPS[195] ,IRQ (IRQ0 of Input Capture 3) preprocessed status bit 195" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[194] ,IRQ (IRQ0 of Input Capture 2) preprocessed status bit 194" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[193] ,IRQ (IRQ0 of Input Capture 1) preprocessed status bit 193" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[192] ,IRQ (IRQ0 of Input Capture 0) preprocessed status bit 192" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQPS[218] ,IRQ (IRQ0 of Output Compare 10) preprocessed status bit 218" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[217] ,IRQ (IRQ0 of Output Compare 9) preprocessed status bit 217" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[216] ,IRQ (IRQ0 of Output Compare 8) preprocessed status bit 216" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[210] ,IRQ (IRQ0 of Output Compare 2) preprocessed status bit 210" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQPS[209] ,IRQ (IRQ0 of Output Compare 1) preprocessed status bit 209" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[208] ,IRQ (IRQ0 of Output Compare 0) preprocessed status bit 208" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[202] ,IRQ (IRQ0 of Input Capture 10) preprocessed status bit 202" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[201] ,IRQ (IRQ0 of Input Capture 9) preprocessed status bit 201" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[200] ,IRQ (IRQ0 of Input Capture 8) preprocessed status bit 200" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[194] ,IRQ (IRQ0 of Input Capture 2) preprocessed status bit 194" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[193] ,IRQ (IRQ0 of Input Capture 1) preprocessed status bit 193" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[192] ,IRQ (IRQ0 of Input Capture 0) preprocessed status bit 192" "No interrupt,Interrupt" endif rgroup.long 0xD0C++0x3 line.long 0x00 "IRQPS7,IRC IRQ Preprocessed Status Register 7" sif (!cpuis("S6J33*")) bitfld.long 0x00 27. " IRQPS[251] ,IRQ (IRQ1 of Input Capture 11) preprocessed status bit 251" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[250] ,IRQ (IRQ1 of Input Capture 10) preprocessed status bit 250" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[249] ,IRQ (IRQ1 of Input Capture 9) preprocessed status bit 249" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[248] ,IRQ (IRQ1 of Input Capture 8) preprocessed status bit 248" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[247] ,IRQ (IRQ1 of Input Capture 7) preprocessed status bit 248" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[246] ,IRQ (IRQ1 of Input Capture 6) preprocessed status bit 246" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[245] ,IRQ (IRQ1 of Input Capture 5) preprocessed status bit 245" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[244] ,IRQ (IRQ1 of Input Capture 4) preprocessed status bit 244" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQPS[243] ,IRQ (IRQ1 of Input Capture 3) preprocessed status bit 243" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[242] ,IRQ (IRQ1 of Input Capture 2) preprocessed status bit 242" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[241] ,IRQ (IRQ1 of Input Capture 1) preprocessed status bit 241" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[240] ,IRQ (IRQ1 of Input Capture 0) preprocessed status bit 240" "No interrupt,Interrupt" textline " " bitfld.long 0x00 09. " IRQPS[233] ,IRQ (QPRC ch.9) preprocessed status bit 233" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[232] ,IRQ (QPRC ch.8) preprocessed status bit 232" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQPS[250] ,IRQ (IRQ1 of Input Capture 10) preprocessed status bit 250" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[249] ,IRQ (IRQ1 of Input Capture 9) preprocessed status bit 249" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[248] ,IRQ (IRQ1 of Input Capture 8) preprocessed status bit 248" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[242] ,IRQ (IRQ1 of Input Capture 2) preprocessed status bit 242" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQPS[241] ,IRQ (IRQ1 of Input Capture 1) preprocessed status bit 241" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[240] ,IRQ (IRQ1 of Input Capture 0) preprocessed status bit 240" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[233] ,IRQ (QPRC ch.9) preprocessed status bit 233" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[232] ,IRQ (QPRC ch.8) preprocessed status bit 232" "No interrupt,Interrupt" endif rgroup.long 0xD10++0x3 line.long 0x00 "IRQPS8,IRC IRQ Preprocessed Status Register 8" sif (!cpuis("S6J33*")) bitfld.long 0x00 31. " IRQPS[287] ,IRQ (DMAC Completion ch.10) preprocessed status bit 287" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[286] ,IRQ (DMAC Completion ch.9) preprocessed status bit 286" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[285] ,IRQ (DMAC Completion ch.8) preprocessed status bit 285" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) preprocessed status bit 282" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQPS[280] ,IRQ (DMAC Completion ch.7) preprocessed status bit 280" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[279] ,IRQ (DMAC Completion ch.6) preprocessed status bit 279" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[278] ,IRQ (DMAC Completion ch.5) preprocessed status bit 278" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[277] ,IRQ (DMAC Completion ch.4) preprocessed status bit 277" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQPS[276] ,IRQ (DMAC Completion ch.3) preprocessed status bit 276" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQPS[275] ,IRQ (DMAC Completion ch.2) preprocessed status bit 275" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[274] ,IRQ (DMAC Completion ch.1) preprocessed status bit 274" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[273] ,IRQ (DMAC Completion ch.0) preprocessed status bit 273" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " IRQPS[272] ,IRQ (DMA Error) preprocessed status bit 272" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQPS[267] ,IRQ (IRQ1 of Output Compare 11) preprocessed status bit 267" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[266] ,IRQ (IRQ1 of Output Compare 10) preprocessed status bit 266" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[265] ,IRQ (IRQ1 of Output Compare 9) preprocessed status bit 265" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[264] ,IRQ (IRQ1 of Output Compare 8) preprocessed status bit 264" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[263] ,IRQ (IRQ1 of Output Compare 7) preprocessed status bit 263" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[262] ,IRQ (IRQ1 of Output Compare 6) preprocessed status bit 262" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[261] ,IRQ (IRQ1 of Output Compare 5) preprocessed status bit 261" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQPS[260] ,IRQ (IRQ1 of Output Compare 4) preprocessed status bit 260" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[259] ,IRQ (IRQ1 of Output Compare 3) preprocessed status bit 259" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[258] ,IRQ (IRQ1 of Output Compare 2) preprocessed status bit 258" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[257] ,IRQ (IRQ1 of Output Compare 1) preprocessed status bit 257" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQPS[256] ,IRQ (IRQ1 of Output Compare 0) preprocessed status bit 256" "No interrupt,Interrupt" else bitfld.long 0x00 31. " IRQPS[287] ,IRQ (DMAC Completion ch.10) preprocessed status bit 287" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[286] ,IRQ (DMAC Completion ch.9) preprocessed status bit 286" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[285] ,IRQ (DMAC Completion ch.8) preprocessed status bit 285" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[282] ,IRQ (DMAC RLT(ch.0,1,2,3 OR-ed)) preprocessed status bit 282" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQPS[280] ,IRQ (DMAC Completion ch.7) preprocessed status bit 280" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[279] ,IRQ (DMAC Completion ch.6) preprocessed status bit 279" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[278] ,IRQ (DMAC Completion ch.5) preprocessed status bit 278" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[277] ,IRQ (DMAC Completion ch.4) preprocessed status bit 277" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQPS[276] ,IRQ (DMAC Completion ch.3) preprocessed status bit 276" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQPS[275] ,IRQ (DMAC Completion ch.2) preprocessed status bit 275" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[274] ,IRQ (DMAC Completion ch.1) preprocessed status bit 274" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[273] ,IRQ (DMAC Completion ch.0) preprocessed status bit 273" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " IRQPS[272] ,IRQ (DMA Error) preprocessed status bit 272" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[266] ,IRQ (IRQ1 of Output Compare 10) preprocessed status bit 266" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[265] ,IRQ (IRQ1 of Output Compare 9) preprocessed status bit 265" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[264] ,IRQ (IRQ1 of Output Compare 8) preprocessed status bit 264" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[258] ,IRQ (IRQ1 of Output Compare 2) preprocessed status bit 258" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[257] ,IRQ (IRQ1 of Output Compare 1) preprocessed status bit 257" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQPS[256] ,IRQ (IRQ1 of Output Compare 0) preprocessed status bit 256" "No interrupt,Interrupt" endif rgroup.long 0xD14++0x3 line.long 0x00 "IRQPS9,IRC IRQ Preprocessed Status Register 9" bitfld.long 0x00 24. " IRQPS[312] ,IRQ (CR5 Performance Monitor Unit IRQ) preprocessed status bit 312" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[311] ,IRQ (SCT Sub OSC IRQ) preprocessed status bit 311" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[310] ,IRQ (SCT Main OSC IRQ) preprocessed status bit 310" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[309] ,IRQ (SCT SRC IRQ) preprocessed status bit 309" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQPS[308] ,IRQ (SCT CR IRQ) preprocessed status bit 308" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[292] ,IRQ (DMAC Completion ch.15) preprocessed status bit 292" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[291] ,IRQ (DMAC Completion ch.14) preprocessed status bit 291" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[290] ,IRQ (DMAC Completion ch.13) preprocessed status bit 290" "No interrupt,Interrupt" textline " " bitfld.long 0x00 01. " IRQPS[289] ,IRQ (DMAC Completion ch.12) preprocessed status bit 289" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[288] ,IRQ (DMAC Completion ch.11) preprocessed status bit 288" "No interrupt,Interrupt" rgroup.long 0xD18++0x3 line.long 0x00 "IRQPS10,IRC IRQ Preprocessed Status Register 10" sif (!cpuis("S6J33*")) bitfld.long 0x00 30. " IRQPS[350] ,IRQ (SG ch.3) preprocessed status bit 350" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[349] ,IRQ (SG ch.2) preprocessed status bit 349" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[348] ,IRQ (SG ch.1) preprocessed status bit 348" "No interrupt,Interrupt" bitfld.long 0x00 27. " IRQPS[347] ,IRQ (SG ch.0) preprocessed status bit 347" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " IRQPS[344] ,IRQ (SMC ch.5) preprocessed status bit 344" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[343] ,IRQ (SMC ch.4) preprocessed status bit 343" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[342] ,IRQ (SMC ch.3) preprocessed status bit 342" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[341] ,IRQ (SMC ch.2) preprocessed status bit 341" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " IRQPS[340] ,IRQ (SMC ch.1) preprocessed status bit 340" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQPS[339] ,IRQ (SMC ch.0) preprocessed status bit 339" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[337] ,IRQ (MFS ch.17 Error) preprocessed status bit 337" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[336] ,IRQ (MFS ch.16 Error) preprocessed status bit 336" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " IRQPS[332] ,IRQ (MFS ch.12 Error) preprocessed status bit 332" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQPS[331] ,IRQ (MFS ch.11 Error) preprocessed status bit 331" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[330] ,IRQ (MFS ch.10 Error) preprocessed status bit 330" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[329] ,IRQ (MFS ch.9 Error) preprocessed status bit 329" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[328] ,IRQ (MFS ch.8 Error) preprocessed status bit 328" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[324] ,IRQ (MFS ch.4 Error) preprocessed status bit 324" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[323] ,IRQ (MFS ch.3 Error) preprocessed status bit 323" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[322] ,IRQ (MFS ch.2 Error) preprocessed status bit 322" "No interrupt,Interrupt" textline " " bitfld.long 0x00 01. " IRQPS[321] ,IRQ (MFS ch.1 Error) preprocessed status bit 321" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[320] ,IRQ (MFS ch.0 Error) preprocessed status bit 320" "No interrupt,Interrupt" else sif (!cpuis("S6J335*")) bitfld.long 0x00 31. " IRQPS[351] ,IRQ (SG ch.4) preprocessed status bit 350" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[350] ,IRQ (SG ch.3) preprocessed status bit 350" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[349] ,IRQ (SG ch.2) preprocessed status bit 349" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[348] ,IRQ (SG ch.1) preprocessed status bit 348" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQPS[347] ,IRQ (SG ch.0) preprocessed status bit 347" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[337] ,IRQ (MFS ch.17 Error) preprocessed status bit 337" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[336] ,IRQ (MFS ch.16 Error) preprocessed status bit 336" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQPS[332] ,IRQ (MFS ch.12 Error) preprocessed status bit 332" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQPS[331] ,IRQ (MFS ch.11 Error) preprocessed status bit 331" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[330] ,IRQ (MFS ch.10 Error) preprocessed status bit 330" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[329] ,IRQ (MFS ch.9 Error) preprocessed status bit 329" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[328] ,IRQ (MFS ch.8 Error) preprocessed status bit 328" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQPS[324] ,IRQ (MFS ch.4 Error) preprocessed status bit 324" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[323] ,IRQ (MFS ch.3 Error) preprocessed status bit 323" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[322] ,IRQ (MFS ch.2 Error) preprocessed status bit 322" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[321] ,IRQ (MFS ch.1 Error) preprocessed status bit 321" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQPS[320] ,IRQ (MFS ch.0 Error) preprocessed status bit 320" "No interrupt,Interrupt" else bitfld.long 0x00 17. " IRQPS[337] ,IRQ (MFS ch.17 Error) preprocessed status bit 337" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[336] ,IRQ (MFS ch.16 Error) preprocessed status bit 336" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQPS[332] ,IRQ (MFS ch.12 Error) preprocessed status bit 332" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQPS[331] ,IRQ (MFS ch.11 Error) preprocessed status bit 331" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " IRQPS[330] ,IRQ (MFS ch.10 Error) preprocessed status bit 330" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[329] ,IRQ (MFS ch.9 Error) preprocessed status bit 329" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[328] ,IRQ (MFS ch.8 Error) preprocessed status bit 328" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[324] ,IRQ (MFS ch.4 Error) preprocessed status bit 324" "No interrupt,Interrupt" textline " " bitfld.long 0x00 03. " IRQPS[323] ,IRQ (MFS ch.3 Error) preprocessed status bit 323" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[322] ,IRQ (MFS ch.2 Error) preprocessed status bit 322" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[321] ,IRQ (MFS ch.1 Error) preprocessed status bit 321" "No interrupt,Interrupt" bitfld.long 0x00 00. " IRQPS[320] ,IRQ (MFS ch.0 Error) preprocessed status bit 320" "No interrupt,Interrupt" endif endif rgroup.long 0xD1C++0x3 line.long 0x00 "IRQPS11,IRC IRQ Preprocessed Status Register 11" sif (!cpuis("S6J334*")) sif (!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) bitfld.long 0x00 26. " IRQPS[378] ,IRQ (I2S1_IRQ) preprocessed status bit 378" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[377] ,IRQ (I2S0_IRQ) preprocessed status bit 377" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[376] ,IRQ (AUDIO_DAC_DMAE_IRQ) preprocessed status bit 376" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[375] ,IRQ (AUDIO_DAC_UDRN_IRQ) preprocessed status bit 375" "No interrupt,Interrupt" textline " " bitfld.long 0x00 22. " IRQPS[374] ,IRQ (AUDIO_DAC_OVFL_IRQ) preprocessed status bit 374" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[373] ,IRQ (AUDIO_DAC_DREQ) preprocessed status bit 373" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[372] ,IRQ (PCMPWM_DMAE) preprocessed status bit 372" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQPS[371] ,IRQ (PCMPWM_UDRN) preprocessed status bit 371" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " IRQPS[370] ,IRQ (PCMPWM_OVFL) preprocessed status bit 370" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[369] ,IRQ (PCMPWM_DREQ) preprocessed status bit 369" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[368] ,IRQ (Indicator PWM) preprocessed status bit 368" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQPS[364] ,IRQ (ETHERNET Q3 IRQ) preprocessed status bit 364" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQPS[363] ,IRQ (ETHERNET Q2 IRQ) preprocessed status bit 363" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[362] ,IRQ (ETHERNET Q1 IRQ) preprocessed status bit 362" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[361] ,IRQ (ETHERNET IRQ) preprocessed status bit 361" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[360] ,IRQ (MLB system interrupt) preprocessed status bit 360" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQPS[359] ,IRQ (MLB channel interrupt) preprocessed status bit 359" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[357] ,IRQ (RPGCRC) preprocessed status bit 357" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[356] ,IRQ (ADC12B RCO) preprocessed status bit 356" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[355] ,IRQ (ADC12B pulse detection function) preprocessed status bit 355" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQPS[354] ,IRQ (ADC12B Group interrupt) preprocessed status bit 354" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[353] ,IRQ (ADC12B Conversion Done) preprocessed status bit 353" "No interrupt,Interrupt" else bitfld.long 0x00 26. " IRQPS[378] ,IRQ (I2S1_IRQ) preprocessed status bit 378" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[377] ,IRQ (I2S0_IRQ) preprocessed status bit 377" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[368] ,IRQ (Indicator PWM) preprocessed status bit 368" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQPS[364] ,IRQ (ETHERNET Q3 IRQ) preprocessed status bit 364" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQPS[363] ,IRQ (ETHERNET Q2 IRQ) preprocessed status bit 363" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[362] ,IRQ (ETHERNET Q1 IRQ) preprocessed status bit 362" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[361] ,IRQ (ETHERNET IRQ) preprocessed status bit 361" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[360] ,IRQ (MLB system interrupt) preprocessed status bit 360" "No interrupt,Interrupt" textline " " bitfld.long 0x00 07. " IRQPS[359] ,IRQ (MLB channel interrupt) preprocessed status bit 359" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[357] ,IRQ (RPGCRC) preprocessed status bit 357" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[356] ,IRQ (ADC12B RCO) preprocessed status bit 356" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[355] ,IRQ (ADC12B pulse detection function) preprocessed status bit 355" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQPS[354] ,IRQ (ADC12B Group interrupt) preprocessed status bit 354" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[353] ,IRQ (ADC12B Conversion Done) preprocessed status bit 353" "No interrupt,Interrupt" endif else bitfld.long 0x00 16. " IRQPS[368] ,IRQ (Indicator PWM) preprocessed status bit 368" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[357] ,IRQ (RPGCRC) preprocessed status bit 357" "No interrupt,Interrupt" bitfld.long 0x00 04. " IRQPS[356] ,IRQ (ADC12B RCO) preprocessed status bit 356" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[355] ,IRQ (ADC12B pulse detection function) preprocessed status bit 355" "No interrupt,Interrupt" textline " " bitfld.long 0x00 02. " IRQPS[354] ,IRQ (ADC12B Group interrupt) preprocessed status bit 354" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[353] ,IRQ (ADC12B Conversion Done) preprocessed status bit 353" "No interrupt,Interrupt" endif rgroup.long 0xD20++0x3 line.long 0x00 "IRQPS12,IRC IRQ Preprocessed Status Register 12" sif (cpuis("S6J33*")) bitfld.long 0x00 25. " IRQPS[409] ,IRQ (2D Graphics Core Display0 Sync1) preprocessed status bit 409" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[408] ,IRQ (2D Graphics Core Display0 Sync0) preprocessed status bit 408" "No interrupt,Interrupt" bitfld.long 0x00 23. " IRQPS[407] ,IRQ (2D Graphics Core Signature0) preprocessed status bit 407" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[406] ,IRQ (2D Graphics Core Display Stream0) preprocessed status bit 406" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " IRQPS[405] ,IRQ (2D Graphics Core Safety Stream0) preprocessed status bit 405" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[404] ,IRQ (2D Graphics Core Content Stream0) preprocessed status bit 404" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQPS[403] ,IRQ (2D Graphics Core Drawing Engine) preprocessed status bit 403" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[402] ,IRQ (2D Graphics Core Blit Engine) preprocessed status bit 402" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " IRQPS[401] ,IRQ (2D Graphics Core Command Sequencer) preprocessed status bit 401" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQPS[395] ,IRQ (Base Timer ch.31) preprocessed status bit 395" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[394] ,IRQ (Base Timer ch.30) preprocessed status bit 394" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQPS[393] ,IRQ (Base Timer ch.29) preprocessed status bit 393" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " IRQPS[392] ,IRQ (Base Timer ch.28) preprocessed status bit 392" "No interrupt,Interrupt" bitfld.long 0x00 7. " IRQPS[391] ,IRQ (Base Timer ch.27) preprocessed status bit 391" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQPS[390] ,IRQ (Base Timer ch.26) preprocessed status bit 390" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQPS[389] ,IRQ (Base Timer ch.25) preprocessed status bit 389" "No interrupt,Interrupt" textline " " sif (cpuis("S6J335*")) bitfld.long 0x00 4. " IRQPS[388] ,IRQ (Base Timer ch.24/32/33/34/35) preprocessed status bit 401" "No interrupt,Interrupt" else bitfld.long 0x00 4. " IRQPS[388] ,IRQ (Base Timer ch.24) preprocessed status bit 401" "No interrupt,Interrupt" endif else bitfld.long 0x00 31. " IRQPS[415] ,IRQ (2D Graphics Core Display1 Sync1) preprocessed status bit 415" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[414] ,IRQ (2D Graphics Core Display1 Sync0) preprocessed status bit 414" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[413] ,IRQ (2D Graphics Core Signature1) preprocessed status bit 413" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[412] ,IRQ (2D Graphics Core Display Stream1) preprocessed status bit 412" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQPS[411] ,IRQ (2D Graphics Core Safety Stream1) preprocessed status bit 411" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[410] ,IRQ (2D Graphics Core Content Stream1) preprocessed status bit 410" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[409] ,IRQ (2D Graphics Core Display0 Sync1) preprocessed status bit 409" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[408] ,IRQ (2D Graphics Core Display0 Sync0) preprocessed status bit 408" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[407] ,IRQ (2D Graphics Core Signature0) preprocessed status bit 407" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[406] ,IRQ (2D Graphics Core Display Stream0) preprocessed status bit 406" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[405] ,IRQ (2D Graphics Core Safety Stream0) preprocessed status bit 405" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[404] ,IRQ (2D Graphics Core Content Stream0) preprocessed status bit 404" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQPS[403] ,IRQ (2D Graphics Core Drawing Engine) preprocessed status bit 403" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[402] ,IRQ (2D Graphics Core Blit Engine) preprocessed status bit 402" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[401] ,IRQ (2D Graphics Core Command Sequencer) preprocessed status bit 401" "No interrupt,Interrupt" endif rgroup.long 0xD24++0x3 line.long 0x00 "IRQPS13,IRC IRQ Preprocessed Status Register 13" sif (cpuis("S6J33*")) sif (!cpuis("S6J335*")) bitfld.long 0x00 31. " IRQPS[447] ,IRQ (MX_OVFL_IRQ4) preprocessed status bit 447" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[446] ,IRQ (MX_OVFL_IRQ3) preprocessed status bit 446" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[445] ,IRQ (MX_OVFL_IRQ2) preprocessed status bit 445" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[444] ,IRQ (MX_OVFL_IRQ1) preprocessed status bit 444" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQPS[443] ,IRQ (MX_OVFL_IRQ0) preprocessed status bit 443" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[442] ,IRQ (MX_DATA_REQ_IRQ4) preprocessed status bit 442" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[441] ,IRQ (MX_DATA_REQ_IRQ3) preprocessed status bit 441" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[440] ,IRQ (MX_DATA_REQ_IRQ2) preprocessed status bit 440" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[439] ,IRQ (MX_DATA_REQ_IRQ1) preprocessed status bit 439" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[438] ,IRQ (MX_DATA_REQ_IRQ0) preprocessed status bit 438" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[437] ,IRQ (WG_AHB_ERR_IRQ) preprocessed status bit 437" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[436] ,IRQ (WG_END_IRQ4) preprocessed status bit 436" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQPS[435] ,IRQ (WG_END_IRQ3) preprocessed status bit 435" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[434] ,IRQ (WG_END_IRQ2) preprocessed status bit 434" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[433] ,IRQ (WG_END_IRQ1) preprocessed status bit 433" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[432] ,IRQ (WG_END_IRQ0) preprocessed status bit 432" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 07. " IRQPS[423] ,IRQ (2D Graphics Core LCDBusIf_Control) preprocessed status bit 423" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[422] ,IRQ (2D Graphics Core LCDBusIf_InstrFifo) preprocessed status bit 422" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[421] ,IRQ (2D Graphics Core LCDBusIf_Control) preprocessed status bit 421" "No interrupt,Interrupt" else bitfld.long 0x00 31. " IRQPS[447] ,IRQ (MX_OVFL_IRQ4) preprocessed status bit 447" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[446] ,IRQ (MX_OVFL_IRQ3) preprocessed status bit 446" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[445] ,IRQ (MX_OVFL_IRQ2) preprocessed status bit 445" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[444] ,IRQ (MX_OVFL_IRQ1) preprocessed status bit 444" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQPS[443] ,IRQ (MX_OVFL_IRQ0) preprocessed status bit 443" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[442] ,IRQ (MX_DATA_REQ_IRQ4) preprocessed status bit 442" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[441] ,IRQ (MX_DATA_REQ_IRQ3) preprocessed status bit 441" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[440] ,IRQ (MX_DATA_REQ_IRQ2) preprocessed status bit 440" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[439] ,IRQ (MX_DATA_REQ_IRQ1) preprocessed status bit 439" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[438] ,IRQ (MX_DATA_REQ_IRQ0) preprocessed status bit 438" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[437] ,IRQ (WG_AHB_ERR_IRQ) preprocessed status bit 437" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[436] ,IRQ (WG_END_IRQ4) preprocessed status bit 436" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQPS[435] ,IRQ (WG_END_IRQ3) preprocessed status bit 435" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[434] ,IRQ (WG_END_IRQ2) preprocessed status bit 434" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[433] ,IRQ (WG_END_IRQ1) preprocessed status bit 433" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[432] ,IRQ (WG_END_IRQ0) preprocessed status bit 432" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " IRQPS[428] ,IRQ (3D Graphics Core SBEI) preprocessed status bit 428" "No interrupt,Interrupt" bitfld.long 0x00 11. " IRQPS[427] ,IRQ (3D Graphics Core BEI) preprocessed status bit 427" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[426] ,IRQ (3D Graphics Core CAEI) preprocessed status bit 426" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[425] ,IRQ (3D Graphics Core DEI) preprocessed status bit 425" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[424] ,IRQ (3D Graphics Core DLEI) preprocessed status bit 424" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[423] ,IRQ (3D Graphics Core DFI) preprocessed status bit 423" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[422] ,IRQ (3D Graphics Core LINI) preprocessed status bit 422" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[421] ,IRQ (3D Graphics Core SRUI) preprocessed status bit 421" "No interrupt,Interrupt" textline " " bitfld.long 0x00 04. " IRQPS[420] ,IRQ (2D Graphics Core DDRHSSPI) preprocessed status bit 420" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[419] ,IRQ (2D Graphics Core Histogram) preprocessed status bit 419" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[418] ,IRQ (2D Graphics Core Storage Stream0) preprocessed status bit 418" "No interrupt,Interrupt" bitfld.long 0x00 01. " IRQPS[417] ,IRQ (2D Graphics Core Display Plane0) preprocessed status bit 417" "No interrupt,Interrupt" textline " " bitfld.long 0x00 00. " IRQPS[416] ,IRQ (2D Graphics Core Capture Plane0) preprocessed status bit 416" "No interrupt,Interrupt" endif rgroup.long 0xD28++0x3 line.long 0x00 "IRQPS14,IRC IRQ Preprocessed Status Register 14" sif (cpuis("S6J33*")) sif (cpuis("S6J331*")) bitfld.long 0x00 13. " IRQPS[461] ,IRQ (ARH IRQ2) preprocessed status bit 461" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQPS[460] ,IRQ (ARH IRQ1) preprocessed status bit 460" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQPS[458] ,IRQ (MX_AHB_ERR_IRQ) preprocessed status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[457] ,IRQ (MX_DMA_ERR_IRQ4) preprocessed status bit 457" "No interrupt,Interrupt" textline " " bitfld.long 0x00 08. " IRQPS[456] ,IRQ (MX_DMA_ERR_IRQ3) preprocessed status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[455] ,IRQ (MX_DMA_ERR_IRQ2) preprocessed status bit 455" "No interrupt,Interrupt" bitfld.long 0x00 06. " IRQPS[454] ,IRQ (MX_DMA_ERR_IRQ1) preprocessed status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[453] ,IRQ (MX_DMA_ERR_IRQ0) preprocessed status bit 453" "No interrupt,Interrupt" elif (cpuis("S6J333*")) bitfld.long 0x00 19. " IRQPS[467] ,IRQ (ADC12B1 RCO) preprocessed status bit 467" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQPS[466] ,IRQ (ADC12B1 pulse detection function) preprocessed status bit 466" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQPS[465] ,IRQ (ADC12B1 Group interrupt) preprocessed status bit 465" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[464] ,IRQ (ADC12B1 Conversion Done) preprocessed status bit 464" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " IRQPS[458] ,IRQ (MX_AHB_ERR_IRQ) preprocessed status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[457] ,IRQ (MX_DMA_ERR_IRQ4) preprocessed status bit 457" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[456] ,IRQ (MX_DMA_ERR_IRQ3) preprocessed status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[455] ,IRQ (MX_DMA_ERR_IRQ2) preprocessed status bit 455" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " IRQPS[454] ,IRQ (MX_DMA_ERR_IRQ1) preprocessed status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[453] ,IRQ (MX_DMA_ERR_IRQ0) preprocessed status bit 453" "No interrupt,Interrupt" elif (cpuis("S6J335*")) bitfld.long 0x00 31. " IRQPS[479] ,IRQ (Base Timer ch.51) preprocessed status bit 479" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[478] ,IRQ (Base Timer ch.50) preprocessed status bit 478" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[477] ,IRQ (Base Timer ch.49) preprocessed status bit 477" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[476] ,IRQ (Base Timer ch.48/56/57/58/59) preprocessed status bit 476" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQPS[475] ,IRQ (Base Timer ch.43) preprocessed status bit 475" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[474] ,IRQ (Base Timer ch.42) preprocessed status bit 474" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[473] ,IRQ (Base Timer ch.41) preprocessed status bit 473" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[472] ,IRQ (Base Timer ch.40) preprocessed status bit 472" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQPS[471] ,IRQ (Base Timer ch.39) preprocessed status bit 471" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQPS[470] ,IRQ (Base Timer ch.38) preprocessed status bit 470" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQPS[469] ,IRQ (Base Timer ch.37) preprocessed status bit 469" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQPS[468] ,IRQ (Base Timer ch.36/44/45/46/47) preprocessed status bit 468" "No interrupt,Interrupt" else bitfld.long 0x00 10. " IRQPS[458] ,IRQ (MX_AHB_ERR_IRQ) preprocessed status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[457] ,IRQ (MX_DMA_ERR_IRQ4) preprocessed status bit 457" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[456] ,IRQ (MX_DMA_ERR_IRQ3) preprocessed status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[455] ,IRQ (MX_DMA_ERR_IRQ2) preprocessed status bit 455" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " IRQPS[454] ,IRQ (MX_DMA_ERR_IRQ1) preprocessed status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[453] ,IRQ (MX_DMA_ERR_IRQ0) preprocessed status bit 453" "No interrupt,Interrupt" endif else bitfld.long 0x00 10. " IRQPS[458] ,IRQ (MX_AHB_ERR_IRQ) preprocessed status bit 458" "No interrupt,Interrupt" bitfld.long 0x00 09. " IRQPS[457] ,IRQ (MX_DMA_ERR_IRQ4) preprocessed status bit 457" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[456] ,IRQ (MX_DMA_ERR_IRQ3) preprocessed status bit 456" "No interrupt,Interrupt" bitfld.long 0x00 07. " IRQPS[455] ,IRQ (MX_DMA_ERR_IRQ2) preprocessed status bit 455" "No interrupt,Interrupt" textline " " bitfld.long 0x00 06. " IRQPS[454] ,IRQ (MX_DMA_ERR_IRQ1) preprocessed status bit 454" "No interrupt,Interrupt" bitfld.long 0x00 05. " IRQPS[453] ,IRQ (MX_DMA_ERR_IRQ0) preprocessed status bit 453" "No interrupt,Interrupt" endif sif (cpuis("S6J335*")) rgroup.long 0xD2C++0x3 line.long 0x00 "IRQPS15,IRC IRQ Preprocessed Status Register 15" bitfld.long 0x00 7. " IRQPS[487] ,IRQ (Base Timer ch.63) preprocessed status bit 487" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQPS[486] ,IRQ (Base Timer ch.62) preprocessed status bit 486" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQPS[485] ,IRQ (Base Timer ch.61) preprocessed status bit 485" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQPS[484] ,IRQ (Base Timer ch.60) preprocessed status bit 484" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQPS[483] ,IRQ (Base Timer ch.55) preprocessed status bit 483" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQPS[482] ,IRQ (Base Timer ch.54) preprocessed status bit 482" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQPS[481] ,IRQ (Base Timer ch.53) preprocessed status bit 481" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQPS[480] ,IRQ (Base Timer ch.52) preprocessed status bit 480" "No interrupt,Interrupt" endif tree.end textline " " group.long 0xD30++0x3 line.long 0x00 "UNLOCK,IRC Unlock Register" group.long 0xD3C++0x3 line.long 0x00 "IRQEEVA,IRC ECC Error Vector Address Register" group.long 0xD40++0x3 line.long 0x00 "EEI,IRC ECC Error Interrupt Register" rbitfld.long 0x00 24. " EEIS ,ECC error IRQ status bit" "Not occurred,Occurred" bitfld.long 0x00 16. " EEIC ,ECC error IRQ clear bit" "No effect,Clear" rbitfld.long 0x00 8. " EENS ,ECC error NMI status bit" "Not occurred,Occurred" bitfld.long 0x00 0. " EENC ,ECC error NMI clear bit" "No effect,Clear" rgroup.long 0xD44++0x3 line.long 0x00 "EAN,IRC ECC Address Number Register" hexmask.long.byte 0x00 0.--7. 1. " EAN ,ECC error occurrence address bits" group.long 0xD48++0x3 line.long 0x00 "ET,IRC ECC Test Register" bitfld.long 0x00 0. " ET ,ECC test enable/disable setting bit" "Disabled,Enabled" group.long 0xD4C++0x3 line.long 0x00 "EEB0,IRC ECC Bit Register" hexmask.long 0x00 2.--31. 1. " EEB ,ECC error occurrence bits" group.long 0xD50++0x3 line.long 0x00 "EEB1,IRC ECC Bit Register" hexmask.long 0x00 2.--31. 1. " EEB ,ECC error occurrence bits" group.long 0xD54++0x3 line.long 0x00 "EEB2,IRC ECC Bit Register" hexmask.long.byte 0x00 8.--14. 1. " EEBO ,ECC error occurrence bits" hexmask.long.byte 0x00 0.--6. 1. " EEBE ,ECC error occurrence bits" width 15. sif (cpu()=="S6J3118HAA")||(cpu()=="S6J3119HAA")||(cpu()=="S6J311AHAA")||(cpu()=="S6J311BJAA")||(cpu()=="S6J311CJAA")||(cpu()=="S6J311DJAA")||(cpu()=="S6J311EJAA")||(cpuis("S6J33*")) base ad:0xFFFEE3FC rgroup.long 0x00++0x03 "Register Memory Layout of Interrupt Controler (HSEL2)" line.long 0x00 "IRC_NMIVASBR,IRC NMI Vector Address Status Register" rgroup.long 0x1800++0x03 "Register Memory Layout of Interrupt Controler (HSEL3)" line.long 0x00 "IRC0_NMIVASBR,IRC NMI Vector Address Status Mirror Register" else rgroup.long 0x3F8++0x03 "Register Memory Layout of Interrupt Controler (HSEL2)" line.long 0x00 "IRC_NMIVASBR,IRC NMI Vector Address Status Register" rgroup.long 0x3FC++0x03 "Register Memory Layout of Interrupt Controler (HSEL3)" line.long 0x00 "IRC0_NMIVASBR,IRC NMI Vector Address Status Mirror Register" endif width 0x0B else width 10. rgroup.long 0x00++0x0F line.long 0x00 "NMIVAS,IRC NMI Vector Address Status Register" line.long 0x04 "NMIST,IRC NMI Status Register" bitfld.long 0x04 8.--11. " NMIPS ,NMI priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--5. " NMISN ,NMI channel number bits" "0,,,,4,5,6,7,8,9,,,12,13,,15,,,18,,20,?..." line.long 0x08 "IRQVAS,IRC IRQ Vector Address Status Register" line.long 0x0C "IRQST,IRC IRQ Status Register" bitfld.long 0x0C 24. " NIRQ ,IRQ interrupt status bit" "No interrupt,Interrupt" bitfld.long 0x0C 16.--20. " IRQPS ,IRQ priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0C 0.--9. 1. " IRQSN ,IRQ channel number bits" tree "NMI Vector Address Registers" group.long 0x10++0x03 line.long 0x00 "NMIVA0,(NMIX pin (Ext-IRC)) NMI Vector Address Bits" group.long 0x20++0x17 line.long 0x00 "NMIVA4,(LVDs IRQ) NMI Vector Address Bits" line.long 0x04 "NMIVA5,(CSV Profile) NMI Vector Address Bits" line.long 0x08 "NMIVA6,(HW-WDT NMI) Vector Address Bits" line.long 0x0C "NMIVA7,(SW-WDT NMI) Vector Address Bits" line.long 0x10 "NMIVA8,(IRC 2-bit ECC error detection) NMI Vector Address Bits" line.long 0x14 "NMIVA9,(Expand PPL CSV(OR-ed of all factors)) NMI Vector Address Bits" group.long 0x40++0x07 line.long 0x00 "NMIVA12,(CAN-FD RAMs 2-bit ECC error detection) NMI Vector Address Bits" line.long 0x04 "NMIVA13,(DMAC MPU #0 protection violation) NMI Vector Address Bits" group.long 0x4C++0x03 line.long 0x00 "NMIVA15,(SHE MPU) NMI Vector Address Bits" group.long 0x58++0x03 line.long 0x00 "NMIVA18,(TPU protection violation) NMI Vector Address Bits" group.long 0x60++0x03 line.long 0x00 "NMIVA20,(LCDBUS MPU) NMI Vector Address Bits" tree.end tree "IRQ Vector Address Registers" group.long 0x94++0x0B line.long 0x00 "IRQVA1,(System Control Status) IRQ Vector Address Bits" line.long 0x04 "IRQVA2,(HW-WDT Pre-warning) IRQ Vector Address Bits" line.long 0x08 "IRQVA3,(SW-WDT Pre-warning) IRQ Vector Address Bits" group.long 0xB0++0x03 line.long 0x00 "IRQVA8,(TCFLASH Single Bit Error) IRQ Vector Address Bits" group.long 0xB8++0x03 line.long 0x00 "IRQVA10,(Work FLASH Single Bit Error) IRQ Vector Address Bits" group.long 0xC8++0x0B line.long 0x00 "IRQVA14,(System RAM Single Bit Error) IRQ Vector Address Bits" line.long 0x04 "IRQVA15,(CAN FD RAM(ch.0 to ch.3) Single Bit Error) IRQ Vector Address Bits" line.long 0x08 "IRQVA16,(IRC Vector Address Ram Single Bit Error) IRQ Vector Address Bits" group.long 0xE0++0x03 line.long 0x00 "IRQVA20,(Work FLASH (RDY Interrupt Request)/(Write Completion)) IRQ Vector Address Bits" group.long 0xF0++0x03 line.long 0x00 "IRQVA24,(External Interrupt Request ch.0/ch.16) IRQ Vector Address Bits" group.long 0xF4++0x03 line.long 0x00 "IRQVA25,(External Interrupt Request ch.1/ch.17) IRQ Vector Address Bits" group.long 0xF8++0x03 line.long 0x00 "IRQVA26,(External Interrupt Request ch.2/ch.18) IRQ Vector Address Bits" group.long 0xFC++0x03 line.long 0x00 "IRQVA27,(External Interrupt Request ch.3/ch.19) IRQ Vector Address Bits" group.long 0x100++0x03 line.long 0x00 "IRQVA28,(External Interrupt Request ch.4/ch.20) IRQ Vector Address Bits" group.long 0x104++0x03 line.long 0x00 "IRQVA29,(External Interrupt Request ch.5/ch.21) IRQ Vector Address Bits" group.long 0x108++0x03 line.long 0x00 "IRQVA30,(External Interrupt Request ch.6/ch.22) IRQ Vector Address Bits" group.long 0x10C++0x03 line.long 0x00 "IRQVA31,(External Interrupt Request ch.7/ch.23) IRQ Vector Address Bits" group.long 0x110++0x03 line.long 0x00 "IRQVA32,(External Interrupt Request ch.8) IRQ Vector Address Bits" group.long 0x114++0x03 line.long 0x00 "IRQVA33,(External Interrupt Request ch.9) IRQ Vector Address Bits" group.long 0x118++0x03 line.long 0x00 "IRQVA34,(External Interrupt Request ch.10) IRQ Vector Address Bits" group.long 0x11C++0x03 line.long 0x00 "IRQVA35,(External Interrupt Request ch.11) IRQ Vector Address Bits" group.long 0x120++0x03 line.long 0x00 "IRQVA36,(External Interrupt Request ch.12) IRQ Vector Address Bits" group.long 0x124++0x03 line.long 0x00 "IRQVA37,(External Interrupt Request ch.13) IRQ Vector Address Bits" group.long 0x128++0x03 line.long 0x00 "IRQVA38,(External Interrupt Request ch.14) IRQ Vector Address Bits" group.long 0x12C++0x03 line.long 0x00 "IRQVA39,(External Interrupt Request ch.15) IRQ Vector Address Bits" group.long 0x130++0x03 line.long 0x00 "IRQVA40,(CAN FD ch.0) IRQ Vector Address Bits" group.long 0x134++0x03 line.long 0x00 "IRQVA41,(CAN FD ch.1) IRQ Vector Address Bits" group.long 0x138++0x03 line.long 0x00 "IRQVA42,(CAN FD ch.2) IRQ Vector Address Bits" group.long 0x13C++0x03 line.long 0x00 "IRQVA43,(CAN FD ch.3) IRQ Vector Address Bits" group.long 0x148++0x03 line.long 0x00 "IRQVA46,(MFS RX ch.0) IRQ Vector Address Bits" group.long (0x148+0x04)++0x03 line.long 0x00 "IRQVA47,(MFS TX ch.0) IRQ Vector Address Bits" group.long 0x150++0x03 line.long 0x00 "IRQVA48,(MFS RX ch.1) IRQ Vector Address Bits" group.long (0x150+0x04)++0x03 line.long 0x00 "IRQVA49,(MFS TX ch.1) IRQ Vector Address Bits" group.long 0x158++0x03 line.long 0x00 "IRQVA50,(MFS RX ch.2) IRQ Vector Address Bits" group.long (0x158+0x04)++0x03 line.long 0x00 "IRQVA51,(MFS TX ch.2) IRQ Vector Address Bits" group.long 0x160++0x03 line.long 0x00 "IRQVA52,(MFS RX ch.3) IRQ Vector Address Bits" group.long (0x160+0x04)++0x03 line.long 0x00 "IRQVA53,(MFS TX ch.3) IRQ Vector Address Bits" group.long 0x168++0x03 line.long 0x00 "IRQVA54,(MFS RX ch.4) IRQ Vector Address Bits" group.long (0x168+0x04)++0x03 line.long 0x00 "IRQVA55,(MFS TX ch.4) IRQ Vector Address Bits" group.long 0x170++0x03 line.long 0x00 "IRQVA56,(MFS RX ch.5) IRQ Vector Address Bits" group.long (0x170+0x04)++0x03 line.long 0x00 "IRQVA57,(MFS TX ch.5) IRQ Vector Address Bits" group.long 0x178++0x03 line.long 0x00 "IRQVA58,(MFS RX ch.6) IRQ Vector Address Bits" group.long (0x178+0x04)++0x03 line.long 0x00 "IRQVA59,(MFS TX ch.6) IRQ Vector Address Bits" group.long 0x180++0x03 line.long 0x00 "IRQVA60,(MFS RX ch.7) IRQ Vector Address Bits" group.long (0x180+0x04)++0x03 line.long 0x00 "IRQVA61,(MFS TX ch.7) IRQ Vector Address Bits" group.long 0x188++0x03 line.long 0x00 "IRQVA62,(MFS RX ch.8) IRQ Vector Address Bits" group.long (0x188+0x04)++0x03 line.long 0x00 "IRQVA63,(MFS TX ch.8) IRQ Vector Address Bits" group.long 0x190++0x03 line.long 0x00 "IRQVA64,(MFS RX ch.9) IRQ Vector Address Bits" group.long (0x190+0x04)++0x03 line.long 0x00 "IRQVA65,(MFS TX ch.9) IRQ Vector Address Bits" group.long 0x198++0x03 line.long 0x00 "IRQVA66,(MFS RX ch.10) IRQ Vector Address Bits" group.long (0x198+0x04)++0x03 line.long 0x00 "IRQVA67,(MFS TX ch.10) IRQ Vector Address Bits" group.long 0x1A0++0x03 line.long 0x00 "IRQVA68,(MFS RX ch.11) IRQ Vector Address Bits" group.long (0x1A0+0x04)++0x03 line.long 0x00 "IRQVA69,(MFS TX ch.11) IRQ Vector Address Bits" group.long 0x1B8++0x03 line.long 0x00 "IRQVA74,(SMC ch.0) IRQ Vector Address Bits" group.long 0x1BC++0x03 line.long 0x00 "IRQVA75,(SMC ch.1) IRQ Vector Address Bits" group.long 0x1C0++0x03 line.long 0x00 "IRQVA76,(SMC ch.2) IRQ Vector Address Bits" group.long 0x1C4++0x03 line.long 0x00 "IRQVA77,(SMC ch.3) IRQ Vector Address Bits" group.long 0x1C8++0x03 line.long 0x00 "IRQVA78,(SMC ch.4) IRQ Vector Address Bits" group.long 0x1CC++0x03 line.long 0x00 "IRQVA79,(SMC ch.5) IRQ Vector Address Bits" group.long 0x1D0++0x03 line.long 0x00 "IRQVA80,(SG ch.0) IRQ Vector Address Bits" group.long 0x1D4++0x03 line.long 0x00 "IRQVA81,(SG ch.1) IRQ Vector Address Bits" group.long 0x1D8++0x03 line.long 0x00 "IRQVA82,(SG ch.2) IRQ Vector Address Bits" group.long 0x1DC++0x03 line.long 0x00 "IRQVA83,(SG ch.3) IRQ Vector Address Bits" group.long 0x1E0++0x03 line.long 0x00 "IRQVA84,(SG ch.4) IRQ Vector Address Bits" group.long 0x1E4++0x2B line.long 0x00 "IRQVA85,(LCD bus interface sequencer sync interrupt) IRQ Vector Address Bits" line.long 0x04 "IRQVA86,(LCD bus interface InstrFifointerrupt) IRQ Vector Address Bits" line.long 0x08 "IRQVA87,(LCD bus interface RxFifoInterrupt) IRQ Vector Address Bits" line.long 0x0C "IRQVA88,(LCD bus interface ReadChannelDone) IRQ Vector Address Bits" line.long 0x10 "IRQVA89,(LCD bus interface WriteChannelDone) IRQ Vector Address Bits" line.long 0x14 "IRQVA90,(Indicator PWM) IRQ Vector Address Bits" line.long 0x18 "IRQVA91,(SHE error) IRQ Vector Address Bits" line.long 0x1C "IRQVA92,(SHE)) IRQ Vector Address Bits" line.long 0x20 "IRQVA93,(DDR HSSPI RX) IRQ Vector Address Bits" line.long 0x24 "IRQVA94,(DDR HSSPI TX) IRQ Vector Address Bits" line.long 0x28 "IRQVA95,(TCRAM diag) IRQ Vector Address Bits" group.long 0x214++0x0F line.long 0x00 "IRQVA97,(Global Timer) IRQ Vector Address Bits" line.long 0x04 "IRQVA98,(RTC) IRQ Vector Address Bits" line.long 0x08 "IRQVA99,(CR calibration) IRQ Vector Address Bits" line.long 0x0C "IRQVA100,(Base Timer ch.0/8/9/10/11) IRQ Vector Address Bits" group.long 0x224++0x03 line.long 0x00 "IRQVA101,(Base Timer ch.1) IRQ Vector Address Bits" group.long 0x228++0x03 line.long 0x00 "IRQVA102,(Base Timer ch.2) IRQ Vector Address Bits" group.long 0x22C++0x03 line.long 0x00 "IRQVA103,(Base Timer ch.3) IRQ Vector Address Bits" group.long 0x230++0x03 line.long 0x00 "IRQVA104,(Base Timer ch.4) IRQ Vector Address Bits" group.long 0x234++0x03 line.long 0x00 "IRQVA105,(Base Timer ch.5) IRQ Vector Address Bits" group.long 0x238++0x03 line.long 0x00 "IRQVA106,(Base Timer ch.6) IRQ Vector Address Bits" group.long 0x23C++0x03 line.long 0x00 "IRQVA107,(Base Timer ch.7) IRQ Vector Address Bits" group.long 0x240++0x03 line.long 0x00 "IRQVA108,(Base Timer ch.12/20/21/22/23) IRQ Vector Address Bits" group.long 0x244++0x03 line.long 0x00 "IRQVA109,(Base Timer ch.13) IRQ Vector Address Bits" group.long 0x248++0x03 line.long 0x00 "IRQVA110,(Base Timer ch.14) IRQ Vector Address Bits" group.long 0x24C++0x03 line.long 0x00 "IRQVA111,(Base Timer ch.15) IRQ Vector Address Bits" group.long 0x250++0x03 line.long 0x00 "IRQVA112,(Base Timer ch.16) IRQ Vector Address Bits" group.long 0x254++0x03 line.long 0x00 "IRQVA113,(Base Timer ch.17) IRQ Vector Address Bits" group.long 0x258++0x03 line.long 0x00 "IRQVA114,(Base Timer ch.18) IRQ Vector Address Bits" group.long 0x25C++0x03 line.long 0x00 "IRQVA115,(Base Timer ch.19) IRQ Vector Address Bits" group.long 0x260++0x03 line.long 0x00 "IRQVA116,(Base Timer ch.24) IRQ Vector Address Bits" group.long 0x264++0x03 line.long 0x00 "IRQVA117,(Base Timer ch.25) IRQ Vector Address Bits" group.long 0x268++0x03 line.long 0x00 "IRQVA118,(Base Timer ch.26) IRQ Vector Address Bits" group.long 0x26C++0x03 line.long 0x00 "IRQVA119,(Base Timer ch.27) IRQ Vector Address Bits" group.long 0x270++0x03 line.long 0x00 "IRQVA120,(Base Timer ch.28) IRQ Vector Address Bits" group.long 0x274++0x03 line.long 0x00 "IRQVA121,(Base Timer ch.29) IRQ Vector Address Bits" group.long 0x278++0x03 line.long 0x00 "IRQVA122,(Base Timer ch.30) IRQ Vector Address Bits" group.long 0x27C++0x03 line.long 0x00 "IRQVA123,(Base Timer ch.31) IRQ Vector Address Bits" group.long 0x2D0++0x03 line.long 0x00 "IRQVA144,(Reload Timer ch.0) IRQ Vector Address Bits" group.long 0x2D4++0x03 line.long 0x00 "IRQVA145,(Reload Timer ch.1) IRQ Vector Address Bits" group.long 0x2D8++0x03 line.long 0x00 "IRQVA146,(Reload Timer ch.2) IRQ Vector Address Bits" group.long 0x2DC++0x03 line.long 0x00 "IRQVA147,(Reload Timer ch.3) IRQ Vector Address Bits" group.long 0x2E0++0x03 line.long 0x00 "IRQVA148,(Reload Timer ch.16) IRQ Vector Address Bits" group.long 0x2E4++0x03 line.long 0x00 "IRQVA149,(Reload Timer ch.17) IRQ Vector Address Bits" group.long 0x2E8++0x03 line.long 0x00 "IRQVA150,(FRT ch.0) IRQ Vector Address Bits" group.long 0x2EC++0x03 line.long 0x00 "IRQVA151,(FRT ch.1) IRQ Vector Address Bits" group.long 0x2F0++0x03 line.long 0x00 "IRQVA152,(FRT ch.2) IRQ Vector Address Bits" group.long 0x2F4++0x03 line.long 0x00 "IRQVA153,(FRT ch.3) IRQ Vector Address Bits" group.long 0x2F8++0x03 line.long 0x00 "IRQVA154,(FRT ch.4) IRQ Vector Address Bits" group.long 0x300++0x13 line.long 0x00 "IRQVA156,(FRT ch.8)) IRQ Vector Address Bits" line.long 0x04 "IRQVA157,(FRT ch.9)) IRQ Vector Address Bits" line.long 0x08 "IRQVA158,(FRT ch.10)) IRQ Vector Address Bits" line.long 0x0C "IRQVA159,(PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE)) IRQ Vector Address Bits" line.long 0x10 "IRQVA160,(PCMPWM_DREQ)) IRQ Vector Address Bits" group.long 0x318++0x3B line.long 0x00 "IRQVA162,(IRQ0 of input capture 0 (ch.0)) IRQ Vector Address Bits" line.long 0x04 "IRQVA163,(IRQ0 of input capture 1 (ch.2)) IRQ Vector Address Bits" line.long 0x08 "IRQVA164,(IRQ0 of input capture 2 (ch.4)) IRQ Vector Address Bits" line.long 0x0C "IRQVA165,(IRQ0 of input capture 8 (ch.16)) IRQ Vector Address Bits" line.long 0x10 "IRQVA166,(IRQ0 of input capture 9 (ch.18)) IRQ Vector Address Bits" line.long 0x14 "IRQVA167,(IRQ0 of input capture 10 (ch.20)) IRQ Vector Address Bits" line.long 0x18 "IRQVA168,(IRQ1 of input capture 0 (ch.1)) IRQ Vector Address Bits" line.long 0x1C "IRQVA169,(IRQ1 of input capture 1 (ch.3)) IRQ Vector Address Bits" line.long 0x20 "IRQVA170,(IRQ1 of input capture 2 (ch.5)) IRQ Vector Address Bits" line.long 0x24 "IRQVA171,(IRQ1 of input capture 8 (ch.17)) IRQ Vector Address Bits" line.long 0x28 "IRQVA172,(IRQ1 of input capture 9 (ch.19)) IRQ Vector Address Bits" line.long 0x2C "IRQVA173,(IRQ1 of input capture 10 (ch.21)) IRQ Vector Address Bits" line.long 0x30 "IRQVA174,(IRQ0 of output compare 0 (ch.0)) IRQ Vector Address Bits" line.long 0x34 "IRQVA175,(IRQ0 of output compare 1 (ch.2)) IRQ Vector Address Bits" line.long 0x38 "IRQVA176,(IRQ0 of output compare 2 (ch.4)) IRQ Vector Address Bits" group.long 0x358++0x17 line.long 0x00 "IRQVA178,(IRQ0 of output compare 8 (ch.16)) IRQ Vector Address Bits" line.long 0x04 "IRQVA179,(IRQ0 of output compare 9 (ch.18)) IRQ Vector Address Bits" line.long 0x08 "IRQVA180,(IRQ0 of output compare 10 (ch.20)) IRQ Vector Address Bits" line.long 0x0C "IRQVA181,(IRQ1 of output compare 0 (ch.1)) IRQ Vector Address Bits" line.long 0x10 "IRQVA182,(IRQ1 of output compare 1 (ch.3)) IRQ Vector Address Bits" line.long 0x14 "IRQVA183,(IRQ1 of output compare 2 (ch.5)) IRQ Vector Address Bits" group.long 0x374++0x13 line.long 0x00 "IRQVA185,(IRQ1 of output compare 8 (ch.17)) IRQ Vector Address Bits" line.long 0x04 "IRQVA186,(IRQ1 of output compare 9 (ch.19)) IRQ Vector Address Bits" line.long 0x08 "IRQVA187,(IRQ1 of output compare 10 (ch.21)) IRQ Vector Address Bits" line.long 0x0C "IRQVA188,(QPRC ch.8) IRQ Vector Address Bits" line.long 0x10 "IRQVA189,(QPRC ch.9) IRQ Vector Address Bits" group.long 0x398++0x13 line.long 0x00 "IRQVA194,(ADC12B0 conversion done) IRQ Vector Address Bits" line.long 0x04 "IRQVA195,(ADC12B0 group interrupt) IRQ Vector Address Bits" line.long 0x08 "IRQVA196,(ADC12B0 pulse detection function) IRQ Vector Address Bits" line.long 0x0C "IRQVA197,(ADC12B0 RCO) IRQ Vector Address Bits" line.long 0x10 "IRQVA198,(DMA Error) IRQ Vector Address Bits" group.long 0x3AC++0x03 line.long 0x00 "IRQVA199,(DMAC Completion ch.0" group.long 0x3B0++0x03 line.long 0x00 "IRQVA200,(DMAC Completion ch.1" group.long 0x3B4++0x03 line.long 0x00 "IRQVA201,(DMAC Completion ch.2" group.long 0x3B8++0x03 line.long 0x00 "IRQVA202,(DMAC Completion ch.3" group.long 0x3BC++0x03 line.long 0x00 "IRQVA203,(DMAC Completion ch.4" group.long 0x3C0++0x03 line.long 0x00 "IRQVA204,(DMAC Completion ch.5" group.long 0x3C4++0x03 line.long 0x00 "IRQVA205,(DMAC Completion ch.6" group.long 0x3C8++0x03 line.long 0x00 "IRQVA206,(DMAC Completion ch.7" group.long 0x3CC++0x03 line.long 0x00 "IRQVA207,(DMAC Completion ch.8" group.long 0x3D0++0x03 line.long 0x00 "IRQVA208,(DMAC Completion ch.9" group.long 0x3D4++0x03 line.long 0x00 "IRQVA209,(DMAC Completion ch.10" group.long 0x3D8++0x03 line.long 0x00 "IRQVA210,(DMAC Completion ch.11" group.long 0x3DC++0x03 line.long 0x00 "IRQVA211,(DMAC Completion ch.12" group.long 0x3E0++0x03 line.long 0x00 "IRQVA212,(DMAC Completion ch.13" group.long 0x3E4++0x03 line.long 0x00 "IRQVA213,(DMAC Completion ch.14" group.long 0x3E8++0x03 line.long 0x00 "IRQVA214,(DMAC Completion ch.15" group.long 0x3EC++0x1B line.long 0x00 "IRQVA215,(DMAC RLT (ch.0,1,2,3 OR-ed)) IRQ Vector Address Bits" line.long 0x04 "IRQVA216,(SCT RC) IRQ) IRQ Vector Address Bits" line.long 0x08 "IRQVA217,(SCT SRC) IRQ) IRQ Vector Address Bits" line.long 0x0C "IRQVA218,(SCT Main OSC) IRQ) IRQ Vector Address Bits" line.long 0x10 "IRQVA219,(SCT Sub OSC) IRQ) IRQ Vector Address Bits" line.long 0x14 "IRQVA220,(CR5 performance monitor unit) IRQ) IRQ Vector Address Bits" line.long 0x18 "IRQVA221,(PRGCRC) IRQ Vector Address Bits" group.long 0x408++0x03 line.long 0x00 "IRQVA222,(MFS ch.0 Error) IRQ Vector Address Bits" group.long 0x40C++0x03 line.long 0x00 "IRQVA223,(MFS ch.1 Error) IRQ Vector Address Bits" group.long 0x410++0x03 line.long 0x00 "IRQVA224,(MFS ch.2 Error) IRQ Vector Address Bits" group.long 0x414++0x03 line.long 0x00 "IRQVA225,(MFS ch.3 Error) IRQ Vector Address Bits" group.long 0x418++0x03 line.long 0x00 "IRQVA226,(MFS ch.4 Error) IRQ Vector Address Bits" group.long 0x41C++0x03 line.long 0x00 "IRQVA227,(MFS ch.5 Error) IRQ Vector Address Bits" group.long 0x420++0x03 line.long 0x00 "IRQVA228,(MFS ch.6 Error) IRQ Vector Address Bits" group.long 0x424++0x03 line.long 0x00 "IRQVA229,(MFS ch.7 Error) IRQ Vector Address Bits" group.long 0x428++0x03 line.long 0x00 "IRQVA230,(MFS ch.8 Error) IRQ Vector Address Bits" group.long 0x42C++0x03 line.long 0x00 "IRQVA231,(MFS ch.9 Error) IRQ Vector Address Bits" group.long 0x430++0x03 line.long 0x00 "IRQVA232,(MFS ch.10 Error) IRQ Vector Address Bits" group.long 0x434++0x03 line.long 0x00 "IRQVA233,(MFS ch.11 Error) IRQ Vector Address Bits" group.long 0x440++0x4B line.long 0x00 "IRQVA236,(I2S0_IRQ) IRQ Vector Address Bits" line.long 0x04 "IRQVA237,(I2S1_IRQ) IRQ Vector Address Bits" line.long 0x08 "IRQVA238,(WG_AHB_ERR_IRQ) IRQ Vector Address Bits" line.long 0x0C "IRQVA239,(WG_END_IRQ0) IRQ Vector Address Bits" line.long 0x10 "IRQVA240,(WG_END_IRQ1) IRQ Vector Address Bits" line.long 0x14 "IRQVA241,(WG_END_IRQ2) IRQ Vector Address Bits" line.long 0x18 "IRQVA242,(WG_END_IRQ3) IRQ Vector Address Bits" line.long 0x1C "IRQVA243,(WG_END_IRQ4) IRQ Vector Address Bits" line.long 0x20 "IRQVA244,(MX_AHB_ERR_IRQ)) IRQ Vector Address Bits" line.long 0x24 "IRQVA245,(MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) IRQ Vector Address Bits" line.long 0x28 "IRQVA246,(MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) IRQ Vector Address Bits" line.long 0x2C "IRQVA247,(MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) IRQ Vector Address Bits" line.long 0x30 "IRQVA248,(MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) IRQ Vector Address Bits" line.long 0x34 "IRQVA249,(MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) IRQ Vector Address Bits" line.long 0x38 "IRQVA250,(MX_DATA_REQ_IRQ0) IRQ Vector Address Bits" line.long 0x3C "IRQVA251,(MX_DATA_REQ_IRQ1) IRQ Vector Address Bits" line.long 0x40 "IRQVA252,(MX_DATA_REQ_IRQ2) IRQ Vector Address Bits" line.long 0x44 "IRQVA253,(MX_DATA_REQ_IRQ3) IRQ Vector Address Bits" line.long 0x48 "IRQVA254,(MX_DATA_REQ_IRQ4) IRQ Vector Address Bits" tree.end tree "NMI Priority Level Registers" group.long 0x890++0x17 line.long 0x00 "NMIPL0,NMI Priority Level Register" bitfld.long 0x00 0.--3. " NMIPL0 ,(NMIX pin(Ext-IRC)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "NMIPL1,NMI Priority Level Register" bitfld.long 0x04 24.--27. " NMIPL7 ,(SW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " NMIPL6 ,(HW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " NMIPL5 ,(CSV Profile) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " NMIPL4 ,(LVDs IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "NMIPL2,NMI Priority Level Register" bitfld.long 0x08 8.--11. " NMIPL9 ,(Expand PLL CSV(OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " NMIPL8 ,(IRC 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "NMIPL3,NMI Priority Level Register" bitfld.long 0x0C 24.--27. " NMIPL15 ,(SHE MPU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " NMIPL13 ,(DMAC MPU #0 protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " NMIPL12 ,(CAN-FD RAMs 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "NMIPL4,NMI Priority Level Register" bitfld.long 0x10 16.--19. " NMIPL18 ,(TPU protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "NMIPL5,NMI Priority Level Register" bitfld.long 0x14 0.--3. " NMIPL20 ,(LCDBUS MPU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "IRQ Priority Level Registers" group.long 0x8B0++0x03 line.long 0x00 "IRQPL0,IRQ Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (SW-WDT Pre-warning) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (HW-WDT Pre-warning) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (System control status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8B8++0x73 line.long 0x00 "IRQPL2,IRQ Priority Level Register" bitfld.long 0x00 16.--20. " IRQPL10 ,IRQ10 (Work FLASH single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL8 ,IRQ8 (TCFLASH single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL3,IRQ Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL15 ,IRQ15 (CAN FD RAM(ch.0 to ch.3) single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL14 ,IRQ14 (System SRAM single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL4,IRQ Priority Level Register" bitfld.long 0x08 0.--4. " IRQPL16 ,IRQ16 (IRC vector address RAM single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL5,IRQ Priority Level Register" bitfld.long 0x0C 0.--4. " IRQPL20 ,IRQ20 (Work FLASH (RDY interrupt request)/(write completion)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL6,IRQ Priority Level Register" bitfld.long 0x10 24.--28. " IRQPL27 ,IRQ27 (External interrupt request ch.3/ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--20. " IRQPL26 ,IRQ26 (External interrupt request ch.2/ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " IRQPL25 ,IRQ25 (External interrupt request ch.1/ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " IRQPL24 ,IRQ24 (External interrupt request ch.0/ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IRQPL7,IRQ Priority Level Register" bitfld.long 0x14 24.--28. " IRQPL31 ,IRQ31 (External interrupt request ch.7/ch.23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " IRQPL30 ,IRQ30 (External interrupt request ch.6/ch.22) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " IRQPL29 ,IRQ29 (External interrupt request ch.5/ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " IRQPL28 ,IRQ28 (External interrupt request ch.4/ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IRQPL8,IRQ Priority Level Register" bitfld.long 0x18 24.--28. " IRQPL35 ,IRQ35 (External interrupt request ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " IRQPL34 ,IRQ34 (External interrupt request ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 8.--12. " IRQPL33 ,IRQ33 (External interrupt request ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " IRQPL32 ,IRQ32 (External interrupt request ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "IRQPL9,IRQ Priority Level Register" bitfld.long 0x1C 24.--28. " IRQPL39 ,IRQ39 (External interrupt request ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--20. " IRQPL38 ,IRQ38 (External interrupt request ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 8.--12. " IRQPL37 ,IRQ37 (External interrupt request ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 0.--4. " IRQPL36 ,IRQ36 (External interrupt request ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "IRQPL10,IRQ Priority Level Register" bitfld.long 0x20 24.--28. " IRQPL43 ,IRQ43 (CAN FD ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " IRQPL42 ,IRQ42 (CAN FD ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 8.--12. " IRQPL41 ,IRQ41 (CAN FD ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " IRQPL40 ,IRQ40 (CAN FD ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "IRQPL11,IRQ Priority Level Register" bitfld.long 0x24 24.--28. " IRQPL47 ,IRQ47 (MFS TX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 16.--20. " IRQPL46 ,IRQ46 (MFS RX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "IRQPL12,IRQ Priority Level Register" bitfld.long 0x28 24.--28. " IRQPL51 ,IRQ51 (MFS TX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 16.--20. " IRQPL50 ,IRQ50 (MFS RX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " IRQPL49 ,IRQ49 (MFS TX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 0.--4. " IRQPL48 ,IRQ48 (MFS RX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "IRQPL13,IRQ Priority Level Register" bitfld.long 0x2C 24.--28. " IRQPL55 ,IRQ55 (MFS TX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 16.--20. " IRQPL54 ,IRQ54 (MFS RX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 8.--12. " IRQPL53 ,IRQ53 (MFS TX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 0.--4. " IRQPL52 ,IRQ52 (MFS RX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "IRQPL14,IRQ Priority Level Register" bitfld.long 0x30 24.--28. " IRQPL59 ,IRQ59 (MFS TX ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 16.--20. " IRQPL58 ,IRQ58 (MFS RX ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 8.--12. " IRQPL57 ,IRQ57 (MFS TX ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 0.--4. " IRQPL56 ,IRQ56 (MFS RX ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "IRQPL15,IRQ Priority Level Register" bitfld.long 0x34 24.--28. " IRQPL63 ,IRQ63 (MFS TX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 16.--20. " IRQPL62 ,IRQ62 (MFS RX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 8.--12. " IRQPL61 ,IRQ61 (MFS TX ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 0.--4. " IRQPL60 ,IRQ60 (MFS RX ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "IRQPL16,IRQ Priority Level Register" bitfld.long 0x38 24.--28. " IRQPL67 ,IRQ67 (MFS TX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 16.--20. " IRQPL66 ,IRQ66 (MFS RX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 8.--12. " IRQPL65 ,IRQ65 (MFS TX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 0.--4. " IRQPL64 ,IRQ64 (MFS RX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "IRQPL17,IRQ Priority Level Register" bitfld.long 0x3C 8.--12. " IRQPL69 ,IRQ68 (MFS TX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 0.--4. " IRQPL68 ,IRQ68 (MFS RX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "IRQPL18,IRQ Priority Level Register" bitfld.long 0x40 24.--28. " IRQPL75 ,IRQ75 (SMC ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x40 16.--20. " IRQPL74 ,IRQ74 (SMC ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "IRQPL19,IRQ Priority Level Register" bitfld.long 0x44 24.--28. " IRQPL79 ,IRQ79 (SMC ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x44 16.--20. " IRQPL78 ,IRQ78 (SMC ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x44 8.--12. " IRQPL77 ,IRQ77 (SMC ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x44 0.--4. " IRQPL76 ,IRQ76 (SMC ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "IRQPL20,IRQ Priority Level Register" bitfld.long 0x48 24.--28. " IRQPL83 ,IRQ83 (SG ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x48 16.--20. " IRQPL82 ,IRQ82 (SG ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x48 8.--12. " IRQPL81 ,IRQ81 (SG ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x48 0.--4. " IRQPL80 ,IRQ80 (SG ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "IRQPL21,IRQ Priority Level Register" bitfld.long 0x4C 24.--28. " IRQPL87 ,IRQ87 (LCD Bus interface RxFifoInterrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x4C 16.--20. " IRQPL86 ,IRQ86 (LCD Bus interface InstrFifointerrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x4C 8.--12. " IRQPL85 ,IRQ85 (LCD Bus Interface Sequencer Sync/Error/Tearing Interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x4C 0.--4. " IRQPL84 ,IRQ84 (SG ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "IRQPL22,IRQ Priority Level Register" bitfld.long 0x50 24.--28. " IRQPL91 ,IRQ91 (SHE Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x50 16.--20. " IRQPL90 ,IRQ90 (Indicator PWM) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x50 8.--12. " IRQPL89 ,IRQ89 (LCD Bus interface WriteChannelDone) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x50 0.--4. " IRQPL88 ,IRQ88 (LCD Bus interface ReadChannelDone) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "IRQPL23,IRQ Priority Level Register" bitfld.long 0x54 24.--28. " IRQPL95 ,IRQ95 (TCRAM diag) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x54 16.--20. " IRQPL94 ,IRQ94 (DDR HSSPI TX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x54 8.--12. " IRQPL93 ,IRQ93 (DDR HSSPI RX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x54 0.--4. " IRQPL92 ,IRQ92 (SHE) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "IRQPL24,IRQ Priority Level Register" bitfld.long 0x58 24.--28. " IRQPL99 ,IRQ99 (CR calibration) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x58 16.--20. " IRQPL98 ,IRQ98 (RTC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x58 8.--12. " IRQPL97 ,IRQ97 (Global timer) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "IRQPL25,IRQ Priority Level Register" bitfld.long 0x5C 24.--28. " IRQPL103 ,IRQ103 (Base Timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x5C 16.--20. " IRQPL102 ,IRQ102 (Base Timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x5C 8.--12. " IRQPL101 ,IRQ101 (Base Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x5C 0.--4. " IRQPL100 ,IRQ100 (Base Timer ch.0/8/9/10/11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "IRQPL26,IRQ Priority Level Register" bitfld.long 0x60 24.--28. " IRQPL107 ,IRQ107 (Base Timer ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 16.--20. " IRQPL106 ,IRQ106 (Base Timer ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 8.--12. " IRQPL105 ,IRQ105 (Base Timer ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 0.--4. " IRQPL104 ,IRQ104 (Base Timer ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "IRQPL27,IRQ Priority Level Register" bitfld.long 0x64 24.--28. " IRQPL111 ,IRQ111 (Base Timer ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 16.--20. " IRQPL110 ,IRQ110 (Base Timer ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 8.--12. " IRQPL109 ,IRQ109 (Base Timer ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 0.--4. " IRQPL108 ,IRQ108 (Base Timer ch.12/20/21/22/23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "IRQPL28,IRQ Priority Level Register" bitfld.long 0x68 24.--28. " IRQPL115 ,IRQ115 (Base Timer ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x68 16.--20. " IRQPL114 ,IRQ114 (Base Timer ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x68 8.--12. " IRQPL113 ,IRQ113 (Base Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x68 0.--4. " IRQPL112 ,IRQ112 (Base Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "IRQPL29,IRQ Priority Level Register" bitfld.long 0x6C 24.--28. " IRQPL119 ,IRQ119 (Base Timer ch.27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x6C 16.--20. " IRQPL118 ,IRQ118 (Base Timer ch.26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x6C 8.--12. " IRQPL117 ,IRQ117 (Base Timer ch.25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x6C 0.--4. " IRQPL116 ,IRQ116 (Base Timer ch.24) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x70 "IRQPL30,IRQ Priority Level Register" bitfld.long 0x70 24.--28. " IRQPL123 ,IRQ123 (Base Timer ch.31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x70 16.--20. " IRQPL122 ,IRQ122 (Base Timer ch.30) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x70 8.--12. " IRQPL121 ,IRQ121 (Base Timer ch.29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x70 0.--4. " IRQPL120 ,IRQ120 (Base Timer ch.28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x940++0x6F line.long 0x00 "IRQPL36,IRQ Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL147 ,IRQ147 (Reload Timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL146 ,IRQ146 (Reload Timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL145 ,IRQ145 (Reload Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL144 ,IRQ144 (Reload Timer ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL37,IRQ Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL151 ,IRQ151 (FRT ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL150 ,IRQ150 (FRT ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " IRQPL149 ,IRQ149 (Reload Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL148 ,IRQ148 (Reload Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL38,IRQ Priority Level Register" bitfld.long 0x08 16.--20. " IRQPL154 ,IRQ154 (FRT ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " IRQPL153 ,IRQ153 (FRT ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " IRQPL152 ,IRQ152 (FRT ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL39,IRQ Priority Level Register" bitfld.long 0x0C 24.--28. " IRQPL159 ,IRQ159 (FRT PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " IRQPL158 ,IRQ158 (FRT ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " IRQPL157 ,IRQ157 (FRT ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0.--4. " IRQPL156 ,IRQ156 (FRT ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL40,IRQ Priority Level Register" bitfld.long 0x10 24.--28. " IRQPL163 ,IRQ163 (IRQ0 of input capture 1 (ch.2)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--20. " IRQPL162 ,IRQ162 (IRQ0 of ynput capture 0 (ch.0)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " IRQPL160 ,IRQ160 (PCMPWM_DREQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IRQPL41,IRQ Priority Level Register" bitfld.long 0x14 24.--28. " IRQPL167 ,IRQ167 (IRQ0 of input capture 10 (ch.20)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " IRQPL166 ,IRQ166 (IRQ0 of input capture 9 (ch.18)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " IRQPL165 ,IRQ165 (IRQ0 of input capture 8 (ch.16)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " IRQPL164 ,IRQ164 (IRQ0 of input capture 2 (ch.4)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IRQPL42,IRQ Priority Level Register" bitfld.long 0x18 24.--28. " IRQPL171 ,IRQ171 (IRQ1 of input capture 8 (ch.17)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " IRQPL170 ,IRQ170 (IRQ1 of input capture 2 (ch.5)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 8.--12. " IRQPL169 ,IRQ169 (IRQ1 of input capture 1 (ch.3)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " IRQPL168 ,IRQ168 (IRQ1 of input capture 0 (ch.1)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "IRQPL43,IRQ Priority Level Register" bitfld.long 0x1C 24.--28. " IRQPL175 ,IRQ175 (IRQ0 of output compare 1 (ch.2)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--20. " IRQPL174 ,IRQ174 (IRQ0 of output compare 0 (ch.0)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 8.--12. " IRQPL173 ,IRQ173 (IRQ1 of input capture 10 (ch.21)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 0.--4. " IRQPL172 ,IRQ172 (IRQ1 of input capture 9 (ch.19)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "IRQPL44,IRQ Priority Level Register" bitfld.long 0x20 24.--28. " IRQPL179 ,IRQ179 (IRQ0 of output compare 9 (ch.18)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " IRQPL178 ,IRQ178 (IRQ0 of output compare 8 (ch.16)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " IRQPL176 ,IRQ176 (IRQ0 of output compare 2 (ch.4)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "IRQPL45,IRQ Priority Level Register" bitfld.long 0x24 24.--28. " IRQPL183 ,IRQ183 (IRQ1 of output compare 2 (ch.5)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 16.--20. " IRQPL182 ,IRQ182 (IRQ1 of output compare 1 (ch.3)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 8.--12. " IRQPL181 ,IRQ181 (IRQ1 of output compare 0 (ch.1)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 0.--4. " IRQPL180 ,IRQ180 (IRQ0 of output compare 10 (ch.20)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "IRQPL46,IRQ Priority Level Register" bitfld.long 0x28 24.--28. " IRQPL187 ,IRQ187 (IRQ1 of output compare 10 (ch.21)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 16.--20. " IRQPL186 ,IRQ186 (IRQ1 of output compare 9 (ch.19)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " IRQPL185 ,IRQ185 (IRQ1 of output compare 8 (ch.17)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "IRQPL47,IRQ Priority Level Register" bitfld.long 0x2C 8.--12. " IRQPL189 ,IRQ189 (QPRC ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 0.--4. " IRQPL188 ,IRQ188 (QPRC ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "IRQPL48,IRQ Priority Level Register" bitfld.long 0x30 24.--28. " IRQPL195 ,IRQ195 (ADC12B0 Group interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 16.--20. " IRQPL194 ,IRQ194 (ADC12B0 Conversion Done) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "IRQPL49,IRQ Priority Level Register" bitfld.long 0x34 24.--28. " IRQPL199 ,IRQ183 (DMAC Completion ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 16.--20. " IRQPL198 ,IRQ182 (DMA Error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 8.--12. " IRQPL197 ,IRQ181 (ADC12B0 RCO) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 0.--4. " IRQPL196 ,IRQ196 (ADC12B0 pulse detection function) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "IRQPL50,IRQ Priority Level Register" bitfld.long 0x38 24.--28. " IRQPL203 ,IRQ203 (DMAC Completion ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 16.--20. " IRQPL202 ,IRQ202 (DMAC Completion ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 8.--12. " IRQPL201 ,IRQ201 (DMAC Completion ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 0.--4. " IRQPL200 ,IRQ200 (DMAC Completion ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x3C "IRQPL51,IRQ Priority Level Register" bitfld.long 0x3C 24.--28. " IRQPL207 ,IRQ207 (DMAC Completion ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 16.--20. " IRQPL206 ,IRQ206 (DMAC Completion ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 8.--12. " IRQPL205 ,IRQ205 (DMAC Completion ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x3C 0.--4. " IRQPL204 ,IRQ204 (DMAC Completion ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "IRQPL52,IRQ Priority Level Register" bitfld.long 0x40 24.--28. " IRQPL211 ,IRQ211 (DMAC Completion ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x40 16.--20. " IRQPL210 ,IRQ210 (DMAC Completion ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x40 8.--12. " IRQPL209 ,IRQ209 (DMAC Completion ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x40 0.--4. " IRQPL208 ,IRQ208 (DMAC Completion ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "IRQPL53,IRQ Priority Level Register" bitfld.long 0x44 24.--28. " IRQPL215 ,IRQ215 (DMAC RLT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x44 16.--20. " IRQPL214 ,IRQ214 (DMAC Completion ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x44 8.--12. " IRQPL213 ,IRQ213 (DMAC Completion ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x44 0.--4. " IRQPL212 ,IRQ212 (DMAC Completion ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "IRQPL54,IRQ Priority Level Register" bitfld.long 0x48 24.--28. " IRQPL219 ,IRQ219 (SCT Sub OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x48 16.--20. " IRQPL218 ,IRQ218 (SCT Main OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x48 8.--12. " IRQPL217 ,IRQ217 (SCT SRC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x48 0.--4. " IRQPL216 ,IRQ216 (SCT RC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x4C "IRQPL55,IRQ Priority Level Register" bitfld.long 0x4C 24.--28. " IRQPL223 ,IRQ223 (MFS ch.1 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x4C 16.--20. " IRQPL222 ,IRQ222 (MFS ch.0 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x4C 8.--12. " IRQPL221 ,IRQ221 (PRGCRC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x4C 0.--4. " IRQPL220 ,IRQ220 (CR5 Performance Monitor Unit IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x50 "IRQPL56,IRQ Priority Level Register" bitfld.long 0x50 24.--28. " IRQPL227 ,IRQ227 (MFS ch.5 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x50 16.--20. " IRQPL226 ,IRQ226 (MFS ch.4 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x50 8.--12. " IRQPL225 ,IRQ225 (MFS ch.3 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x50 0.--4. " IRQPL224 ,IRQ224 (MFS ch.2 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x54 "IRQPL57,IRQ Priority Level Register" bitfld.long 0x54 24.--28. " IRQPL231 ,IRQ231 (MFS ch.9 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x54 16.--20. " IRQPL230 ,IRQ230 (MFS ch.8 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x54 8.--12. " IRQPL229 ,IRQ229 (MFS ch.7 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x54 0.--4. " IRQPL228 ,IRQ228 (MFS ch.6 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x58 "IRQPL58,IRQ Priority Level Register" bitfld.long 0x58 8.--12. " IRQPL233 ,IRQ233 (MFS ch.11 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x58 0.--4. " IRQPL232 ,IRQ232 (MFS ch.10 Error (Tx/Rx error, Status OR-ed)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x5C "IRQPL59,IRQ Priority Level Register" bitfld.long 0x5C 24.--28. " IRQPL239 ,IRQ239 (WG_END_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x5C 16.--20. " IRQPL238 ,IRQ238 (WG_AHB_ERR_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x5C 8.--12. " IRQPL237 ,IRQ237 (I2S1_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x5C 0.--4. " IRQPL236 ,IRQ236 (I2S0_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x60 "IRQPL60,IRQ Priority Level Register" bitfld.long 0x60 24.--28. " IRQPL243 ,IRQ243 (WG_END_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 16.--20. " IRQPL242 ,IRQ242 (WG_END_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 8.--12. " IRQPL241 ,IRQ241 (WG_END_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 0.--4. " IRQPL240 ,IRQ240 (WG_END_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x64 "IRQPL61,IRQ Priority Level Register" bitfld.long 0x64 24.--28. " IRQPL247 ,IRQ247 (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 16.--20. " IRQPL246 ,IRQ246 (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 8.--12. " IRQPL245 ,IRQ245 (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x64 0.--4. " IRQPL244 ,IRQ244 (MX_AHB_ERR_IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x68 "IRQPL62,IRQ Priority Level Register" bitfld.long 0x68 24.--28. " IRQPL251 ,IRQ251 (MX_DATA_REQ_IRQ1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x68 16.--20. " IRQPL250 ,IRQ250 (MX_DATA_REQ_IRQ0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x68 8.--12. " IRQPL249 ,IRQ249 (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x68 0.--4. " IRQPL248 ,IRQ248 (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x6C "IRQPL63,IRQ Priority Level Register" bitfld.long 0x6C 16.--20. " IRQPL254 ,IRQ254 (MX_DMA_REQ_IRQ4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x6C 8.--12. " IRQPL253 ,IRQ253 (MX_DMA_REQ_IRQ3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x6C 0.--4. " IRQPL252 ,IRQ252 (MX_DMA_REQ_IRQ2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end newline width 16. group.long 0xAB8++0x03 line.long 0x00 "NMISIS_SET/CLR,IRC NMI Software Interrupt Status Register" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " NMISIS[20] ,NMI20 (LCDBUS MPU) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS[18] ,NMI18 (TPU protection violation) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 15. -0x08 15. -0x04 15. " NMISIS[15] ,NMI15 (SHE MPU) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NMISIS[13] ,NMI13 (DMAC MPU #0 protection violation) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 12. -0x08 12. -0x04 12. " NMISIS[12] ,NMI12 (CAN-FD RAMs 2-bit ECC error detection) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x08 09. -0x04 09. " NMISIS[9] ,NMI9 (Expand PLL CSV(OR-ed of all factors)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x08 08. -0x04 08. " NMISIS[8] ,NMI8 (IRC 2-bit ECC err detection) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x08 07. -0x04 07. " NMISIS[7] ,NMI7 (SW-WDT) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 06. -0x08 06. -0x04 06. " NMISIS[6] ,NMI6 (HW-WDT) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x08 05. -0x04 05. " NMISIS[5] ,NMI5 (CSV, Profile) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x08 04. -0x04 04. " NMISIS[4] ,NMI4 (LVDs IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x08 01. -0x04 00. " NMISIS[0] ,NMI0 (NMIX pin(Ext-IRC)) software interrupt status bit" "No interrupt,Interrupt" width 18. tree "IRC IRQ Software Interrupt Status Registers" group.long 0xB40++0x1F line.long 0x00 "IRQSIS0_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[31] ,IRQ (External interrupt request ch.7/ch.23) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQSIS[30] ,IRQ (External interrupt request ch.6/ch.22) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQSIS[29] ,IRQ (External interrupt request ch.5/ch.21) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQSIS[28] ,IRQ (External interrupt request ch.4/ch.20) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQSIS[27] ,IRQ (External interrupt request ch.3/ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQSIS[26] ,IRQ (External interrupt request ch.2/ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQSIS[25] ,IRQ (External interrupt request ch.1/ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQSIS[24] ,IRQ (External interrupt request ch.0/ch.16) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQSIS[20] ,IRQ (Work FLASH (RDY interrupt request)/(write completion)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQSIS[16] ,IRQ (IRC vector address RAM single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 15. -0x80 15. -0x40 15. " IRQSIS[15] ,IRQ (CAN FD RAM(ch.0 to ch.3) single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQSIS[14] ,IRQ (System SRAM Single Bit Error) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQSIS[10] ,IRQ (Work FLASH single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQSIS[8] ,IRQ (TCFLASH single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQSIS[3] ,IRQ (SW-WDT pre-warning) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQSIS[2] ,IRQ (HW-WDT pre-warning) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQSIS[1] ,IRQ (System control status) software interrupt status bit" "No interrupt,Interrupt" line.long 0x04 "IRQSIS1_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x04 31. -0x7C 31. -0x3C 31. " IRQSIS[63] ,IRQ (MFS RX ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 30. -0x7C 30. -0x3C 30. " IRQSIS[62] ,IRQ (MFS TX ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 29. -0x7C 29. -0x3C 29. " IRQSIS[61] ,IRQ (MFS RX ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 28. -0x7C 28. -0x3C 28. " IRQSIS[60] ,IRQ (MFS TX ch.7) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 27. -0x7C 27. -0x3C 27. " IRQSIS[59] ,IRQ (MFS RX ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 26. -0x7C 26. -0x3C 26. " IRQSIS[58] ,IRQ (MFS RX ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 25. -0x7C 25. -0x3C 25. " IRQSIS[57] ,IRQ (MFS TX ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQSIS[56] ,IRQ (MFS RX ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 23. -0x7C 23. -0x3C 23. " IRQSIS[55] ,IRQ (MFS TX ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 22. -0x7C 22. -0x3C 22. " IRQSIS[54] ,IRQ (MFS RX ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 21. -0x7C 21. -0x3C 21. " IRQSIS[53] ,IRQ (MFS TX ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 20. -0x7C 20. -0x3C 20. " IRQSIS[52] ,IRQ (MFS RX ch.3) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 19. -0x7C 19. -0x3C 19. " IRQSIS[51] ,IRQ (MFS TX ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 18. -0x7C 18. -0x3C 18. " IRQSIS[50] ,IRQ (MFS RX ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 17. -0x7C 17. -0x3C 17. " IRQSIS[49] ,IRQ (MFS TX ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 16. -0x7C 16. -0x3C 16. " IRQSIS[48] ,IRQ (MFS RX ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 15. -0x7C 15. -0x3C 15. " IRQSIS[47] ,IRQ (MFS TX ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 14. -0x7C 14. -0x3C 14. " IRQSIS[46] ,IRQ (MFS RX ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 11. -0x7C 11. -0x3C 11. " IRQSIS[43] ,IRQ (CAN FD ch.3 (OR-ed of all factors)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 10. -0x7C 10. -0x3C 10. " IRQSIS[42] ,IRQ (CAN FD ch.2 (OR-ed of all factors)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 09. -0x7C 09. -0x3C 09. " IRQSIS[41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 08. -0x7C 08. -0x3C 08. " IRQSIS[40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 07. -0x7C 07. -0x3C 07. " IRQSIS[39] ,IRQ (External interrupt request ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 06. -0x7C 06. -0x3C 06. " IRQSIS[38] ,IRQ (External interrupt request ch.14) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 05. -0x7C 05. -0x3C 05. " IRQSIS[37] ,IRQ (External interrupt request ch.13) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 04. -0x7C 04. -0x3C 04. " IRQSIS[36] ,IRQ (External interrupt request ch.12) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 03. -0x7C 03. -0x3C 03. " IRQSIS[35] ,IRQ (External interrupt request ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 02. -0x7C 02. -0x3C 02. " IRQSIS[34] ,IRQ (External interrupt request ch.10) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 01. -0x7C 01. -0x3C 01. " IRQSIS[33] ,IRQ (External interrupt request ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 00. -0x7C 00. -0x3C 00. " IRQSIS[32] ,IRQ (External interrupt request ch.8) software interrupt status bit" "No interrupt,Interrupt" line.long 0x08 "IRQSIS2_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQSIS[95] ,IRQ (TCRAM diag) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 30. -0x78 30. -0x38 30. " IRQSIS[94] ,IRQ (DDR HSSPI TX) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 29. -0x78 29. -0x38 29. " IRQSIS[93] ,IRQ (DDR HSSPI RX) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 28. -0x78 28. -0x38 28. " IRQSIS[92] ,IRQ (SHE) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQSIS[91] ,IRQ (SHE error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 26. -0x78 26. -0x38 26. " IRQSIS[90] ,IRQ (Indicator PWM) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 25. -0x78 25. -0x38 25. " IRQSIS[89] ,IRQ (LCD bus interface WriteChannelDone) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 24. -0x78 24. -0x38 24. " IRQSIS[88] ,IRQ (LCD bus interface ReadChannelDone) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 23. -0x78 23. -0x38 23. " IRQSIS[87] ,IRQ (LCD bus interface RxFifoInterrupt status bits" "No interrupt,Interrupt" setclrfld.long 0x08 22. -0x78 22. -0x38 22. " IRQSIS[86] ,IRQ (LCD bus interface InstrFifointerrupt) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 21. -0x78 21. -0x38 21. " IRQSIS[85] ,IRQ (LCD bus Interface Sequencer Sync/ Error/Tearing Interrupt) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 20. -0x78 20. -0x38 20. " IRQSIS[84] ,IRQ (SG ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 19. -0x78 19. -0x38 19. " IRQSIS[83] ,IRQ (SG ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 18. -0x78 18. -0x38 18. " IRQSIS[82] ,IRQ (SG ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 17. -0x78 17. -0x38 17. " IRQSIS[81] ,IRQ (SG ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 16. -0x78 16. -0x38 16. " IRQSIS[80] ,IRQ (SG ch.0) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 15. -0x78 15. -0x38 15. " IRQSIS[79] ,IRQ (SMC ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 14. -0x78 14. -0x38 14. " IRQSIS[78] ,IRQ (SMC ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 13. -0x78 13. -0x38 13. " IRQSIS[77] ,IRQ (SMC ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 12. -0x78 12. -0x38 12. " IRQSIS[76] ,IRQ (SMC ch.2) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 11. -0x78 11. -0x38 11. " IRQSIS[75] ,IRQ (SMC ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 10. -0x78 10. -0x38 10. " IRQSIS[74] ,IRQ (SMC ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 05. -0x78 05. -0x38 05. " IRQSIS[69] ,IRQ (MFS TX ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 04. -0x78 04. -0x38 04. " IRQSIS[68] ,IRQ (MFS RX ch.11) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 03. -0x78 03. -0x38 03. " IRQSIS[67] ,IRQ (MFS TX ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 02. -0x78 02. -0x38 02. " IRQSIS[66] ,IRQ (MFS RX ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 01. -0x78 01. -0x38 01. " IRQSIS[65] ,IRQ (MFS TX ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 00. -0x78 00. -0x38 00. " IRQSIS[64] ,IRQ (MFS RX ch.9) software interrupt status bit" "No interrupt,Interrupt" line.long 0x0C "IRQSIS3_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x0C 27. -0x74 27. -0x34 27. " IRQSIS[123] ,IRQ (Base timer ch.31) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " IRQSIS[122] ,IRQ (Base timer ch.30) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " IRQSIS[121] ,IRQ (Base timer ch.29) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " IRQSIS[120] ,IRQ (Base timer ch.28) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " IRQSIS[119] ,IRQBase timer ch.27) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " IRQSIS[118] ,IRQ (Base timer ch.26) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQSIS[117] ,IRQ (Base timer ch.25) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " IRQSIS[116] ,IRQ (Base timer ch.24) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 19. -0x74 19. -0x34 19. " IRQSIS[115] ,IRQ (Base timer ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " IRQSIS[114] ,IRQ (Base timer ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " IRQSIS[113] ,IRQ (Base timer ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " IRQSIS[112] ,IRQ (Base timer ch.16) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 15. -0x74 15. -0x34 15. " IRQSIS[111] ,IRQ (Base timer ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQSIS[110] ,IRQ (Base timer ch.14) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 13. -0x74 13. -0x34 13. " IRQSIS[109] ,IRQ (Base timer ch.13) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 12. -0x74 12. -0x34 12. " IRQSIS[108] ,IRQ (Base timer ch.12/20/21/22/23) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 11. -0x74 11. -0x34 11. " IRQSIS[107] ,IRQ (Base timer ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 10. -0x74 10. -0x34 10. " IRQSIS[106] ,IRQ (Base timer ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 09. -0x74 09. -0x34 09. " IRQSIS[105] ,IRQ (Base timer ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 08. -0x74 08. -0x34 08. " IRQSIS[104] ,IRQ (Base timer ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 07. -0x74 07. -0x34 07. " IRQSIS[103] ,IRQ (Base timer ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 06. -0x74 06. -0x34 06. " IRQSIS[102] ,IRQ (Base timer ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 05. -0x74 05. -0x34 05. " IRQSIS[101] ,IRQ (Base timer ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 04. -0x74 04. -0x34 04. " IRQSIS[100] ,IRQ (Base timer ch.0/8/9/10/11) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 03. -0x74 03. -0x34 03. " IRQSIS[99] ,IRQ (CR CARIBRATION) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 02. -0x74 02. -0x34 02. " IRQSIS[98] ,IRQ (RTC) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 01. -0x74 01. -0x34 01. " IRQSIS[97] ,IRQ (Global timer (Compare clear interrupt)) software interrupt status bit" "No interrupt,Interrupt" line.long 0x10 "IRQSIS4_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQSIS[159] ,IRQ (PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 30. -0x70 30. -0x30 30. " IRQSIS[158] ,IRQ (FRT ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQSIS[157] ,IRQ (FRT ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 28. -0x70 28. -0x30 28. " IRQSIS[156] ,IRQ (FRT ch.8) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 26. -0x70 26. -0x30 26. " IRQSIS[154] ,IRQ (FRT ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQSIS[153] ,IRQ (FRT ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQSIS[152] ,IRQ (FRT ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 23. -0x70 23. -0x30 23. " IRQSIS[151] ,IRQ (FRT ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 22. -0x70 22. -0x30 22. " IRQSIS[150] ,IRQ (FRT ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 21. -0x70 21. -0x30 21. " IRQSIS[149] ,IRQ (Reload timer ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 20. -0x70 20. -0x30 20. " IRQSIS[148] ,IRQ (Reload timer ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 19. -0x70 19. -0x30 19. " IRQSIS[147] ,IRQ (Reload timer ch.3) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 18. -0x70 18. -0x30 18. " IRQSIS[146] ,IRQ (Reload timer ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 17. -0x70 17. -0x30 17. " IRQSIS[145] ,IRQ (Reload timer ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 16. -0x70 16. -0x30 16. " IRQSIS[144] ,IRQ (Reload timer ch.0) software interrupt status bit" "No interrupt,Interrupt" line.long 0x14 "IRQSIS5_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " IRQSIS[189] ,IRQ (QPRC ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " IRQSIS[188] ,IRQ (QPRC ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " IRQSIS[187] ,IRQ (IRQ1 of output compare 10 (ch.21)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " IRQSIS[186] ,IRQ1 of output compare 9 (ch.19)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " IRQSIS[185] ,IRQ (IRQ1 of output compare 8 (ch.17)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " IRQSIS[183] ,IRQ (IRQ1 of output compare 2 (ch.5)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " IRQSIS[182] ,IRQ (IRQ1 of output compare 1 (ch.3)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " IRQSIS[181] ,IRQ (IRQ1 of output compare 0 (ch.1)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQSIS[180] ,IRQ (IRQ0 of output compare 10 (ch.20)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQSIS[179] ,IRQ (IRQ0 of output compare 9 (ch.18)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQSIS[178] ,IRQ (IRQ0 of output compare 8 (ch.16)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQSIS[176] ,IRQ (IRQ0 of output compare 2 (ch.4)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " IRQSIS[175] ,IRQ (IRQ0 of output compare 1 (ch.2)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " IRQSIS[174] ,IRQ (IRQ0 of output compare 0 (ch.0)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " IRQSIS[173] ,IRQ (IRQ1 of input capture 10 (ch.21)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " IRQSIS[172] ,IRQ (IRQ1 of input capture 9 (ch.19)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " IRQSIS[171] ,IRQ (IRQ1 of input capture 8 (ch.17)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " IRQSIS[170] ,IRQ (IRQ1 of input capture 2 (ch.5)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 09. -0x6C 09. -0x2C 09. " IRQSIS[169] ,IRQ (IRQ1 of input capture 1 (ch.3)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 08. -0x6C 08. -0x2C 08. " IRQSIS[168] ,IRQ (IRQ1 of input capture 0 (ch.1)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 07. -0x6C 07. -0x2C 07. " IRQSIS[167] ,IRQ (IRQ0 of input capture 10 (ch.20)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 06. -0x6C 06. -0x2C 06. " IRQSIS[166] ,IRQ (IRQ0 of input capture 9 (ch.18)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 05. -0x6C 05. -0x2C 05. " IRQSIS[165] ,IRQ (IRQ0 of input capture 8 (ch.16)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 04. -0x6C 04. -0x2C 04. " IRQSIS[164] ,IRQ (IRQ0 of input capture 2 (ch.4)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 03. -0x6C 03. -0x2C 03. " IRQSIS[163] ,IRQ (IRQ0 of input capture 1 (ch.2)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 02. -0x6C 02. -0x2C 02. " IRQSIS[162] ,IRQ (IRQ0 of input capture 0 (ch.0)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 00. -0x6C 00. -0x2C 00. " IRQSIS[160] ,IRQ (PCMPWM_DREQ) software interrupt status bit" "No interrupt,Interrupt" line.long 0x18 "IRQSIS6_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x18 31. -0x68 31. -0x28 31. " IRQSIS[223] ,IRQ (MFS ch.1 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQSIS[222] ,IRQ (MFS ch.0 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 29. -0x68 29. -0x28 29. " IRQSIS[221] ,IRQ (PRGCRC) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 28. -0x68 28. -0x28 28. " IRQSIS[220] ,IRQ (CR5 Performance Monitor Unit IRQ) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 27. -0x68 27. -0x28 27. " IRQSIS[219] ,IRQ (SCT Sub OSC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 26. -0x68 26. -0x28 26. " IRQSIS[218] ,IRQ (SCT Main OSC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 25. -0x68 25. -0x28 25. " IRQSIS[217] ,IRQ (SCT SRC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 24. -0x68 24. -0x28 24. " IRQSIS[216] ,IRQ (SCT RC IRQ) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 23. -0x68 23. -0x28 23. " IRQSIS[215] ,IRQ (DMAC RLT (ch.0,1,2,3 OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 22. -0x68 22. -0x28 22. " IRQSIS[214] ,IRQ (DMAC completion ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 21. -0x68 21. -0x28 21. " IRQSIS[213] ,IRQ (DMAC completion ch.14) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQSIS[212] ,IRQ (DMAC completion ch.13) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 19. -0x68 19. -0x28 19. " IRQSIS[211] ,IRQ (DMAC completion ch.12) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 18. -0x68 18. -0x28 18. " IRQSIS[210] ,IRQ (DMAC completion ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 17. -0x68 17. -0x28 17. " IRQSIS[209] ,IRQ (DMAC completion ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 16. -0x68 16. -0x28 16. " IRQSIS[208] ,IRQ (DMAC completion ch.9) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 15. -0x68 15. -0x28 15. " IRQSIS[207] ,IRQ (DMAC completion ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 14. -0x68 14. -0x28 14. " IRQSIS[206] ,IRQ (DMAC completion ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQSIS[205] ,IRQ (DMAC completion ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 12. -0x68 12. -0x28 12. " IRQSIS[204] ,IRQ (DMAC completion ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 11. -0x68 11. -0x28 11. " IRQSIS[203] ,IRQ (DMAC completion ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 10. -0x68 10. -0x28 10. " IRQSIS[202] ,IRQ (DMAC completion ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 09. -0x68 09. -0x28 09. " IRQSIS[201] ,IRQ (DMAC completion ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 08. -0x68 08. -0x28 08. " IRQSIS[200] ,IRQ (DMAC completion ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 07. -0x68 07. -0x28 07. " IRQSIS[199] ,IRQ (DMAC completion ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 06. -0x68 06. -0x28 06. " IRQSIS[198] ,IRQ (DMA error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 05. -0x68 05. -0x28 05. " IRQSIS[197] ,IRQ (ADC12B0 RCO) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 04. -0x68 04. -0x28 04. " IRQSIS[196] ,IRQ (ADC12B0 pulse detection function) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 03. -0x68 03. -0x28 03. " IRQSIS[195] ,IRQ (ADC12B0 group interrupt) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 02. -0x68 02. -0x28 02. " IRQSIS[194] ,IRQ (ADC12B0 conversion done) software interrupt status bit" "No interrupt,Interrupt" line.long 0x1C "IRQSIS7_SET/CLR,IRC IRQ Software Interrupt Status Register" setclrfld.long 0x1C 30. -0x64 30. -0x24 30. " IRQSIS[254] ,IRQ (MX_DATA_REQ_IRQ4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 29. -0x64 29. -0x24 29. " IRQSIS[253] ,IRQ (MX_DATA_REQ_IRQ3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 28. -0x64 28. -0x24 28. " IRQSIS[252] ,IRQ (MX_DATA_REQ_IRQ2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 27. -0x64 27. -0x24 27. " IRQSIS[251] ,IRQ (MX_DATA_REQ_IRQ1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 26. -0x64 26. -0x24 26. " IRQSIS[250] ,IRQ (MX_DATA_REQ_IRQ0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 25. -0x64 25. -0x24 25. " IRQSIS[249] ,IRQ (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 24. -0x64 24. -0x24 24. " IRQSIS[248] ,IRQ (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 23. -0x64 23. -0x24 23. " IRQSIS[247] ,IRQ (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 22. -0x64 22. -0x24 22. " IRQSIS[246] ,IRQ (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 21. -0x64 21. -0x24 21. " IRQSIS[245] ,IRQ (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 20. -0x64 20. -0x24 20. " IRQSIS[244] ,IRQ (MX_AHB_ERR_IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 19. -0x64 19. -0x24 19. " IRQSIS[243] ,IRQ (WG_END_IRQ4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 18. -0x64 18. -0x24 18. " IRQSIS[242] ,IRQ (WG_END_IRQ3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 17. -0x64 17. -0x24 17. " IRQSIS[241] ,IRQ (WG_END_IRQ2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 16. -0x64 16. -0x24 16. " IRQSIS[240] ,IRQ (WG_END_IRQ1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 15. -0x64 15. -0x24 15. " IRQSIS[239] ,IRQ (WG_END_IRQ0) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 14. -0x64 14. -0x24 14. " IRQSIS[238] ,IRQ (WG_AHB_ERR_IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 13. -0x64 13. -0x24 13. " IRQSIS[237] ,IRQ (I2S1_IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 12. -0x64 12. -0x24 12. " IRQSIS[236] ,IRQ (I2S0_IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 09. -0x64 09. -0x24 09. " IRQSIS[233] ,IRQ (MFS ch.11 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 08. -0x64 08. -0x24 08. " IRQSIS[232] ,IRQ (MFS ch.10 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 07. -0x64 07. -0x24 07. " IRQSIS[231] ,IRQ (MFS ch.9 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 06. -0x64 06. -0x24 06. " IRQSIS[230] ,IRQ (MFS ch.8 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 05. -0x64 05. -0x24 05. " IRQSIS[229] ,IRQ (MFS ch.7 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 04. -0x64 04. -0x24 04. " IRQSIS[228] ,IRQ (MFS ch.6 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 03. -0x64 03. -0x24 03. " IRQSIS[227] ,IRQ (MFS ch.5 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 02. -0x64 02. -0x24 02. " IRQSIS[226] ,IRQ (MFS ch.4 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x1C 01. -0x64 01. -0x24 01. " IRQSIS[225] ,IRQ (MFS ch.3 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x1C 00. -0x64 00. -0x24 00. " IRQSIS[224] ,IRQ (MFS ch.2 error (Tx/Rx error, Status OR-ed)) software interrupt status bit" "No interrupt,Interrupt" tree.end newline width 17. tree "IRC IRQ Channel Enable Registers" group.long 0xC00++0x1F line.long 0x00 "IRQCE0_SET/CLR,IRC IRQ Channel Enable Setting Register 0" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[31] ,IRQ (External interrupt request ch.7/ch.23) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " IRQCE[30] ,IRQ (External interrupt request ch.6/ch.22) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " IRQCE[29] ,IRQ (External interrupt request ch.5/ch.21) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " IRQCE[28] ,IRQ (External interrupt request ch.4/ch.20) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " IRQCE[27] ,IRQ (External interrupt request ch.3/ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " IRQCE[26] ,IRQ (External interrupt request ch.2/ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " IRQCE[25] ,IRQ (External interrupt request ch.1/ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " IRQCE[24] ,IRQ (External interrupt request ch.0/ch.16) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 20. -0x80 20. -0x40 20. " IRQCE[20] ,IRQ (Work FLASH (RDY interrupt request)/(write completion)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " IRQCE[16] ,IRQ (IRC vector address RAM single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 15. -0x80 15. -0x40 15. " IRQCE[15] ,IRQ (CAN FD RAM(ch.0 to ch.3) single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " IRQCE[14] ,IRQ (System SRAM Single Bit Error) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 10. -0x80 10. -0x40 10. " IRQCE[10] ,IRQ (Work FLASH single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " IRQCE[8] ,IRQ (TCFLASH single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " IRQCE[3] ,IRQ (SW-WDT pre-warning) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " IRQCE[2] ,IRQ (HW-WDT pre-warning) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 01. -0x80 01. -0x40 01. " IRQCE[1] ,IRQ (System control status) channel enable setting bit" "Disabled,Enabled" line.long 0x04 "IRQCE1_SET/CLR,IRC IRQ Channel Enable Setting Register 1" setclrfld.long 0x04 31. -0x7C 31. -0x3C 31. " IRQCE[63] ,IRQ (MFS RX ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 30. -0x7C 30. -0x3C 30. " IRQCE[62] ,IRQ (MFS TX ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 29. -0x7C 29. -0x3C 29. " IRQCE[61] ,IRQ (MFS RX ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 28. -0x7C 28. -0x3C 28. " IRQCE[60] ,IRQ (MFS TX ch.7) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 27. -0x7C 27. -0x3C 27. " IRQCE[59] ,IRQ (MFS RX ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 26. -0x7C 26. -0x3C 26. " IRQCE[58] ,IRQ (MFS RX ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 25. -0x7C 25. -0x3C 25. " IRQCE[57] ,IRQ (MFS TX ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 24. -0x7C 24. -0x3C 24. " IRQCE[56] ,IRQ (MFS RX ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 23. -0x7C 23. -0x3C 23. " IRQCE[55] ,IRQ (MFS TX ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 22. -0x7C 22. -0x3C 22. " IRQCE[54] ,IRQ (MFS RX ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 21. -0x7C 21. -0x3C 21. " IRQCE[53] ,IRQ (MFS TX ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 20. -0x7C 20. -0x3C 20. " IRQCE[52] ,IRQ (MFS RX ch.3) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 19. -0x7C 19. -0x3C 19. " IRQCE[51] ,IRQ (MFS TX ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 18. -0x7C 18. -0x3C 18. " IRQCE[50] ,IRQ (MFS RX ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 17. -0x7C 17. -0x3C 17. " IRQCE[49] ,IRQ (MFS TX ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 16. -0x7C 16. -0x3C 16. " IRQCE[48] ,IRQ (MFS RX ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 15. -0x7C 15. -0x3C 15. " IRQCE[47] ,IRQ (MFS TX ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 14. -0x7C 14. -0x3C 14. " IRQCE[46] ,IRQ (MFS RX ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 11. -0x7C 11. -0x3C 11. " IRQCE[43] ,IRQ (CAN FD ch.3 (OR-ed of all factors)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 10. -0x7C 10. -0x3C 10. " IRQCE[42] ,IRQ (CAN FD ch.2 (OR-ed of all factors)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 09. -0x7C 09. -0x3C 09. " IRQCE[41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 08. -0x7C 08. -0x3C 08. " IRQCE[40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 07. -0x7C 07. -0x3C 07. " IRQCE[39] ,IRQ (External interrupt request ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 06. -0x7C 06. -0x3C 06. " IRQCE[38] ,IRQ (External interrupt request ch.14) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 05. -0x7C 05. -0x3C 05. " IRQCE[37] ,IRQ (External interrupt request ch.13) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 04. -0x7C 04. -0x3C 04. " IRQCE[36] ,IRQ (External interrupt request ch.12) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 03. -0x7C 03. -0x3C 03. " IRQCE[35] ,IRQ (External interrupt request ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 02. -0x7C 02. -0x3C 02. " IRQCE[34] ,IRQ (External interrupt request ch.10) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 01. -0x7C 01. -0x3C 01. " IRQCE[33] ,IRQ (External interrupt request ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 00. -0x7C 00. -0x3C 00. " IRQCE[32] ,IRQ (External interrupt request ch.8) channel enable setting bit" "Disabled,Enabled" line.long 0x08 "IRQCE2_SET/CLR,IRC IRQ Channel Enable Setting Register 2" setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQCE[95] ,IRQ (TCRAM diag) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 30. -0x78 30. -0x38 30. " IRQCE[94] ,IRQ (DDR HSSPI TX) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 29. -0x78 29. -0x38 29. " IRQCE[93] ,IRQ (DDR HSSPI RX) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 28. -0x78 28. -0x38 28. " IRQCE[92] ,IRQ (SHE) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQCE[91] ,IRQ (SHE error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 26. -0x78 26. -0x38 26. " IRQCE[90] ,IRQ (Indicator PWM) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 25. -0x78 25. -0x38 25. " IRQCE[89] ,IRQ (LCD bus interface WriteChannelDone) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 24. -0x78 24. -0x38 24. " IRQCE[88] ,IRQ (LCD bus interface ReadChannelDone) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 23. -0x78 23. -0x38 23. " IRQCE[87] ,IRQ (LCD bus interface RxFifoInterrupt status bits" "Disabled,Enabled" setclrfld.long 0x08 22. -0x78 22. -0x38 22. " IRQCE[86] ,IRQ (LCD bus interface InstrFifointerrupt) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 21. -0x78 21. -0x38 21. " IRQCE[85] ,IRQ (LCD bus Interface Sequencer Sync/ Error/Tearing Interrupt) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 20. -0x78 20. -0x38 20. " IRQCE[84] ,IRQ (SG ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 19. -0x78 19. -0x38 19. " IRQCE[83] ,IRQ (SG ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 18. -0x78 18. -0x38 18. " IRQCE[82] ,IRQ (SG ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 17. -0x78 17. -0x38 17. " IRQCE[81] ,IRQ (SG ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 16. -0x78 16. -0x38 16. " IRQCE[80] ,IRQ (SG ch.0) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 15. -0x78 15. -0x38 15. " IRQCE[79] ,IRQ (SMC ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 14. -0x78 14. -0x38 14. " IRQCE[78] ,IRQ (SMC ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 13. -0x78 13. -0x38 13. " IRQCE[77] ,IRQ (SMC ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 12. -0x78 12. -0x38 12. " IRQCE[76] ,IRQ (SMC ch.2) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 11. -0x78 11. -0x38 11. " IRQCE[75] ,IRQ (SMC ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 10. -0x78 10. -0x38 10. " IRQCE[74] ,IRQ (SMC ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 05. -0x78 05. -0x38 05. " IRQCE[69] ,IRQ (MFS TX ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 04. -0x78 04. -0x38 04. " IRQCE[68] ,IRQ (MFS RX ch.11) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 03. -0x78 03. -0x38 03. " IRQCE[67] ,IRQ (MFS TX ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 02. -0x78 02. -0x38 02. " IRQCE[66] ,IRQ (MFS RX ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 01. -0x78 01. -0x38 01. " IRQCE[65] ,IRQ (MFS TX ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 00. -0x78 00. -0x38 00. " IRQCE[64] ,IRQ (MFS RX ch.9) channel enable setting bit" "Disabled,Enabled" line.long 0x0C "IRQCE3_SET/CLR,IRC IRQ Channel Enable Setting Register 3" setclrfld.long 0x0C 27. -0x74 27. -0x34 27. " IRQCE[123] ,IRQ (Base timer ch.31) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " IRQCE[122] ,IRQ (Base timer ch.30) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " IRQCE[121] ,IRQ (Base timer ch.29) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " IRQCE[120] ,IRQ (Base timer ch.28) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " IRQCE[119] ,IRQBase timer ch.27) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " IRQCE[118] ,IRQ (Base timer ch.26) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " IRQCE[117] ,IRQ (Base timer ch.25) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " IRQCE[116] ,IRQ (Base timer ch.24) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 19. -0x74 19. -0x34 19. " IRQCE[115] ,IRQ (Base timer ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " IRQCE[114] ,IRQ (Base timer ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " IRQCE[113] ,IRQ (Base timer ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " IRQCE[112] ,IRQ (Base timer ch.16) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 15. -0x74 15. -0x34 15. " IRQCE[111] ,IRQ (Base timer ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " IRQCE[110] ,IRQ (Base timer ch.14) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 13. -0x74 13. -0x34 13. " IRQCE[109] ,IRQ (Base timer ch.13) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 12. -0x74 12. -0x34 12. " IRQCE[108] ,IRQ (Base timer ch.12/20/21/22/23) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 11. -0x74 11. -0x34 11. " IRQCE[107] ,IRQ (Base timer ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 10. -0x74 10. -0x34 10. " IRQCE[106] ,IRQ (Base timer ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 09. -0x74 09. -0x34 09. " IRQCE[105] ,IRQ (Base timer ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 08. -0x74 08. -0x34 08. " IRQCE[104] ,IRQ (Base timer ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 07. -0x74 07. -0x34 07. " IRQCE[103] ,IRQ (Base timer ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 06. -0x74 06. -0x34 06. " IRQCE[102] ,IRQ (Base timer ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 05. -0x74 05. -0x34 05. " IRQCE[101] ,IRQ (Base timer ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 04. -0x74 04. -0x34 04. " IRQCE[100] ,IRQ (Base timer ch.0/8/9/10/11) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 03. -0x74 03. -0x34 03. " IRQCE[99] ,IRQ (CR CARIBRATION) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 02. -0x74 02. -0x34 02. " IRQCE[98] ,IRQ (RTC) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 01. -0x74 01. -0x34 01. " IRQCE[97] ,IRQ (Global timer (Compare clear interrupt)) channel enable setting bit" "Disabled,Enabled" line.long 0x10 "IRQCE4_SET/CLR,IRC IRQ Channel Enable Setting Register 4" setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQCE[159] ,IRQ (PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 30. -0x70 30. -0x30 30. " IRQCE[158] ,IRQ (FRT ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQCE[157] ,IRQ (FRT ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 28. -0x70 28. -0x30 28. " IRQCE[156] ,IRQ (FRT ch.8) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 26. -0x70 26. -0x30 26. " IRQCE[154] ,IRQ (FRT ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 25. -0x70 25. -0x30 25. " IRQCE[153] ,IRQ (FRT ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 24. -0x70 24. -0x30 24. " IRQCE[152] ,IRQ (FRT ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 23. -0x70 23. -0x30 23. " IRQCE[151] ,IRQ (FRT ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 22. -0x70 22. -0x30 22. " IRQCE[150] ,IRQ (FRT ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 21. -0x70 21. -0x30 21. " IRQCE[149] ,IRQ (Reload timer ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 20. -0x70 20. -0x30 20. " IRQCE[148] ,IRQ (Reload timer ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 19. -0x70 19. -0x30 19. " IRQCE[147] ,IRQ (Reload timer ch.3) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 18. -0x70 18. -0x30 18. " IRQCE[146] ,IRQ (Reload timer ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 17. -0x70 17. -0x30 17. " IRQCE[145] ,IRQ (Reload timer ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 16. -0x70 16. -0x30 16. " IRQCE[144] ,IRQ (Reload timer ch.0) channel enable setting bit" "Disabled,Enabled" line.long 0x14 "IRQCE5_SET/CLR,IRC IRQ Channel Enable Setting Register 5" setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " IRQCE[189] ,IRQ (QPRC ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " IRQCE[188] ,IRQ (QPRC ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " IRQCE[187] ,IRQ (IRQ1 of output compare 10 (ch.21)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " IRQCE[186] ,IRQ1 of output compare 9 (ch.19)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " IRQCE[185] ,IRQ (IRQ1 of output compare 8 (ch.17)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " IRQCE[183] ,IRQ (IRQ1 of output compare 2 (ch.5)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " IRQCE[182] ,IRQ (IRQ1 of output compare 1 (ch.3)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " IRQCE[181] ,IRQ (IRQ1 of output compare 0 (ch.1)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " IRQCE[180] ,IRQ (IRQ0 of output compare 10 (ch.20)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " IRQCE[179] ,IRQ (IRQ0 of output compare 9 (ch.18)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " IRQCE[178] ,IRQ (IRQ0 of output compare 8 (ch.16)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " IRQCE[176] ,IRQ (IRQ0 of output compare 2 (ch.4)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " IRQCE[175] ,IRQ (IRQ0 of output compare 1 (ch.2)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " IRQCE[174] ,IRQ (IRQ0 of output compare 0 (ch.0)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " IRQCE[173] ,IRQ (IRQ1 of input capture 10 (ch.21)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " IRQCE[172] ,IRQ (IRQ1 of input capture 9 (ch.19)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " IRQCE[171] ,IRQ (IRQ1 of input capture 8 (ch.17)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " IRQCE[170] ,IRQ (IRQ1 of input capture 2 (ch.5)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 09. -0x6C 09. -0x2C 09. " IRQCE[169] ,IRQ (IRQ1 of input capture 1 (ch.3)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 08. -0x6C 08. -0x2C 08. " IRQCE[168] ,IRQ (IRQ1 of input capture 0 (ch.1)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 07. -0x6C 07. -0x2C 07. " IRQCE[167] ,IRQ (IRQ0 of input capture 10 (ch.20)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 06. -0x6C 06. -0x2C 06. " IRQCE[166] ,IRQ (IRQ0 of input capture 9 (ch.18)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 05. -0x6C 05. -0x2C 05. " IRQCE[165] ,IRQ (IRQ0 of input capture 8 (ch.16)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 04. -0x6C 04. -0x2C 04. " IRQCE[164] ,IRQ (IRQ0 of input capture 2 (ch.4)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 03. -0x6C 03. -0x2C 03. " IRQCE[163] ,IRQ (IRQ0 of input capture 1 (ch.2)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 02. -0x6C 02. -0x2C 02. " IRQCE[162] ,IRQ (IRQ0 of input capture 0 (ch.0)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 00. -0x6C 00. -0x2C 00. " IRQCE[160] ,IRQ (PCMPWM_DREQ) channel enable setting bit" "Disabled,Enabled" line.long 0x18 "IRQCE6_SET/CLR,IRC IRQ Channel Enable Setting Register 6" setclrfld.long 0x18 31. -0x68 31. -0x28 31. " IRQCE[223] ,IRQ (MFS ch.1 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQCE[222] ,IRQ (MFS ch.0 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 29. -0x68 29. -0x28 29. " IRQCE[221] ,IRQ (PRGCRC) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 28. -0x68 28. -0x28 28. " IRQCE[220] ,IRQ (CR5 Performance Monitor Unit IRQ) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 27. -0x68 27. -0x28 27. " IRQCE[219] ,IRQ (SCT Sub OSC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 26. -0x68 26. -0x28 26. " IRQCE[218] ,IRQ (SCT Main OSC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 25. -0x68 25. -0x28 25. " IRQCE[217] ,IRQ (SCT SRC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 24. -0x68 24. -0x28 24. " IRQCE[216] ,IRQ (SCT RC IRQ) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 23. -0x68 23. -0x28 23. " IRQCE[215] ,IRQ (DMAC RLT (ch.0,1,2,3 OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 22. -0x68 22. -0x28 22. " IRQCE[214] ,IRQ (DMAC completion ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 21. -0x68 21. -0x28 21. " IRQCE[213] ,IRQ (DMAC completion ch.14) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 20. -0x68 20. -0x28 20. " IRQCE[212] ,IRQ (DMAC completion ch.13) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 19. -0x68 19. -0x28 19. " IRQCE[211] ,IRQ (DMAC completion ch.12) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 18. -0x68 18. -0x28 18. " IRQCE[210] ,IRQ (DMAC completion ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 17. -0x68 17. -0x28 17. " IRQCE[209] ,IRQ (DMAC completion ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 16. -0x68 16. -0x28 16. " IRQCE[208] ,IRQ (DMAC completion ch.9) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 15. -0x68 15. -0x28 15. " IRQCE[207] ,IRQ (DMAC completion ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 14. -0x68 14. -0x28 14. " IRQCE[206] ,IRQ (DMAC completion ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQCE[205] ,IRQ (DMAC completion ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 12. -0x68 12. -0x28 12. " IRQCE[204] ,IRQ (DMAC completion ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 11. -0x68 11. -0x28 11. " IRQCE[203] ,IRQ (DMAC completion ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 10. -0x68 10. -0x28 10. " IRQCE[202] ,IRQ (DMAC completion ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 09. -0x68 09. -0x28 09. " IRQCE[201] ,IRQ (DMAC completion ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 08. -0x68 08. -0x28 08. " IRQCE[200] ,IRQ (DMAC completion ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 07. -0x68 07. -0x28 07. " IRQCE[199] ,IRQ (DMAC completion ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 06. -0x68 06. -0x28 06. " IRQCE[198] ,IRQ (DMA error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 05. -0x68 05. -0x28 05. " IRQCE[197] ,IRQ (ADC12B0 RCO) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 04. -0x68 04. -0x28 04. " IRQCE[196] ,IRQ (ADC12B0 pulse detection function) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 03. -0x68 03. -0x28 03. " IRQCE[195] ,IRQ (ADC12B0 group interrupt) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 02. -0x68 02. -0x28 02. " IRQCE[194] ,IRQ (ADC12B0 conversion done) channel enable setting bit" "Disabled,Enabled" line.long 0x1C "IRQCE7_SET/CLR,IRC IRQ Channel Enable Setting Register 7" setclrfld.long 0x1C 30. -0x64 30. -0x24 30. " IRQCE[254] ,IRQ (MX_DATA_REQ_IRQ4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 29. -0x64 29. -0x24 29. " IRQCE[253] ,IRQ (MX_DATA_REQ_IRQ3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 28. -0x64 28. -0x24 28. " IRQCE[252] ,IRQ (MX_DATA_REQ_IRQ2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 27. -0x64 27. -0x24 27. " IRQCE[251] ,IRQ (MX_DATA_REQ_IRQ1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 26. -0x64 26. -0x24 26. " IRQCE[250] ,IRQ (MX_DATA_REQ_IRQ0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 25. -0x64 25. -0x24 25. " IRQCE[249] ,IRQ (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 24. -0x64 24. -0x24 24. " IRQCE[248] ,IRQ (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 23. -0x64 23. -0x24 23. " IRQCE[247] ,IRQ (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 22. -0x64 22. -0x24 22. " IRQCE[246] ,IRQ (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 21. -0x64 21. -0x24 21. " IRQCE[245] ,IRQ (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 20. -0x64 20. -0x24 20. " IRQCE[244] ,IRQ (MX_AHB_ERR_IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 19. -0x64 19. -0x24 19. " IRQCE[243] ,IRQ (WG_END_IRQ4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 18. -0x64 18. -0x24 18. " IRQCE[242] ,IRQ (WG_END_IRQ3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 17. -0x64 17. -0x24 17. " IRQCE[241] ,IRQ (WG_END_IRQ2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 16. -0x64 16. -0x24 16. " IRQCE[240] ,IRQ (WG_END_IRQ1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 15. -0x64 15. -0x24 15. " IRQCE[239] ,IRQ (WG_END_IRQ0) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 14. -0x64 14. -0x24 14. " IRQCE[238] ,IRQ (WG_AHB_ERR_IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 13. -0x64 13. -0x24 13. " IRQCE[237] ,IRQ (I2S1_IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 12. -0x64 12. -0x24 12. " IRQCE[236] ,IRQ (I2S0_IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 09. -0x64 09. -0x24 09. " IRQCE[233] ,IRQ (MFS ch.11 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 08. -0x64 08. -0x24 08. " IRQCE[232] ,IRQ (MFS ch.10 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 07. -0x64 07. -0x24 07. " IRQCE[231] ,IRQ (MFS ch.9 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 06. -0x64 06. -0x24 06. " IRQCE[230] ,IRQ (MFS ch.8 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 05. -0x64 05. -0x24 05. " IRQCE[229] ,IRQ (MFS ch.7 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 04. -0x64 04. -0x24 04. " IRQCE[228] ,IRQ (MFS ch.6 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 03. -0x64 03. -0x24 03. " IRQCE[227] ,IRQ (MFS ch.5 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 02. -0x64 02. -0x24 02. " IRQCE[226] ,IRQ (MFS ch.4 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x1C 01. -0x64 01. -0x24 01. " IRQCE[225] ,IRQ (MFS ch.3 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x1C 00. -0x64 00. -0x24 00. " IRQCE[224] ,IRQ (MFS ch.2 error (Tx/Rx error, Status OR-ed)) channel enable setting bit" "Disabled,Enabled" tree.end newline width 15. group.long 0xC40++0x03 line.long 0x00 "NMIHC,IRC NMI Hold Clear Register" bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,,,,4,5,6,7,8,9,,,12,13,,15,,,18,,20,?..." rgroup.long 0xC44++0x03 line.long 0x00 "NMIHS,IRC NMI Hold Status Register" bitfld.long 0x00 20. " NMISIS[20] ,NMI20 (LCDBUS MPU) hold status bit" "Not applied,Applied" bitfld.long 0x00 18. " NMISIS[18] ,NMI18 (TPU protection violation) hold status bit" "Not applied,Applied" bitfld.long 0x00 15. " NMISIS[15] ,NMI15 (SHE MPU) hold status bit" "Not applied,Applied" bitfld.long 0x00 13. " NMISIS[13] ,NMI13 (DMAC MPU #0 protection violation) hold status bit" "Not applied,Applied" newline bitfld.long 0x00 12. " NMISIS[12] ,NMI12 (CAN-FD RAMs 2-bit ECC error detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 09. " NMISIS[9] ,NMI9 Expand PLL CSV(OR-ed of all factors) hold status bit" "Not applied,Applied" bitfld.long 0x00 08. " NMISIS[8] ,NMI8 (IRC 2-bit ECC err detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 07. " NMISIS[7] ,NMI7 (SW-WDT) hold status bit" "Not applied,Applied" newline bitfld.long 0x00 06. " NMISIS[6] ,NMI6 (HW-WDT) hold status bit" "Not applied,Applied" bitfld.long 0x00 05. " NMISIS[5] ,NMI5 (CSV, Profile) hold status bit" "Not applied,Applied" bitfld.long 0x00 04. " NMISIS[4] ,NMI4 LVDs IRQ hold status bit" "Not applied,Applied" bitfld.long 0x00 00. " NMISIS[0] ,NMI0 (NMIX pin(Ext-IRC)) hold status bit" "Not applied,Applied" newline group.long 0xC48++0x03 line.long 0x00 "IRQHC,IRC IRQ Hold Clear Register" hexmask.long.word 0x00 0.--8. 1. " IRQHCN ,Bits for IRQ channel number for which holds to be cleared" width 9. tree "IRQHS IRC IRQ Hold Status Register" rgroup.long 0xC50++0x1F line.long 0x00 "IRQHS,IRC IRQ Hold Status Register 0" bitfld.long 0x00 31. " IRQHS[31] ,IRQ (External interrupt request ch.7/ch.23) hold status bits" "Not applied,Applied" bitfld.long 0x00 30. " IRQHS[30] ,IRQ (External interrupt request ch.6/ch.22) hold status bits" "Not applied,Applied" bitfld.long 0x00 29. " IRQHS[29] ,IRQ (External interrupt request ch.5/ch.21) hold status bits" "Not applied,Applied" bitfld.long 0x00 28. " IRQHS[28] ,IRQ (External interrupt request ch.4/ch.20) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 27. " IRQHS[27] ,IRQ (External interrupt request ch.3/ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x00 26. " IRQHS[26] ,IRQ (External interrupt request ch.2/ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x00 25. " IRQHS[25] ,IRQ (External interrupt request ch.1/ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x00 24. " IRQHS[24] ,IRQ (External interrupt request ch.0/ch.16) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 20. " IRQHS[20] ,IRQ (Work FLASH (RDY interrupt request)/(write completion)) hold status bits" "Not applied,Applied" bitfld.long 0x00 16. " IRQHS[16] ,IRQ (IRC vector address RAM single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 15. " IRQHS[15] ,IRQ (CAN FD RAM(ch.0 to ch.3) single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 14. " IRQHS[14] ,IRQ (System SRAM single bit error) hold Status Bits" "Not applied,Applied" newline bitfld.long 0x00 10. " IRQHS[10] ,IRQ (Work FLASH single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 08. " IRQHS[8] ,IRQ (TCFLASH single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 03. " IRQHS[3] ,IRQ (SW-WDT pre-warning) hold status bits" "Not applied,Applied" bitfld.long 0x00 02. " IRQHS[2] ,IRQ (HW-WDT pre-warning) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 01. " IRQHS[1] ,IRQ (System control status) hold status bits" "Not applied,Applied" line.long 0x04 "IRQHS1,IRC IRQ Hold Status Register 1" bitfld.long 0x04 31. " IRQHS[63] ,IRQ (MFS RX ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x04 30. " IRQHS[62] ,IRQ (MFS TX ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x04 29. " IRQHS[61] ,IRQ (MFS RX ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x04 28. " IRQHS[60] ,IRQ (MFS TX ch.7) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 27. " IRQHS[59] ,IRQ (MFS RX ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x04 26. " IRQHS[58] ,IRQ (MFS RX ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x04 25. " IRQHS[57] ,IRQ (MFS TX ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x04 24. " IRQHS[56] ,IRQ (MFS RX ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 23. " IRQHS[55] ,IRQ (MFS TX ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x04 22. " IRQHS[54] ,IRQ (MFS RX ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x04 21. " IRQHS[53] ,IRQ (MFS TX ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x04 20. " IRQHS[52] ,IRQ (MFS RX ch.3) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 19. " IRQHS[51] ,IRQ (MFS TX ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x04 18. " IRQHS[50] ,IRQ (MFS RX ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x04 17. " IRQHS[49] ,IRQ (MFS TX ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x04 16. " IRQHS[48] ,IRQ (MFS RX ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 15. " IRQHS[47] ,IRQ (MFS TX ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x04 14. " IRQHS[46] ,IRQ (MFS RX ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x04 11. " IRQHS[43] ,IRQ (CAN FD ch.3 (OR-ed of all factors)) hold status bits" "Not applied,Applied" bitfld.long 0x04 10. " IRQHS[42] ,IRQ (CAN FD ch.2 (OR-ed of all factors)) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 09. " IRQHS[41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x04 08. " IRQHS[40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x04 07. " IRQHS[39] ,IRQ (External interrupt request ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x04 06. " IRQHS[38] ,IRQ (External interrupt request ch.14) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 05. " IRQHS[37] ,IRQ (External interrupt request ch.13) hold status bits" "Not applied,Applied" bitfld.long 0x04 04. " IRQHS[36] ,IRQ (External interrupt request ch.12) hold status bits" "Not applied,Applied" bitfld.long 0x04 03. " IRQHS[35] ,IRQ (External interrupt request ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x04 02. " IRQHS[34] ,IRQ (External interrupt request ch.10) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 01. " IRQHS[33] ,IRQ (External interrupt request ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x04 00. " IRQHS[32] ,IRQ (External interrupt request ch.8) hold status bits" "Not applied,Applied" line.long 0x08 "IRQHS2,IRC IRQ Hold Status Register 2" bitfld.long 0x08 31. " IRQHS[95] ,IRQ (TCRAM diag) hold status bits" "Not applied,Applied" bitfld.long 0x08 30. " IRQHS[94] ,IRQ (DDR HSSPI TX) hold status bits" "Not applied,Applied" bitfld.long 0x08 29. " IRQHS[93] ,IRQ (DDR HSSPI RX) hold status bits" "Not applied,Applied" bitfld.long 0x08 28. " IRQHS[92] ,IRQ (SHE) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 27. " IRQHS[91] ,IRQ (SHE error) hold status bits" "Not applied,Applied" bitfld.long 0x08 26. " IRQHS[90] ,IRQ (Indicator PWM) hold status bits" "Not applied,Applied" bitfld.long 0x08 25. " IRQHS[89] ,IRQ (LCD bus interface WriteChannelDone) hold status bits" "Not applied,Applied" bitfld.long 0x08 24. " IRQHS[88] ,IRQ (LCD bus interface ReadChannelDone) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 23. " IRQHS[87] ,IRQ (LCD bus interface RxFifoInterrupt status bits" "Not applied,Applied" bitfld.long 0x08 22. " IRQHS[86] ,IRQ (LCD bus interface InstrFifointerrupt) hold status bits" "Not applied,Applied" bitfld.long 0x08 21. " IRQHS[85] ,IRQ (LCD bus Interface Sequencer Sync/ Error/Tearing Interrupt) hold status bits" "Not applied,Applied" bitfld.long 0x08 20. " IRQHS[84] ,IRQ (SG ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 19. " IRQHS[83] ,IRQ (SG ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x08 18. " IRQHS[82] ,IRQ (SG ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x08 17. " IRQHS[81] ,IRQ (SG ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x08 16. " IRQHS[80] ,IRQ (SG ch.0) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 15. " IRQHS[79] ,IRQ (SMC ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x08 14. " IRQHS[78] ,IRQ (SMC ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x08 13. " IRQHS[77] ,IRQ (SMC ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x08 12. " IRQHS[76] ,IRQ (SMC ch.2) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 11. " IRQHS[75] ,IRQ (SMC ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x08 10. " IRQHS[74] ,IRQ (SMC ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x08 05. " IRQHS[69] ,IRQ (MFS TX ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x08 04. " IRQHS[68] ,IRQ (MFS RX ch.11) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 03. " IRQHS[67] ,IRQ (MFS TX ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x08 02. " IRQHS[66] ,IRQ (MFS RX ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x08 01. " IRQHS[65] ,IRQ (MFS TX ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x08 00. " IRQHS[64] ,IRQ (MFS RX ch.9) hold status bits" "Not applied,Applied" line.long 0x0C "IRQHS3,IRC IRQ Hold Status Register 3" bitfld.long 0x0C 27. " IRQHS[123] ,IRQ (Base timer ch.31) hold status bits" "Not applied,Applied" bitfld.long 0x0C 26. " IRQHS[122] ,IRQ (Base timer ch.30) hold status bits" "Not applied,Applied" bitfld.long 0x0C 25. " IRQHS[121] ,IRQ (Base timer ch.29) hold status bits" "Not applied,Applied" bitfld.long 0x0C 24. " IRQHS[120] ,IRQ (Base timer ch.28) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 23. " IRQHS[119] ,IRQBase timer ch.27) hold status bits" "Not applied,Applied" bitfld.long 0x0C 22. " IRQHS[118] ,IRQ (Base timer ch.26) hold status bits" "Not applied,Applied" bitfld.long 0x0C 21. " IRQHS[117] ,IRQ (Base timer ch.25) hold status bits" "Not applied,Applied" bitfld.long 0x0C 20. " IRQHS[116] ,IRQ (Base timer ch.24) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 19. " IRQHS[115] ,IRQ (Base timer ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x0C 18. " IRQHS[114] ,IRQ (Base timer ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x0C 17. " IRQHS[113] ,IRQ (Base timer ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x0C 16. " IRQHS[112] ,IRQ (Base timer ch.16) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 15. " IRQHS[111] ,IRQ (Base timer ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x0C 14. " IRQHS[110] ,IRQ (Base timer ch.14) hold status bits" "Not applied,Applied" bitfld.long 0x0C 13. " IRQHS[109] ,IRQ (Base timer ch.13) hold status bits" "Not applied,Applied" bitfld.long 0x0C 12. " IRQHS[108] ,IRQ (Base timer ch.12/20/21/22/23) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 11. " IRQHS[107] ,IRQ (Base timer ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x0C 10. " IRQHS[106] ,IRQ (Base timer ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x0C 09. " IRQHS[105] ,IRQ (Base timer ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x0C 08. " IRQHS[104] ,IRQ (Base timer ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 07. " IRQHS[103] ,IRQ (Base timer ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x0C 06. " IRQHS[102] ,IRQ (Base timer ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x0C 05. " IRQHS[101] ,IRQ (Base timer ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x0C 04. " IRQHS[100] ,IRQ (Base timer ch.0/8/9/10/11) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 03. " IRQHS[99] ,IRQ (CR CARIBRATION) hold status bits" "Not applied,Applied" bitfld.long 0x0C 02. " IRQHS[98] ,IRQ (RTC) hold status bits" "Not applied,Applied" bitfld.long 0x0C 01. " IRQHS[97] ,IRQ (Global timer (Compare clear interrupt)) hold status bits" "Not applied,Applied" line.long 0x10 "IRQHS4,IRC IRQ Hold Status Register 4" bitfld.long 0x10 31. " IRQHS[159] ,IRQ (PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE) hold status bits" "Not applied,Applied" bitfld.long 0x10 30. " IRQHS[158] ,IRQ (FRT ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x10 29. " IRQHS[157] ,IRQ (FRT ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x10 28. " IRQHS[156] ,IRQ (FRT ch.8) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 26. " IRQHS[154] ,IRQ (FRT ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x10 25. " IRQHS[153] ,IRQ (FRT ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x10 24. " IRQHS[152] ,IRQ (FRT ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x10 23. " IRQHS[151] ,IRQ (FRT ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 22. " IRQHS[150] ,IRQ (FRT ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x10 21. " IRQHS[149] ,IRQ (Reload timer ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x10 20. " IRQHS[148] ,IRQ (Reload timer ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x10 19. " IRQHS[147] ,IRQ (Reload timer ch.3) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 18. " IRQHS[146] ,IRQ (Reload timer ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x10 17. " IRQHS[145] ,IRQ (Reload timer ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x10 16. " IRQHS[144] ,IRQ (Reload timer ch.0) hold status bits" "Not applied,Applied" line.long 0x14 "IRQHS5,IRC IRQ Hold Status Register 5" bitfld.long 0x14 29. " IRQHS[189] ,IRQ (QPRC ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x14 28. " IRQHS[188] ,IRQ (QPRC ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x14 27. " IRQHS[187] ,IRQ (IRQ1 of output compare 10 (ch.21)) hold status bits" "Not applied,Applied" bitfld.long 0x14 26. " IRQHS[186] ,IRQ1 of output compare 9 (ch.19)) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 25. " IRQHS[185] ,IRQ (IRQ1 of output compare 8 (ch.17)) hold status bits" "Not applied,Applied" bitfld.long 0x14 23. " IRQHS[183] ,IRQ (IRQ1 of output compare 2 (ch.5)) hold status bits" "Not applied,Applied" bitfld.long 0x14 22. " IRQHS[182] ,IRQ (IRQ1 of output compare 1 (ch.3)) hold status bits" "Not applied,Applied" bitfld.long 0x14 21. " IRQHS[181] ,IRQ (IRQ1 of output compare 0 (ch.1)) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 20. " IRQHS[180] ,IRQ (IRQ0 of output compare 10 (ch.20)) hold status bits" "Not applied,Applied" bitfld.long 0x14 19. " IRQHS[179] ,IRQ (IRQ0 of output compare 9 (ch.18)) hold status bits" "Not applied,Applied" bitfld.long 0x14 18. " IRQHS[178] ,IRQ (IRQ0 of output compare 8 (ch.16)) hold status bits" "Not applied,Applied" bitfld.long 0x14 16. " IRQHS[176] ,IRQ (IRQ0 of output compare 2 (ch.4)) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 15. " IRQHS[175] ,IRQ (IRQ0 of output compare 1 (ch.2)) hold status bits" "Not applied,Applied" bitfld.long 0x14 14. " IRQHS[174] ,IRQ (IRQ0 of output compare 0 (ch.0)) hold status bits" "Not applied,Applied" bitfld.long 0x14 13. " IRQHS[173] ,IRQ (IRQ1 of input capture 10 (ch.21)) hold status bits" "Not applied,Applied" bitfld.long 0x14 12. " IRQHS[172] ,IRQ (IRQ1 of input capture 9 (ch.19)) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 11. " IRQHS[171] ,IRQ (IRQ1 of input capture 8 (ch.17)) hold status bits" "Not applied,Applied" bitfld.long 0x14 10. " IRQHS[170] ,IRQ (IRQ1 of input capture 2 (ch.5)) hold status bits" "Not applied,Applied" bitfld.long 0x14 09. " IRQHS[169] ,IRQ (IRQ1 of input capture 1 (ch.3)) hold status bits" "Not applied,Applied" bitfld.long 0x14 08. " IRQHS[168] ,IRQ (IRQ1 of input capture 0 (ch.1)) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 07. " IRQHS[167] ,IRQ (IRQ0 of input capture 10 (ch.20)) hold status bits" "Not applied,Applied" bitfld.long 0x14 06. " IRQHS[166] ,IRQ (IRQ0 of input capture 9 (ch.18)) hold status bits" "Not applied,Applied" bitfld.long 0x14 05. " IRQHS[165] ,IRQ (IRQ0 of input capture 8 (ch.16)) hold status bits" "Not applied,Applied" bitfld.long 0x14 04. " IRQHS[164] ,IRQ (IRQ0 of input capture 2 (ch.4)) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 03. " IRQHS[163] ,IRQ (IRQ0 of input capture 1 (ch.2)) hold status bits" "Not applied,Applied" bitfld.long 0x14 02. " IRQHS[162] ,IRQ (IRQ0 of input capture 0 (ch.0)) hold status bits" "Not applied,Applied" bitfld.long 0x14 00. " IRQHS[160] ,IRQ (PCMPWM_DREQ) hold status bits" "Not applied,Applied" line.long 0x18 "IRQHS6,IRC IRQ Hold Status Register 6" bitfld.long 0x18 31. " IRQHS[223] ,IRQ (MFS ch.1 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x18 30. " IRQHS[222] ,IRQ (MFS ch.0 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x18 29. " IRQHS[221] ,IRQ (PRGCRC) hold status bits" "Not applied,Applied" bitfld.long 0x18 28. " IRQHS[220] ,IRQ (CR5 Performance Monitor Unit IRQ) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 27. " IRQHS[219] ,IRQ (SCT Sub OSC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x18 26. " IRQHS[218] ,IRQ (SCT Main OSC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x18 25. " IRQHS[217] ,IRQ (SCT SRC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x18 24. " IRQHS[216] ,IRQ (SCT RC IRQ) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 23. " IRQHS[215] ,IRQ (DMAC RLT (ch.0,1,2,3 OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x18 22. " IRQHS[214] ,IRQ (DMAC completion ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x18 21. " IRQHS[213] ,IRQ (DMAC completion ch.14) hold status bits" "Not applied,Applied" bitfld.long 0x18 20. " IRQHS[212] ,IRQ (DMAC completion ch.13) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 19. " IRQHS[211] ,IRQ (DMAC completion ch.12) hold status bits" "Not applied,Applied" bitfld.long 0x18 18. " IRQHS[210] ,IRQ (DMAC completion ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x18 17. " IRQHS[209] ,IRQ (DMAC completion ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x18 16. " IRQHS[208] ,IRQ (DMAC completion ch.9) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 15. " IRQHS[207] ,IRQ (DMAC completion ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x18 14. " IRQHS[206] ,IRQ (DMAC completion ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x18 13. " IRQHS[205] ,IRQ (DMAC completion ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x18 12. " IRQHS[204] ,IRQ (DMAC completion ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 11. " IRQHS[203] ,IRQ (DMAC completion ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x18 10. " IRQHS[202] ,IRQ (DMAC completion ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x18 09. " IRQHS[201] ,IRQ (DMAC completion ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x18 08. " IRQHS[200] ,IRQ (DMAC completion ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 07. " IRQHS[199] ,IRQ (DMAC completion ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x18 06. " IRQHS[198] ,IRQ (DMA error) hold status bits" "Not applied,Applied" bitfld.long 0x18 05. " IRQHS[197] ,IRQ (ADC12B0 RCO) hold status bits" "Not applied,Applied" bitfld.long 0x18 04. " IRQHS[196] ,IRQ (ADC12B0 pulse detection function) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 03. " IRQHS[195] ,IRQ (ADC12B0 group interrupt) hold status bits" "Not applied,Applied" bitfld.long 0x18 02. " IRQHS[194] ,IRQ (ADC12B0 conversion done) hold status bits" "Not applied,Applied" line.long 0x1C "IRQHS7,IRC IRQ Hold Status Register 7" bitfld.long 0x1C 30. " IRQHS[254] ,IRQ (MX_DATA_REQ_IRQ4) hold status bits" "Not applied,Applied" bitfld.long 0x1C 29. " IRQHS[253] ,IRQ (MX_DATA_REQ_IRQ3) hold status bits" "Not applied,Applied" bitfld.long 0x1C 28. " IRQHS[252] ,IRQ (MX_DATA_REQ_IRQ2) hold status bits" "Not applied,Applied" bitfld.long 0x1C 27. " IRQHS[251] ,IRQ (MX_DATA_REQ_IRQ1) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 26. " IRQHS[250] ,IRQ (MX_DATA_REQ_IRQ0) hold status bits" "Not applied,Applied" bitfld.long 0x1C 25. " IRQHS[249] ,IRQ (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) hold status bits" "Not applied,Applied" bitfld.long 0x1C 24. " IRQHS[248] ,IRQ (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) hold status bits" "Not applied,Applied" bitfld.long 0x1C 23. " IRQHS[247] ,IRQ (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 22. " IRQHS[246] ,IRQ (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) hold status bits" "Not applied,Applied" bitfld.long 0x1C 21. " IRQHS[245] ,IRQ (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) hold status bits" "Not applied,Applied" bitfld.long 0x1C 20. " IRQHS[244] ,IRQ (MX_AHB_ERR_IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x1C 19. " IRQHS[243] ,IRQ (WG_END_IRQ4) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 18. " IRQHS[242] ,IRQ (WG_END_IRQ3) hold status bits" "Not applied,Applied" bitfld.long 0x1C 17. " IRQHS[241] ,IRQ (WG_END_IRQ2) hold status bits" "Not applied,Applied" bitfld.long 0x1C 16. " IRQHS[240] ,IRQ (WG_END_IRQ1) hold status bits" "Not applied,Applied" bitfld.long 0x1C 15. " IRQHS[239] ,IRQ (WG_END_IRQ0) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 14. " IRQHS[238] ,IRQ (WG_AHB_ERR_IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x1C 13. " IRQHS[237] ,IRQ (I2S1_IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x1C 12. " IRQHS[236] ,IRQ (I2S0_IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x1C 09. " IRQHS[233] ,IRQ (MFS ch.11 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 08. " IRQHS[232] ,IRQ (MFS ch.10 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x1C 07. " IRQHS[231] ,IRQ (MFS ch.9 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x1C 06. " IRQHS[230] ,IRQ (MFS ch.8 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x1C 05. " IRQHS[229] ,IRQ (MFS ch.7 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 04. " IRQHS[228] ,IRQ (MFS ch.6 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x1C 03. " IRQHS[227] ,IRQ (MFS ch.5 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x1C 02. " IRQHS[226] ,IRQ (MFS ch.4 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" bitfld.long 0x1C 01. " IRQHS[225] ,IRQ (MFS ch.3 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" newline bitfld.long 0x1C 00. " IRQHS[224] ,IRQ (MFS ch.2 error (Tx/Rx error, Status OR-ed)) hold status bits" "Not applied,Applied" tree.end newline width 9. group.long 0xC90++0x03 line.long 0x00 "IRQPLM,IRC IRQ Priority Level Mask Register" bitfld.long 0x00 0.--5. " IRQPLM ,IRQ priority level mask bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC98++0x03 line.long 0x00 "CSR,IRC Control/Status Register" rbitfld.long 0x00 16. " LST ,Interrupt controller lock status" "Unlocked,Locked" bitfld.long 0x00 0. " IRQEN ,IRQ processing block enable/disable setting bit" "Disabled,Enabled" newline rgroup.long 0xCA8++0x07 line.long 0x00 "NMIRS,IRC NMI RAW Status Register" bitfld.long 0x00 20. " NMIRS[20] ,RAW status bit for NMI (LCDBUS MPU)" "No interrupt,Interrupt" bitfld.long 0x00 18. " NMIRS[18] ,RAW status bit for NMI (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x00 15. " NMIRS[15] ,RAW status bit for NMI (SHE MPU)" "No interrupt,Interrupt" bitfld.long 0x00 13. " NMIRS[13] ,RAW status bit for NMI (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " NMIRS[12] ,RAW status bit for NMI (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 09. " NMIRS[9] ,RAW status bit for NMI (Expand PLL CSV(OR-ed of all factors))" "No interrupt,Interrupt" bitfld.long 0x00 08. " NMIRS[8] ,RAW status bit for NMI (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x00 07. " NMIRS[7] ,RAW status bit for NMI (SW-WDT)" "No interrupt,Interrupt" newline bitfld.long 0x00 06. " NMIRS[6] ,RAW status bit for NMI (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x00 05. " NMIRS[5] ,RAW status bit for NMI (CSV, Profile)" "No interrupt,Interrupt" bitfld.long 0x00 04. " NMIRS[4] ,RAW status bit for NMI (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x00 00. " NMIRS[0] ,RAW status bit for NMI (NMIX pin(Ext-IRC))" "No interrupt,Interrupt" line.long 0x04 "NIMPS,IRC NMI preprocessed status register" bitfld.long 0x04 20. " NMIPS[20] ,Preprocessed status bits for LCDBUS MPU" "No interrupt,Interrupt" bitfld.long 0x04 18. " NMIPS[18] ,Preprocessed status bits for TPU protection violation" "No interrupt,Interrupt" bitfld.long 0x04 15. " NMIPS[15] ,Preprocessed status bits for SHE MPU" "No interrupt,Interrupt" bitfld.long 0x04 13. " NMIPS[13] ,Preprocessed status bits for DMAC MPU #0 protection violation" "No interrupt,Interrupt" newline bitfld.long 0x04 12. " NMIPS[12] ,Preprocessed status bits for (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x04 09. " NMIPS[9] ,Preprocessed status bits for (Expand PLL CSV(OR-ed of all factors))" "No interrupt,Interrupt" bitfld.long 0x04 08. " NMIPS[8] ,Preprocessed status bits for (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x04 07. " NMIPS[7] ,Preprocessed status bits for (SW-WDT)" "No interrupt,Interrupt" newline bitfld.long 0x04 06. " NMIPS[6] ,Preprocessed status bits for (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x04 05. " NMIPS[5] ,Preprocessed status bits for (CSV, Profile)" "No interrupt,Interrupt" bitfld.long 0x04 04. " NMIPS[4] ,Preprocessed status bits for (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x04 00. " NMIPS[0] ,Preprocessed status bits for (NMIX pin(Ext-IRC))" "No interrupt,Interrupt" tree "IRQRS IRC IRQ RWA Status Register" rgroup.long 0xCB0++0x1F line.long 0x00 "IRQRS0,IRC IRQ RAW Status Register 0" bitfld.long 0x00 31. " IRQRS[31] ,IRQ (External interrupt request ch.7/ch.23) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQRS[30] ,IRQ (External interrupt request ch.6/ch.22) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQRS[29] ,IRQ (External interrupt request ch.5/ch.21) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQRS[28] ,IRQ (External interrupt request ch.4/ch.20) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " IRQRS[27] ,IRQ (External interrupt request ch.3/ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQRS[26] ,IRQ (External interrupt request ch.2/ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQRS[25] ,IRQ (External interrupt request ch.1/ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQRS[24] ,IRQ (External interrupt request ch.0/ch.16) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 20. " IRQRS[20] ,IRQ (Work FLASH (RDY interrupt request)/(write completion)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQRS[16] ,IRQ (IRC vector address RAM single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 15. " IRQRS[15] ,IRQ (CAN FD RAM(ch.0 to ch.3)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQRS[14] ,IRQ (System SRAM Single Bit Error) RAW Status Bits" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " IRQRS[10] ,IRQ (Work FLASH single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQRS[8] ,IRQ (TCFLASH single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQRS[3] ,IRQ (SW-WDT pre-warning) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQRS[2] ,IRQ (HW-WDT pre-warning) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 01. " IRQRS[1] ,IRQ (System control status) RAW status bits" "No interrupt,Interrupt" line.long 0x04 "IRQRS1,IRC IRQ RAW Status Register 1" bitfld.long 0x04 31. " IRQRS[63] ,IRQ (MFS RX ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 30. " IRQRS[62] ,IRQ (MFS TX ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 29. " IRQRS[61] ,IRQ (MFS RX ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 28. " IRQRS[60] ,IRQ (MFS TX ch.7) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " IRQRS[59] ,IRQ (MFS RX ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 26. " IRQRS[58] ,IRQ (MFS RX ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 25. " IRQRS[57] ,IRQ (MFS TX ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 24. " IRQRS[56] ,IRQ (MFS RX ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 23. " IRQRS[55] ,IRQ (MFS TX ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 22. " IRQRS[54] ,IRQ (MFS RX ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 21. " IRQRS[53] ,IRQ (MFS TX ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 20. " IRQRS[52] ,IRQ (MFS RX ch.3) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 19. " IRQRS[51] ,IRQ (MFS TX ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 18. " IRQRS[50] ,IRQ (MFS RX ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 17. " IRQRS[49] ,IRQ (MFS TX ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 16. " IRQRS[48] ,IRQ (MFS RX ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 15. " IRQRS[47] ,IRQ (MFS TX ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 14. " IRQRS[46] ,IRQ (MFS RX ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 11. " IRQRS[43] ,IRQ (CAN FD ch.3 (OR-ed of all factors)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 10. " IRQRS[42] ,IRQ (CAN FD ch.2 (OR-ed of all factors)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 09. " IRQRS[41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 08. " IRQRS[40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 07. " IRQRS[39] ,IRQ (External interrupt request ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 06. " IRQRS[38] ,IRQ (External interrupt request ch.14) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 05. " IRQRS[37] ,IRQ (External interrupt request ch.13) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 04. " IRQRS[36] ,IRQ (External interrupt request ch.12) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 03. " IRQRS[35] ,IRQ (External interrupt request ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 02. " IRQRS[34] ,IRQ (External interrupt request ch.10) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 01. " IRQRS[33] ,IRQ (External interrupt request ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 00. " IRQRS[32] ,IRQ (External interrupt request ch.8) RAW status bits" "No interrupt,Interrupt" line.long 0x08 "IRQRS2,IRC IRQ RAW Status Register 2" bitfld.long 0x08 31. " IRQRS[95] ,IRQ (TCRAM diag) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 30. " IRQRS[94] ,IRQ (DDR HSSPI TX) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 29. " IRQRS[93] ,IRQ (DDR HSSPI RX) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 28. " IRQRS[92] ,IRQ (SHE) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 27. " IRQRS[91] ,IRQ (SHE error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 26. " IRQRS[90] ,IRQ (Indicator PWM) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 25. " IRQRS[89] ,IRQ (LCD bus interface WriteChannelDone) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 24. " IRQRS[88] ,IRQ (LCD bus interface ReadChannelDone) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " IRQRS[87] ,IRQ (LCD bus interface RxFifoInterrupt status bits" "No interrupt,Interrupt" bitfld.long 0x08 22. " IRQRS[86] ,IRQ (LCD bus interface InstrFifointerrupt) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 21. " IRQRS[85] ,IRQ (LCD bus Interface Sequencer Sync/ Error/Tearing Interrupt) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 20. " IRQRS[84] ,IRQ (SG ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " IRQRS[83] ,IRQ (SG ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 18. " IRQRS[82] ,IRQ (SG ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 17. " IRQRS[81] ,IRQ (SG ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 16. " IRQRS[80] ,IRQ (SG ch.0) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " IRQRS[79] ,IRQ (SMC ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 14. " IRQRS[78] ,IRQ (SMC ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 13. " IRQRS[77] ,IRQ (SMC ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 12. " IRQRS[76] ,IRQ (SMC ch.2) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " IRQRS[75] ,IRQ (SMC ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 10. " IRQRS[74] ,IRQ (SMC ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 05. " IRQRS[69] ,IRQ (MFS TX ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 04. " IRQRS[68] ,IRQ (MFS RX ch.11) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 03. " IRQRS[67] ,IRQ (MFS TX ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 02. " IRQRS[66] ,IRQ (MFS RX ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 01. " IRQRS[65] ,IRQ (MFS TX ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 00. " IRQRS[64] ,IRQ (MFS RX ch.9) RAW status bits" "No interrupt,Interrupt" line.long 0x0C "IRQRS3,IRC IRQ RAW Status Register 3" bitfld.long 0x0C 27. " IRQRS[123] ,IRQ (Base timer ch.31) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 26. " IRQRS[122] ,IRQ (Base timer ch.30) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 25. " IRQRS[121] ,IRQ (Base timer ch.29) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 24. " IRQRS[120] ,IRQ (Base timer ch.28) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 23. " IRQRS[119] ,IRQBase timer ch.27) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 22. " IRQRS[118] ,IRQ (Base timer ch.26) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 21. " IRQRS[117] ,IRQ (Base timer ch.25) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 20. " IRQRS[116] ,IRQ (Base timer ch.24) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 19. " IRQRS[115] ,IRQ (Base timer ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 18. " IRQRS[114] ,IRQ (Base timer ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 17. " IRQRS[113] ,IRQ (Base timer ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 16. " IRQRS[112] ,IRQ (Base timer ch.16) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 15. " IRQRS[111] ,IRQ (Base timer ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 14. " IRQRS[110] ,IRQ (Base timer ch.14) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 13. " IRQRS[109] ,IRQ (Base timer ch.13) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 12. " IRQRS[108] ,IRQ (Base timer ch.12/20/21/22/23) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 11. " IRQRS[107] ,IRQ (Base timer ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 10. " IRQRS[106] ,IRQ (Base timer ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 09. " IRQRS[105] ,IRQ (Base timer ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 08. " IRQRS[104] ,IRQ (Base timer ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 07. " IRQRS[103] ,IRQ (Base timer ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 06. " IRQRS[102] ,IRQ (Base timer ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 05. " IRQRS[101] ,IRQ (Base timer ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 04. " IRQRS[100] ,IRQ (Base timer ch.0/8/9/10/11) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 03. " IRQRS[99] ,IRQ (CR CARIBRATION) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 02. " IRQRS[98] ,IRQ (RTC) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 01. " IRQRS[97] ,IRQ (Global timer (Compare clear interrupt)) RAW status bits" "No interrupt,Interrupt" line.long 0x10 "IRQRS4,IRC IRQ RAW Status Register 4" bitfld.long 0x10 31. " IRQRS[159] ,IRQ (PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 30. " IRQRS[158] ,IRQ (FRT ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 29. " IRQRS[157] ,IRQ (FRT ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 28. " IRQRS[156] ,IRQ (FRT ch.8) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 26. " IRQRS[154] ,IRQ (FRT ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 25. " IRQRS[153] ,IRQ (FRT ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 24. " IRQRS[152] ,IRQ (FRT ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 23. " IRQRS[151] ,IRQ (FRT ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 22. " IRQRS[150] ,IRQ (FRT ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 21. " IRQRS[149] ,IRQ (Reload timer ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 20. " IRQRS[148] ,IRQ (Reload timer ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 19. " IRQRS[147] ,IRQ (Reload timer ch.3) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 18. " IRQRS[146] ,IRQ (Reload timer ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 17. " IRQRS[145] ,IRQ (Reload timer ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 16. " IRQRS[144] ,IRQ (Reload timer ch.0) RAW status bits" "No interrupt,Interrupt" line.long 0x14 "IRQRS5,IRC IRQ RAW Status Register 5" bitfld.long 0x14 29. " IRQRS[189] ,IRQ (QPRC ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 28. " IRQRS[188] ,IRQ (QPRC ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 27. " IRQRS[187] ,IRQ (IRQ1 of output compare 10 (ch.21)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 26. " IRQRS[186] ,IRQ1 of output compare 9 (ch.19)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 25. " IRQRS[185] ,IRQ (IRQ1 of output compare 8 (ch.17)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 23. " IRQRS[183] ,IRQ (IRQ1 of output compare 2 (ch.5)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 22. " IRQRS[182] ,IRQ (IRQ1 of output compare 1 (ch.3)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 21. " IRQRS[181] ,IRQ (IRQ1 of output compare 0 (ch.1)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 20. " IRQRS[180] ,IRQ (IRQ0 of output compare 10 (ch.20)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 19. " IRQRS[179] ,IRQ (IRQ0 of output compare 9 (ch.18)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 18. " IRQRS[178] ,IRQ (IRQ0 of output compare 8 (ch.16)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 16. " IRQRS[176] ,IRQ (IRQ0 of output compare 2 (ch.4)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " IRQRS[175] ,IRQ (IRQ0 of output compare 1 (ch.2)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 14. " IRQRS[174] ,IRQ (IRQ0 of output compare 0 (ch.0)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 13. " IRQRS[173] ,IRQ (IRQ1 of input capture 10 (ch.21)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 12. " IRQRS[172] ,IRQ (IRQ1 of input capture 9 (ch.19)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " IRQRS[171] ,IRQ (IRQ1 of input capture 8 (ch.17)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 10. " IRQRS[170] ,IRQ (IRQ1 of input capture 2 (ch.5)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 09. " IRQRS[169] ,IRQ (IRQ1 of input capture 1 (ch.3)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 08. " IRQRS[168] ,IRQ (IRQ1 of input capture 0 (ch.1)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 07. " IRQRS[167] ,IRQ (IRQ0 of input capture 10 (ch.20)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 06. " IRQRS[166] ,IRQ (IRQ0 of input capture 9 (ch.18)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 05. " IRQRS[165] ,IRQ (IRQ0 of input capture 8 (ch.16)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 04. " IRQRS[164] ,IRQ (IRQ0 of input capture 2 (ch.4)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 03. " IRQRS[163] ,IRQ (IRQ0 of input capture 1 (ch.2)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 02. " IRQRS[162] ,IRQ (IRQ0 of input capture 0 (ch.0)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 00. " IRQRS[160] ,IRQ (PCMPWM_DREQ) RAW status bits" "No interrupt,Interrupt" line.long 0x18 "IRQRS6,IRC IRQ RAW Status Register 6" bitfld.long 0x18 31. " IRQRS[223] ,IRQ (MFS ch.1 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 30. " IRQRS[222] ,IRQ (MFS ch.0 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 29. " IRQRS[221] ,IRQ (PRGCRC) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 28. " IRQRS[220] ,IRQ (CR5 performance monitor unit IRQ) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 27. " IRQRS[219] ,IRQ (SCT Sub OSC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 26. " IRQRS[218] ,IRQ (SCT Main OSC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 25. " IRQRS[217] ,IRQ (SCT SRC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 24. " IRQRS[216] ,IRQ (SCT RC IRQ) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 23. " IRQRS[215] ,IRQ (DMAC RLT (ch.0,1,2,3 OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 22. " IRQRS[214] ,IRQ (DMAC completion ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 21. " IRQRS[213] ,IRQ (DMAC completion ch.14) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 20. " IRQRS[212] ,IRQ (DMAC completion ch.13) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 19. " IRQRS[211] ,IRQ (DMAC completion ch.12) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 18. " IRQRS[210] ,IRQ (DMAC completion ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 17. " IRQRS[209] ,IRQ (DMAC completion ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 16. " IRQRS[208] ,IRQ (DMAC completion ch.9) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 15. " IRQRS[207] ,IRQ (DMAC completion ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 14. " IRQRS[206] ,IRQ (DMAC completion ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 13. " IRQRS[205] ,IRQ (DMAC completion ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 12. " IRQRS[204] ,IRQ (DMAC completion ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 11. " IRQRS[203] ,IRQ (DMAC completion ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 10. " IRQRS[202] ,IRQ (DMAC completion ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 09. " IRQRS[201] ,IRQ (DMAC completion ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 08. " IRQRS[200] ,IRQ (DMAC completion ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 07. " IRQRS[199] ,IRQ (DMAC completion ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 06. " IRQRS[198] ,IRQ (DMA error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 05. " IRQRS[197] ,IRQ (ADC12B0 RCO) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 04. " IRQRS[196] ,IRQ (ADC12B0 pulse detection function) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 03. " IRQRS[195] ,IRQ (ADC12B0 group interrupt) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 02. " IRQRS[194] ,IRQ (ADC12B0 conversion done) RAW status bits" "No interrupt,Interrupt" line.long 0x1C "IRQRS7,IRC IRQ RAW Status Register 7" bitfld.long 0x1C 30. " IRQRS[254] ,IRQ (MX_DATA_REQ_IRQ4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 29. " IRQRS[253] ,IRQ (MX_DATA_REQ_IRQ3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 28. " IRQRS[252] ,IRQ (MX_DATA_REQ_IRQ2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 27. " IRQRS[251] ,IRQ (MX_DATA_REQ_IRQ1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 26. " IRQRS[250] ,IRQ (MX_DATA_REQ_IRQ0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 25. " IRQRS[249] ,IRQ (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 24. " IRQRS[248] ,IRQ (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 23. " IRQRS[247] ,IRQ (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 22. " IRQRS[246] ,IRQ (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 21. " IRQRS[245] ,IRQ (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 20. " IRQRS[244] ,IRQ (MX_AHB_ERR_IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 19. " IRQRS[243] ,IRQ (WG_END_IRQ4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 18. " IRQRS[242] ,IRQ (WG_END_IRQ3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 17. " IRQRS[241] ,IRQ (WG_END_IRQ2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 16. " IRQRS[240] ,IRQ (WG_END_IRQ1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 15. " IRQRS[239] ,IRQ (WG_END_IRQ0) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 14. " IRQRS[238] ,IRQ (WG_AHB_ERR_IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 13. " IRQRS[237] ,IRQ (I2S1_IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 12. " IRQRS[236] ,IRQ (I2S0_IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 09. " IRQRS[233] ,IRQ (MFS ch.11 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 08. " IRQRS[232] ,IRQ (MFS ch.10 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 07. " IRQRS[231] ,IRQ (MFS ch.9 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 06. " IRQRS[230] ,IRQ (MFS ch.8 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 05. " IRQRS[229] ,IRQ (MFS ch.7 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 04. " IRQRS[228] ,IRQ (MFS ch.6 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 03. " IRQRS[227] ,IRQ (MFS ch.5 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 02. " IRQRS[226] ,IRQ (MFS ch.4 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x1C 01. " IRQRS[225] ,IRQ (MFS ch.3 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x1C 00. " IRQRS[224] ,IRQ (MFS ch.2 error (Tx/Rx error, Status OR-ed)) RAW status bits" "No interrupt,Interrupt" tree.end tree "IRQPS IRC IRQ Preprocessed Status Register" rgroup.long 0xCF0++0x1F line.long 0x00 "IRQPS0,IRC IRQ Preprocessed Status Register 0" bitfld.long 0x00 31. " IRQPS[31] ,IRQ (External interrupt request ch.7/ch.23) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQPS[30] ,IRQ (External interrupt request ch.6/ch.22) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQPS[29] ,IRQ (External interrupt request ch.5/ch.21) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQPS[28] ,IRQ (External interrupt request ch.4/ch.20) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " IRQPS[27] ,IRQ (External interrupt request ch.3/ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQPS[26] ,IRQ (External interrupt request ch.2/ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQPS[25] ,IRQ (External interrupt request ch.1/ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQPS[24] ,IRQ (External interrupt request ch.0/ch.16) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 20. " IRQPS[20] ,IRQ (Work FLASH (RDY interrupt request)/(write completion)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQPS[16] ,IRQ (IRC vector address RAM single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 15. " IRQPS[15] ,IRQ (CAN FD RAM(ch.0 to ch.3) single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQPS[14] ,IRQ (System SRAM Single Bit Error) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " IRQPS[10] ,IRQ (Work FLASH single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 08. " IRQPS[8] ,IRQ (TCFLASH single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 03. " IRQPS[3] ,IRQ (SW-WDT pre-warning) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 02. " IRQPS[2] ,IRQ (HW-WDT pre-warning) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 01. " IRQPS[1] ,IRQ (System control status) preprocessed status bit" "No interrupt,Interrupt" line.long 0x04 "IRQPS1,IRC IRQ Preprocessed Status Register 1" bitfld.long 0x04 31. " IRQPS[63] ,IRQ (MFS RX ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 30. " IRQPS[62] ,IRQ (MFS TX ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 29. " IRQPS[61] ,IRQ (MFS RX ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 28. " IRQPS[60] ,IRQ (MFS TX ch.7) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " IRQPS[59] ,IRQ (MFS RX ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 26. " IRQPS[58] ,IRQ (MFS RX ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 25. " IRQPS[57] ,IRQ (MFS TX ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 24. " IRQPS[56] ,IRQ (MFS RX ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 23. " IRQPS[55] ,IRQ (MFS TX ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 22. " IRQPS[54] ,IRQ (MFS RX ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 21. " IRQPS[53] ,IRQ (MFS TX ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 20. " IRQPS[52] ,IRQ (MFS RX ch.3) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 19. " IRQPS[51] ,IRQ (MFS TX ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 18. " IRQPS[50] ,IRQ (MFS RX ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 17. " IRQPS[49] ,IRQ (MFS TX ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 16. " IRQPS[48] ,IRQ (MFS RX ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 15. " IRQPS[47] ,IRQ (MFS TX ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 14. " IRQPS[46] ,IRQ (MFS RX ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 11. " IRQPS[43] ,IRQ (CAN FD ch.3 (OR-ed of all factors)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 10. " IRQPS[42] ,IRQ (CAN FD ch.2 (OR-ed of all factors)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 09. " IRQPS[41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 08. " IRQPS[40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 07. " IRQPS[39] ,IRQ (External interrupt request ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 06. " IRQPS[38] ,IRQ (External interrupt request ch.14) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 05. " IRQPS[37] ,IRQ (External interrupt request ch.13) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 04. " IRQPS[36] ,IRQ (External interrupt request ch.12) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 03. " IRQPS[35] ,IRQ (External interrupt request ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 02. " IRQPS[34] ,IRQ (External interrupt request ch.10) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 01. " IRQPS[33] ,IRQ (External interrupt request ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 00. " IRQPS[32] ,IRQ (External interrupt request ch.8) preprocessed status bit" "No interrupt,Interrupt" line.long 0x08 "IRQPS2,IRC IRQ Preprocessed Status Register 2" bitfld.long 0x08 31. " IRQPS[95] ,IRQ (TCRAM diag) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 30. " IRQPS[94] ,IRQ (DDR HSSPI TX) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 29. " IRQPS[93] ,IRQ (DDR HSSPI RX) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 28. " IRQPS[92] ,IRQ (SHE) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 27. " IRQPS[91] ,IRQ (SHE error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 26. " IRQPS[90] ,IRQ (Indicator PWM) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 25. " IRQPS[89] ,IRQ (LCD bus interface WriteChannelDone) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 24. " IRQPS[88] ,IRQ (LCD bus interface ReadChannelDone) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " IRQPS[87] ,IRQ (LCD bus interface RxFifoInterrupt status bits" "No interrupt,Interrupt" bitfld.long 0x08 22. " IRQPS[86] ,IRQ (LCD bus interface InstrFifointerrupt) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 21. " IRQPS[85] ,IRQ (LCD bus Interface Sequencer Sync/ Error/Tearing Interrupt) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 20. " IRQPS[84] ,IRQ (SG ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " IRQPS[83] ,IRQ (SG ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 18. " IRQPS[82] ,IRQ (SG ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 17. " IRQPS[81] ,IRQ (SG ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 16. " IRQPS[80] ,IRQ (SG ch.0) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " IRQPS[79] ,IRQ (SMC ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 14. " IRQPS[78] ,IRQ (SMC ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 13. " IRQPS[77] ,IRQ (SMC ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 12. " IRQPS[76] ,IRQ (SMC ch.2) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " IRQPS[75] ,IRQ (SMC ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 10. " IRQPS[74] ,IRQ (SMC ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 05. " IRQPS[69] ,IRQ (MFS TX ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 04. " IRQPS[68] ,IRQ (MFS RX ch.11) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 03. " IRQPS[67] ,IRQ (MFS TX ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 02. " IRQPS[66] ,IRQ (MFS RX ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 01. " IRQPS[65] ,IRQ (MFS TX ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 00. " IRQPS[64] ,IRQ (MFS RX ch.9) preprocessed status bit" "No interrupt,Interrupt" line.long 0x0C "IRQPS3,IRC IRQ Preprocessed Status Register 3" bitfld.long 0x0C 27. " IRQPS[123] ,IRQ (Base timer ch.31) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 26. " IRQPS[122] ,IRQ (Base timer ch.30) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 25. " IRQPS[121] ,IRQ (Base timer ch.29) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 24. " IRQPS[120] ,IRQ (Base timer ch.28) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 23. " IRQPS[119] ,IRQBase timer ch.27) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 22. " IRQPS[118] ,IRQ (Base timer ch.26) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 21. " IRQPS[117] ,IRQ (Base timer ch.25) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 20. " IRQPS[116] ,IRQ (Base timer ch.24) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 19. " IRQPS[115] ,IRQ (Base timer ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 18. " IRQPS[114] ,IRQ (Base timer ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 17. " IRQPS[113] ,IRQ (Base timer ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 16. " IRQPS[112] ,IRQ (Base timer ch.16) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 15. " IRQPS[111] ,IRQ (Base timer ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 14. " IRQPS[110] ,IRQ (Base timer ch.14) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 13. " IRQPS[109] ,IRQ (Base timer ch.13) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 12. " IRQPS[108] ,IRQ (Base timer ch.12/20/21/22/23) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 11. " IRQPS[107] ,IRQ (Base timer ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 10. " IRQPS[106] ,IRQ (Base timer ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 09. " IRQPS[105] ,IRQ (Base timer ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 08. " IRQPS[104] ,IRQ (Base timer ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 07. " IRQPS[103] ,IRQ (Base timer ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 06. " IRQPS[102] ,IRQ (Base timer ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 05. " IRQPS[101] ,IRQ (Base timer ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 04. " IRQPS[100] ,IRQ (Base timer ch.0/8/9/10/11) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 03. " IRQPS[99] ,IRQ (CR CARIBRATION) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 02. " IRQPS[98] ,IRQ (RTC) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 01. " IRQPS[97] ,IRQ (Global timer (Compare clear interrupt)) preprocessed status bit" "No interrupt,Interrupt" line.long 0x10 "IRQPS4,IRC IRQ Preprocessed Status Register 4" bitfld.long 0x10 31. " IRQPS[159] ,IRQ (PCMPWM_OVFL/PCMPWM_UDRN/PCMPWM_DMAE) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 30. " IRQPS[158] ,IRQ (FRT ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 29. " IRQPS[157] ,IRQ (FRT ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 28. " IRQPS[156] ,IRQ (FRT ch.8) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 26. " IRQPS[154] ,IRQ (FRT ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 25. " IRQPS[153] ,IRQ (FRT ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 24. " IRQPS[152] ,IRQ (FRT ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 23. " IRQPS[151] ,IRQ (FRT ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 22. " IRQPS[150] ,IRQ (FRT ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 21. " IRQPS[149] ,IRQ (Reload timer ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 20. " IRQPS[148] ,IRQ (Reload timer ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 19. " IRQPS[147] ,IRQ (Reload timer ch.3) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 18. " IRQPS[146] ,IRQ (Reload timer ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 17. " IRQPS[145] ,IRQ (Reload timer ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 16. " IRQPS[144] ,IRQ (Reload timer ch.0) preprocessed status bit" "No interrupt,Interrupt" line.long 0x14 "IRQPS5,IRC IRQ Preprocessed Status Register 5" bitfld.long 0x14 29. " IRQPS[189] ,IRQ (QPRC ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 28. " IRQPS[188] ,IRQ (QPRC ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 27. " IRQPS[187] ,IRQ (IRQ1 of output compare 10 (ch.21)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 26. " IRQPS[186] ,IRQ1 of output compare 9 (ch.19)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 25. " IRQPS[185] ,IRQ (IRQ1 of output compare 8 (ch.17)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 23. " IRQPS[183] ,IRQ (IRQ1 of output compare 2 (ch.5)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 22. " IRQPS[182] ,IRQ (IRQ1 of output compare 1 (ch.3)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 21. " IRQPS[181] ,IRQ (IRQ1 of output compare 0 (ch.1)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 20. " IRQPS[180] ,IRQ (IRQ0 of output compare 10 (ch.20)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 19. " IRQPS[179] ,IRQ (IRQ0 of output compare 9 (ch.18)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 18. " IRQPS[178] ,IRQ (IRQ0 of output compare 8 (ch.16)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 16. " IRQPS[176] ,IRQ (IRQ0 of output compare 2 (ch.4)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " IRQPS[175] ,IRQ (IRQ0 of output compare 1 (ch.2)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 14. " IRQPS[174] ,IRQ (IRQ0 of output compare 0 (ch.0)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 13. " IRQPS[173] ,IRQ (IRQ1 of input capture 10 (ch.21)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 12. " IRQPS[172] ,IRQ (IRQ1 of input capture 9 (ch.19)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " IRQPS[171] ,IRQ (IRQ1 of input capture 8 (ch.17)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 10. " IRQPS[170] ,IRQ (IRQ1 of input capture 2 (ch.5)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 09. " IRQPS[169] ,IRQ (IRQ1 of input capture 1 (ch.3)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 08. " IRQPS[168] ,IRQ (IRQ1 of input capture 0 (ch.1)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 07. " IRQPS[167] ,IRQ (IRQ0 of input capture 10 (ch.20)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 06. " IRQPS[166] ,IRQ (IRQ0 of input capture 9 (ch.18)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 05. " IRQPS[165] ,IRQ (IRQ0 of input capture 8 (ch.16)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 04. " IRQPS[164] ,IRQ (IRQ0 of input capture 2 (ch.4)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 03. " IRQPS[163] ,IRQ (IRQ0 of input capture 1 (ch.2)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 02. " IRQPS[162] ,IRQ (IRQ0 of input capture 0 (ch.0)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 00. " IRQPS[160] ,IRQ (PCMPWM_DREQ) preprocessed status bit" "No interrupt,Interrupt" line.long 0x18 "IRQPS6,IRC IRQ Preprocessed Status Register 6" bitfld.long 0x18 31. " IRQPS[223] ,IRQ (MFS ch.1 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 30. " IRQPS[222] ,IRQ (MFS ch.0 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 29. " IRQPS[221] ,IRQ (PRGCRC) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 28. " IRQPS[220] ,IRQ (CR5 Performance Monitor Unit IRQ) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 27. " IRQPS[219] ,IRQ (SCT Sub OSC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 26. " IRQPS[218] ,IRQ (SCT Main OSC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 25. " IRQPS[217] ,IRQ (SCT SRC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 24. " IRQPS[216] ,IRQ (SCT RC IRQ) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 23. " IRQPS[215] ,IRQ (DMAC RLT (ch.0,1,2,3 OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 22. " IRQPS[214] ,IRQ (DMAC completion ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 21. " IRQPS[213] ,IRQ (DMAC completion ch.14) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 20. " IRQPS[212] ,IRQ (DMAC completion ch.13) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 19. " IRQPS[211] ,IRQ (DMAC completion ch.12) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 18. " IRQPS[210] ,IRQ (DMAC completion ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 17. " IRQPS[209] ,IRQ (DMAC completion ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 16. " IRQPS[208] ,IRQ (DMAC completion ch.9) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 15. " IRQPS[207] ,IRQ (DMAC completion ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 14. " IRQPS[206] ,IRQ (DMAC completion ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 13. " IRQPS[205] ,IRQ (DMAC completion ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 12. " IRQPS[204] ,IRQ (DMAC completion ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 11. " IRQPS[203] ,IRQ (DMAC completion ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 10. " IRQPS[202] ,IRQ (DMAC completion ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 09. " IRQPS[201] ,IRQ (DMAC completion ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 08. " IRQPS[200] ,IRQ (DMAC completion ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 07. " IRQPS[199] ,IRQ (DMAC completion ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 06. " IRQPS[198] ,IRQ (DMA error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 05. " IRQPS[197] ,IRQ (ADC12B0 RCO) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 04. " IRQPS[196] ,IRQ (ADC12B0 pulse detection function) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 03. " IRQPS[195] ,IRQ (ADC12B0 group interrupt) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 02. " IRQPS[194] ,IRQ (ADC12B0 conversion done) preprocessed status bit" "No interrupt,Interrupt" line.long 0x1C "IRQPS7,IRC IRQ Preprocessed Status Register 7" bitfld.long 0x1C 30. " IRQPS[254] ,IRQ (MX_DATA_REQ_IRQ4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 29. " IRQPS[253] ,IRQ (MX_DATA_REQ_IRQ3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 28. " IRQPS[252] ,IRQ (MX_DATA_REQ_IRQ2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 27. " IRQPS[251] ,IRQ (MX_DATA_REQ_IRQ1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 26. " IRQPS[250] ,IRQ (MX_DATA_REQ_IRQ0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 25. " IRQPS[249] ,IRQ (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 24. " IRQPS[248] ,IRQ (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 23. " IRQPS[247] ,IRQ (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 22. " IRQPS[246] ,IRQ (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 21. " IRQPS[245] ,IRQ (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 20. " IRQPS[244] ,IRQ (MX_AHB_ERR_IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 19. " IRQPS[243] ,IRQ (WG_END_IRQ4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 18. " IRQPS[242] ,IRQ (WG_END_IRQ3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 17. " IRQPS[241] ,IRQ (WG_END_IRQ2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 16. " IRQPS[240] ,IRQ (WG_END_IRQ1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 15. " IRQPS[239] ,IRQ (WG_END_IRQ0) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 14. " IRQPS[238] ,IRQ (WG_AHB_ERR_IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 13. " IRQPS[237] ,IRQ (I2S1_IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 12. " IRQPS[236] ,IRQ (I2S0_IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 09. " IRQPS[233] ,IRQ (MFS ch.11 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 08. " IRQPS[232] ,IRQ (MFS ch.10 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 07. " IRQPS[231] ,IRQ (MFS ch.9 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 06. " IRQPS[230] ,IRQ (MFS ch.8 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 05. " IRQPS[229] ,IRQ (MFS ch.7 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 04. " IRQPS[228] ,IRQ (MFS ch.6 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 03. " IRQPS[227] ,IRQ (MFS ch.5 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 02. " IRQPS[226] ,IRQ (MFS ch.4 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x1C 01. " IRQPS[225] ,IRQ (MFS ch.3 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x1C 00. " IRQPS[224] ,IRQ (MFS ch.2 error (Tx/Rx error, Status OR-ed)) preprocessed status bit" "No interrupt,Interrupt" tree.end newline group.long 0xD30++0x03 line.long 0x00 "UNLOCK,IRC Unlock Register" group.long 0xD40++0x03 line.long 0x00 "EEI,IRC ECC Error Interrupt Register" rbitfld.long 0x00 24. " EEIS ,ECC error IRQ status bit" "Not occurred,Occurred" bitfld.long 0x00 16. " EEIC ,ECC error IRQ clear bit" "No effect,Clear" rbitfld.long 0x00 8. " EENS ,ECC error NMI status bit" "Not occurred,Occurred" bitfld.long 0x00 0. " EENC ,ECC error NMI clear bit" "No effect,Clear" rgroup.long 0xD44++0x03 line.long 0x00 "EAN,IRC ECC Address Number Register" hexmask.long.byte 0x00 0.--7. 0x01 " EAN ,ECC error occurrence address bits" group.long 0xD48++0x0F line.long 0x00 "ET,IRC ECC Test Register" bitfld.long 0x00 0. " ET ,ECC test enable/disable setting bit" "Disabled,Enabled" line.long 0x04 "EEB0,IRC ECC Bit Register" bitfld.long 0x04 31. " EEB[29] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 30. " [28] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 29. " [27] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 28. " [26] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 27. " [25] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 26. " [24] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 25. " [23] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 24. " [22] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 23. " [21] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 22. " [19] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 21. " [18] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 20. " [17] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 19. " [16] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 18. " [15] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 16. " [14] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 15. " [13] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 14. " [12] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 13. " [11] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 12. " [10] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 11. " [9] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 10. " [8] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 9. " [7] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 8. " [6] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 7. " [5] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 6. " [4] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 5. " [3] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 4. " [2] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x04 3. " [1] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x04 2. " [0] ,ECC error occurrence bits" "Not inverted,Inverted" line.long 0x08 "EEB1,IRC ECC Bit Register" bitfld.long 0x08 31. " EEB[67] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 30. " [66] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 29. " [65] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 28. " [64] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 27. " [63] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 26. " [62] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 25. " [61] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 24. " [60] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 23. " [59] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 22. " [58] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 21. " [57] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 20. " [56] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 19. " [55] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 18. " [54] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 17. " [53] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 16. " [52] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 15. " [51] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 14. " [50] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 13. " [49] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 12. " [48] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 11. " [47] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 10. " [46] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 9. " [45] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 8. " [44] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 7. " [43] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 6. " [42] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 5. " [41] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 4. " [40] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x08 3. " [39] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x08 2. " [38] ,ECC error occurrence bits" "Not inverted,Inverted" line.long 0x0C "EEB2,IRC ECC Bit Register" bitfld.long 0x0C 14. " EEBO[73] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 13. " [72] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 12. " [71] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 11. " [70] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x0C 10. " [69] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 9. " [68] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 8. " [67] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 6. " [36] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x0C 5. " [35] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 4. " [34] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 3. " [33] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 2. " [32] ,ECC error occurrence bits" "Not inverted,Inverted" newline bitfld.long 0x0C 1. " [31] ,ECC error occurrence bits" "Not inverted,Inverted" bitfld.long 0x0C 0. " [30] ,ECC error occurrence bits" "Not inverted,Inverted" group.long 0xD3C++0x03 line.long 0x00 "IRQEEVA,IRC ECC Error Vector Address Register" width 15. base ad:0xFFFEE000 rgroup.long 0x00++0x03 "Register Memory Layout Of Interrupt Controller (HSEL2)" line.long 0x00 "IRC0_NMIVASBR,IRC NMI Vector Address Status Register" rgroup.long 0x1800++0x03 "Register Memory Layout Of Interrupt Controller (HSEL3)" line.long 0x00 "IRC_NMIVASBR,IRC NMI Vector Address Status Mirror Register" width 0x0B endif tree.end tree "TPU (TIME PROTECTION)" base ad:0xB0408000 width 13. group.long 0x00++0x03 line.long 0x00 "TPU0_UNLOCK,TPU Lock Release Register" rgroup.long 0x04++0x03 line.long 0x00 "TPU0_LST,TPU Lock Status Register" bitfld.long 0x00 0. " LST ,Lock status of the time" "Unlocked,Locked" group.long 0x08++0x03 line.long 0x00 "TPU0_CFG,TPU Configuration Register" bitfld.long 0x00 24. " DBGE ,Debug mode enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable/disable bit" "Disabled,Enabled" bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division setting bit" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" bitfld.long 0x00 0. " INTE ,Time protection unit interrupt enable setting bit" "Disabled,Enabled" rgroup.long 0x0C++0x07 line.long 0x00 "TPU0_TIR,TPU Timer Interrupt Request Register" bitfld.long 0x00 7. " IR[7] ,Timer 7 interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 6. " IR[6] ,Timer 6 interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 5. " IR[5] ,Timer 5 interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 4. " IR[4] ,Timer 4 interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " IR[3] ,Timer 3 interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 2. " IR[2] ,Timer 2 interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 1. " IR[1] ,Timer 1 interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 0. " IR[0] ,Timer 0 interrupt request bit" "No interrupt,Interrupt" line.long 0x04 "TPU0_TST,TPU Timer Status Register" bitfld.long 0x04 7. " ST[7] ,Timer 7 status bit" "Stopped,Running" bitfld.long 0x04 6. " ST[6] ,Timer 6 status bit" "Stopped,Running" bitfld.long 0x04 5. " ST[5] ,Timer 5 status bit" "Stopped,Running" bitfld.long 0x04 4. " ST[4] ,Timer 4 status bit" "Stopped,Running" newline bitfld.long 0x04 3. " ST[3] ,Timer 3 status bit" "Stopped,Running" bitfld.long 0x04 2. " ST[2] ,Timer 2 status bit" "Stopped,Running" bitfld.long 0x04 1. " ST[1] ,Timer 1 status bit" "Stopped,Running" bitfld.long 0x04 0. " ST[0] ,Timer 0 status bit" "Stopped,Running" group.long 0x14++0x03 line.long 0x00 "TPU0_TIE,TPU Timer Interrupt Enable Register" bitfld.long 0x00 7. " IE[7] ,Timer 7 interrupt enable setting bit" "Disabled,Enabled" bitfld.long 0x00 6. " IE[6] ,Timer 6 interrupt enable setting bit" "Disabled,Enabled" bitfld.long 0x00 5. " IE[5] ,Timer 5 interrupt enable setting bit" "Disabled,Enabled" bitfld.long 0x00 4. " IE[4] ,Timer 4 interrupt enable setting bit" "Disabled,Enabled" newline bitfld.long 0x00 3. " IE[3] ,Timer 3 interrupt enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " IE[2] ,Timer 2 interrupt enable setting bit" "Disabled,Enabled" bitfld.long 0x00 1. " IE[1] ,Timer 1 interrupt enable setting bit" "Disabled,Enabled" bitfld.long 0x00 0. " IE[0] ,Timer 0 interrupt enable setting bit" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "TPU0_TCN00,TPU Timer 0 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x34++0x03 line.long 0x00 "TPU0_TCN01,TPU Timer 1 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x38++0x03 line.long 0x00 "TPU0_TCN02,TPU Timer 2 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x3C++0x03 line.long 0x00 "TPU0_TCN03,TPU Timer 3 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x40++0x03 line.long 0x00 "TPU0_TCN04,TPU Timer 4 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x44++0x03 line.long 0x00 "TPU0_TCN05,TPU Timer 5 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x48++0x03 line.long 0x00 "TPU0_TCN06,TPU Timer 6 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x4C++0x03 line.long 0x00 "TPU0_TCN07,TPU Timer 7 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart" newline bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable" bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits" group.long 0x50++0x03 line.long 0x00 "TPU0_TCN10,TPU Timer 0 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x54++0x03 line.long 0x00 "TPU0_TCN11,TPU Timer 1 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x58++0x03 line.long 0x00 "TPU0_TCN12,TPU Timer 2 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x5C++0x03 line.long 0x00 "TPU0_TCN13,TPU Timer 3 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x60++0x03 line.long 0x00 "TPU0_TCN14,TPU Timer 4 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x64++0x03 line.long 0x00 "TPU0_TCN15,TPU Timer 5 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x68++0x03 line.long 0x00 "TPU0_TCN16,TPU Timer 6 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" group.long 0x6C++0x03 line.long 0x00 "TPU0_TCN17,TPU Timer 7 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16" rgroup.long 0x70++0x03 line.long 0x00 "TPU0_TCC0,TPU Timer 0 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x74++0x03 line.long 0x00 "TPU0_TCC1,TPU Timer 1 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x78++0x03 line.long 0x00 "TPU0_TCC2,TPU Timer 2 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x7C++0x03 line.long 0x00 "TPU0_TCC3,TPU Timer 3 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x80++0x03 line.long 0x00 "TPU0_TCC4,TPU Timer 4 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x84++0x03 line.long 0x00 "TPU0_TCC5,TPU Timer 5 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x88++0x03 line.long 0x00 "TPU0_TCC6,TPU Timer 6 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" rgroup.long 0x8C++0x03 line.long 0x00 "TPU0_TCC7,TPU Timer 7 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits" width 0x0B tree.end tree "SECURITY" base ad:0xB0411300 width 9. if (((per.l(ad:0xB0411300+0xC0))&0x01)==0x00) rgroup.long 0xC0++0x03 line.long 0x00 "SECSTAT,Security Status Register" bitfld.long 0x00 19. " TBOSEC ,ECC single error correction in TBO data" "No error,Error" bitfld.long 0x00 18. " TBODED ,ECC double error detection in TBO data" "No error,Error" bitfld.long 0x00 17. " ECCSEC ,ECC single error correction when fetching security marker" "No error,Error" bitfld.long 0x00 16. " ECCDED ,ECC double error detection when fetching security marker" "No error,Error" newline bitfld.long 0x00 8. " UMV ,Specification of the unlock marker value" "Non-trivial,Trivial" bitfld.long 0x00 5. " SFDONE ,Security fetch done register" "Ongoing,Finished" bitfld.long 0x00 4. " SWPOE ,Sector write permission overwrite enable register" "Disabled,Enabled" bitfld.long 0x00 3. " SECOE ,Security overwrite enable register" "Disabled,Enabled" newline bitfld.long 0x00 2. " CEEN ,Chip erase enable register" "Disabled,Enabled" textfld " " bitfld.long 0x00 0. " SECEN ,Security enable register" "Disabled,Enabled" else rgroup.long 0xC0++0x03 line.long 0x00 "SECSTAT,Security Status Register" bitfld.long 0x00 19. " TBOSEC ,ECC single error correction in TBO data" "No error,Error" bitfld.long 0x00 18. " TBODED ,ECC double error detection in TBO data" "No error,Error" bitfld.long 0x00 17. " ECCSEC ,ECC single Error correction when fetching security marker" "No error,Error" bitfld.long 0x00 16. " ECCDED ,ECC double error detection when fetching security marker" "No error,Error" newline bitfld.long 0x00 8. " UMV ,Specification of the unlock marker value" "Non-trivial,Trivial" bitfld.long 0x00 5. " SFDONE ,Security fetch done register" "Ongoing,Finished" bitfld.long 0x00 4. " SWPOE ,Sector write permission overwrite enable register" "Disabled,Enabled" bitfld.long 0x00 3. " SECOE ,Security overwrite enable register" "Disabled,Enabled" newline bitfld.long 0x00 2. " CEEN ,Chip erase enable register" "Disabled,Enabled" bitfld.long 0x00 1. " SECSC ,Security scope register" "Flash,Device" bitfld.long 0x00 0. " SECEN ,Security enable register" "Disabled,Enabled" endif group.long 0xC4++0x13 line.long 0x00 "SER,Security Enable Register" line.long 0x04 "SSR,Security Scope Register" line.long 0x08 "CEER,Chip Erase Enable Register" line.long 0x0C "SOER,Security Overwrite Enable Register" line.long 0x10 "SWPOER,Sector Write Permission Overwrite Enable Register" group.long 0x40++0x07 line.long 0x00 "WSWP0,Work Flash Sector Write Permissions Register 0" bitfld.long 0x00 31. " WSWP_[31] ,Work flash sector write permission SA31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Work flash sector write permission SA30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Work flash sector write permission SA29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Work flash sector write permission SA28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Work flash sector write permission SA27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Work flash sector write permission SA26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Work flash sector write permission SA25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Work flash sector write permission SA24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Work flash sector write permission SA23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Work flash sector write permission SA22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Work flash sector write permission SA21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Work flash sector write permission SA20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Work flash sector write permission SA19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Work flash sector write permission SA18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Work flash sector write permission SA17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Work flash sector write permission SA16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Work flash sector write permission SA15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Work flash sector write permission SA14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Work flash sector write permission SA13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Work flash sector write permission SA12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Work flash sector write permission SA11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Work flash sector write permission SA10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Work flash sector write permission SA9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Work flash sector write permission SA8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Work flash sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Work flash sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Work flash sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Work flash sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Work flash sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Work flash sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Work flash sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Work flash sector write permission SA0" "Disabled,Enabled" line.long 0x04 "WSWP1,Work Flash Sector Write Permissions Register 1" bitfld.long 0x04 31. " WSWP_[63] ,Work flash sector write permission SA63" "Disabled,Enabled" bitfld.long 0x04 30. " [62] ,Work flash sector write permission SA62" "Disabled,Enabled" bitfld.long 0x04 29. " [61] ,Work flash sector write permission SA61" "Disabled,Enabled" bitfld.long 0x04 28. " [60] ,Work flash sector write permission SA60" "Disabled,Enabled" newline bitfld.long 0x04 27. " [59] ,Work flash sector write permission SA59" "Disabled,Enabled" bitfld.long 0x04 26. " [58] ,Work flash sector write permission SA58" "Disabled,Enabled" bitfld.long 0x04 25. " [57] ,Work flash sector write permission SA57" "Disabled,Enabled" bitfld.long 0x04 24. " [56] ,Work flash sector write permission SA56" "Disabled,Enabled" newline bitfld.long 0x04 23. " [55] ,Work flash sector write permission SA55" "Disabled,Enabled" bitfld.long 0x04 22. " [54] ,Work flash sector write permission SA54" "Disabled,Enabled" bitfld.long 0x04 21. " [53] ,Work flash sector write permission SA53" "Disabled,Enabled" bitfld.long 0x04 20. " [52] ,Work flash sector write permission SA52" "Disabled,Enabled" newline bitfld.long 0x04 19. " [51] ,Work flash sector write permission SA51" "Disabled,Enabled" bitfld.long 0x04 18. " [50] ,Work flash sector write permission SA50" "Disabled,Enabled" bitfld.long 0x04 17. " [49] ,Work flash sector write permission SA49" "Disabled,Enabled" bitfld.long 0x04 16. " [48] ,Work flash sector write permission SA48" "Disabled,Enabled" newline bitfld.long 0x04 15. " [47] ,Work flash sector write permission SA47" "Disabled,Enabled" bitfld.long 0x04 14. " [46] ,Work flash sector write permission SA46" "Disabled,Enabled" bitfld.long 0x04 13. " [45] ,Work flash sector write permission SA45" "Disabled,Enabled" bitfld.long 0x04 12. " [44] ,Work flash sector write permission SA44" "Disabled,Enabled" newline bitfld.long 0x04 11. " [43] ,Work flash sector write permission SA43" "Disabled,Enabled" bitfld.long 0x04 10. " [42] ,Work flash sector write permission SA42" "Disabled,Enabled" bitfld.long 0x04 9. " [41] ,Work flash sector write permission SA41" "Disabled,Enabled" bitfld.long 0x04 8. " [40] ,Work flash sector write permission SA40" "Disabled,Enabled" newline bitfld.long 0x04 7. " [39] ,Work flash sector write permission SA39" "Disabled,Enabled" bitfld.long 0x04 6. " [38] ,Work flash sector write permission SA38" "Disabled,Enabled" bitfld.long 0x04 5. " [37] ,Work flash sector write permission SA37" "Disabled,Enabled" bitfld.long 0x04 4. " [36] ,Work flash sector write permission SA36" "Disabled,Enabled" newline bitfld.long 0x04 3. " [35] ,Work flash sector write permission SA35" "Disabled,Enabled" bitfld.long 0x04 2. " [34] ,Work flash sector write permission SA34" "Disabled,Enabled" bitfld.long 0x04 1. " [33] ,Work flash sector write permission SA33" "Disabled,Enabled" bitfld.long 0x04 0. " [32] ,Work flash sector write permission SA32" "Disabled,Enabled" group.long 0xDC++0x03 line.long 0x00 "CSWP0,Code Flash Small Sector Write Permissions Register 0" bitfld.long 0x00 31. " F3SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 30. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 29. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 28. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 27. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 26. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 25. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 24. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" newline bitfld.long 0x00 23. " F2SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" newline bitfld.long 0x00 15. " F1SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 11. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" newline bitfld.long 0x00 7. " F0SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" group.long 0x80++0x1F line.long 0x00 "CSWP1,Code Flash Large Sector Write Permissions Register 1" bitfld.long 0x00 31. " SWP_[39] ,Work flash large sector write permission SA39" "Disabled,Enabled" bitfld.long 0x00 30. " [38] ,Work flash large sector write permission SA38" "Disabled,Enabled" bitfld.long 0x00 29. " [37] ,Work flash large sector write permission SA37" "Disabled,Enabled" bitfld.long 0x00 28. " [36] ,Work flash large sector write permission SA36" "Disabled,Enabled" newline bitfld.long 0x00 27. " [35] ,Work flash large sector write permission SA35" "Disabled,Enabled" bitfld.long 0x00 26. " [34] ,Work flash large sector write permission SA34" "Disabled,Enabled" bitfld.long 0x00 25. " [33] ,Work flash large sector write permission SA33" "Disabled,Enabled" bitfld.long 0x00 24. " [32] ,Work flash large sector write permission SA32" "Disabled,Enabled" newline bitfld.long 0x00 23. " [31] ,Work flash large sector write permission SA31" "Disabled,Enabled" bitfld.long 0x00 22. " [30] ,Work flash large sector write permission SA30" "Disabled,Enabled" bitfld.long 0x00 21. " [29] ,Work flash large sector write permission SA29" "Disabled,Enabled" bitfld.long 0x00 20. " [28] ,Work flash large sector write permission SA28" "Disabled,Enabled" newline bitfld.long 0x00 19. " [27] ,Work flash large sector write permission SA27" "Disabled,Enabled" bitfld.long 0x00 18. " [26] ,Work flash large sector write permission SA26" "Disabled,Enabled" bitfld.long 0x00 17. " [25] ,Work flash large sector write permission SA25" "Disabled,Enabled" bitfld.long 0x00 16. " [24] ,Work flash large sector write permission SA24" "Disabled,Enabled" newline bitfld.long 0x00 15. " [23] ,Work flash large sector write permission SA23" "Disabled,Enabled" bitfld.long 0x00 14. " [22] ,Work flash large sector write permission SA22" "Disabled,Enabled" bitfld.long 0x00 13. " [21] ,Work flash large sector write permission SA21" "Disabled,Enabled" bitfld.long 0x00 12. " [20] ,Work flash large sector write permission SA20" "Disabled,Enabled" newline bitfld.long 0x00 11. " [19] ,Work flash large sector write permission SA19" "Disabled,Enabled" bitfld.long 0x00 10. " [18] ,Work flash large sector write permission SA18" "Disabled,Enabled" bitfld.long 0x00 9. " [17] ,Work flash large sector write permission SA17" "Disabled,Enabled" bitfld.long 0x00 8. " [16] ,Work flash large sector write permission SA16" "Disabled,Enabled" newline bitfld.long 0x00 7. " [15] ,Work flash large sector write permission SA15" "Disabled,Enabled" bitfld.long 0x00 6. " [14] ,Work flash large sector write permission SA14" "Disabled,Enabled" bitfld.long 0x00 5. " [13] ,Work flash large sector write permission SA13" "Disabled,Enabled" bitfld.long 0x00 4. " [12] ,Work flash large sector write permission SA12" "Disabled,Enabled" newline bitfld.long 0x00 3. " [11] ,Work flash large sector write permission SA11" "Disabled,Enabled" bitfld.long 0x00 2. " [10] ,Work flash large sector write permission SA10" "Disabled,Enabled" bitfld.long 0x00 1. " [9] ,Work flash large sector write permission SA9" "Disabled,Enabled" bitfld.long 0x00 0. " [8] ,Work flash large sector write permission SA8" "Disabled,Enabled" line.long 0x04 "CSWP2,Code Flash Large Sector Write Permissions Register 2" bitfld.long 0x04 31. " SWP_[71] ,Work flash large sector write permission SA71" "Disabled,Enabled" bitfld.long 0x04 30. " [70] ,Work flash large sector write permission SA70" "Disabled,Enabled" bitfld.long 0x04 29. " [69] ,Work flash large sector write permission SA69" "Disabled,Enabled" bitfld.long 0x04 28. " [68] ,Work flash large sector write permission SA68" "Disabled,Enabled" newline bitfld.long 0x04 27. " [67] ,Work flash large sector write permission SA67" "Disabled,Enabled" bitfld.long 0x04 26. " [66] ,Work flash large sector write permission SA66" "Disabled,Enabled" bitfld.long 0x04 25. " [65] ,Work flash large sector write permission SA65" "Disabled,Enabled" bitfld.long 0x04 24. " [64] ,Work flash large sector write permission SA64" "Disabled,Enabled" newline bitfld.long 0x04 23. " [63] ,Work flash large sector write permission SA63" "Disabled,Enabled" bitfld.long 0x04 22. " [62] ,Work flash large sector write permission SA62" "Disabled,Enabled" bitfld.long 0x04 21. " [61] ,Work flash large sector write permission SA61" "Disabled,Enabled" bitfld.long 0x04 20. " [60] ,Work flash large sector write permission SA60" "Disabled,Enabled" newline bitfld.long 0x04 19. " [59] ,Work flash large sector write permission SA59" "Disabled,Enabled" bitfld.long 0x04 18. " [58] ,Work flash large sector write permission SA58" "Disabled,Enabled" bitfld.long 0x04 17. " [57] ,Work flash large sector write permission SA57" "Disabled,Enabled" bitfld.long 0x04 16. " [56] ,Work flash large sector write permission SA56" "Disabled,Enabled" newline bitfld.long 0x04 15. " [55] ,Work flash large sector write permission SA55" "Disabled,Enabled" bitfld.long 0x04 14. " [54] ,Work flash large sector write permission SA54" "Disabled,Enabled" bitfld.long 0x04 13. " [53] ,Work flash large sector write permission SA53" "Disabled,Enabled" bitfld.long 0x04 12. " [52] ,Work flash large sector write permission SA52" "Disabled,Enabled" newline bitfld.long 0x04 11. " [51] ,Work flash large sector write permission SA51" "Disabled,Enabled" bitfld.long 0x04 10. " [50] ,Work flash large sector write permission SA50" "Disabled,Enabled" bitfld.long 0x04 9. " [49] ,Work flash large sector write permission SA49" "Disabled,Enabled" bitfld.long 0x04 8. " [48] ,Work flash large sector write permission SA48" "Disabled,Enabled" newline bitfld.long 0x04 7. " [47] ,Work flash large sector write permission SA47" "Disabled,Enabled" bitfld.long 0x04 6. " [46] ,Work flash large sector write permission SA46" "Disabled,Enabled" bitfld.long 0x04 5. " [45] ,Work flash large sector write permission SA45" "Disabled,Enabled" bitfld.long 0x04 4. " [44] ,Work flash large sector write permission SA44" "Disabled,Enabled" newline bitfld.long 0x04 3. " [43] ,Work flash large sector write permission SA43" "Disabled,Enabled" bitfld.long 0x04 2. " [42] ,Work flash large sector write permission SA42" "Disabled,Enabled" bitfld.long 0x04 1. " [41] ,Work flash large sector write permission SA41" "Disabled,Enabled" bitfld.long 0x04 0. " [40] ,Work flash large sector write permission SA40" "Disabled,Enabled" line.long 0x08 "CSWP3,Code Flash Large Sector Write Permissions Register 3" bitfld.long 0x08 31. " SWP_[103] ,Work flash large sector write permission SA103" "Disabled,Enabled" bitfld.long 0x08 30. " [102] ,Work flash large sector write permission SA102" "Disabled,Enabled" bitfld.long 0x08 29. " [101] ,Work flash large sector write permission SA101" "Disabled,Enabled" bitfld.long 0x08 28. " [100] ,Work flash large sector write permission SA100" "Disabled,Enabled" newline bitfld.long 0x08 27. " [99] ,Work flash large sector write permission SA99" "Disabled,Enabled" bitfld.long 0x08 26. " [98] ,Work flash large sector write permission SA98" "Disabled,Enabled" bitfld.long 0x08 25. " [97] ,Work flash large sector write permission SA97" "Disabled,Enabled" bitfld.long 0x08 24. " [96] ,Work flash large sector write permission SA96" "Disabled,Enabled" newline bitfld.long 0x08 23. " [95] ,Work flash large sector write permission SA95" "Disabled,Enabled" bitfld.long 0x08 22. " [94] ,Work flash large sector write permission SA94" "Disabled,Enabled" bitfld.long 0x08 21. " [93] ,Work flash large sector write permission SA93" "Disabled,Enabled" bitfld.long 0x08 20. " [92] ,Work flash large sector write permission SA92" "Disabled,Enabled" newline bitfld.long 0x08 19. " [91] ,Work flash large sector write permission SA91" "Disabled,Enabled" bitfld.long 0x08 18. " [90] ,Work flash large sector write permission SA90" "Disabled,Enabled" bitfld.long 0x08 17. " [89] ,Work flash large sector write permission SA89" "Disabled,Enabled" bitfld.long 0x08 16. " [88] ,Work flash large sector write permission SA88" "Disabled,Enabled" newline bitfld.long 0x08 15. " [87] ,Work flash large sector write permission SA87" "Disabled,Enabled" bitfld.long 0x08 14. " [86] ,Work flash large sector write permission SA86" "Disabled,Enabled" bitfld.long 0x08 13. " [85] ,Work flash large sector write permission SA85" "Disabled,Enabled" bitfld.long 0x08 12. " [84] ,Work flash large sector write permission SA84" "Disabled,Enabled" newline bitfld.long 0x08 11. " [83] ,Work flash large sector write permission SA83" "Disabled,Enabled" bitfld.long 0x08 10. " [82] ,Work flash large sector write permission SA82" "Disabled,Enabled" bitfld.long 0x08 9. " [81] ,Work flash large sector write permission SA81" "Disabled,Enabled" bitfld.long 0x08 8. " [80] ,Work flash large sector write permission SA80" "Disabled,Enabled" newline bitfld.long 0x08 7. " [79] ,Work flash large sector write permission SA79" "Disabled,Enabled" bitfld.long 0x08 6. " [78] ,Work flash large sector write permission SA78" "Disabled,Enabled" bitfld.long 0x08 5. " [77] ,Work flash large sector write permission SA77" "Disabled,Enabled" bitfld.long 0x08 4. " [76] ,Work flash large sector write permission SA76" "Disabled,Enabled" newline bitfld.long 0x08 3. " [75] ,Work flash large sector write permission SA75" "Disabled,Enabled" bitfld.long 0x08 2. " [74] ,Work flash large sector write permission SA74" "Disabled,Enabled" bitfld.long 0x08 1. " [73] ,Work flash large sector write permission SA73" "Disabled,Enabled" bitfld.long 0x08 0. " [72] ,Work flash large sector write permission SA72" "Disabled,Enabled" line.long 0x0C "CSWP4,Code Flash Large Sector Write Permissions Register 4" bitfld.long 0x0C 31. " SWP_[135] ,Work flash large sector write permission SA135" "Disabled,Enabled" bitfld.long 0x0C 30. " [134] ,Work flash large sector write permission SA134" "Disabled,Enabled" bitfld.long 0x0C 29. " [133] ,Work flash large sector write permission SA133" "Disabled,Enabled" bitfld.long 0x0C 28. " [132] ,Work flash large sector write permission SA132" "Disabled,Enabled" newline bitfld.long 0x0C 27. " [131] ,Work flash large sector write permission SA131" "Disabled,Enabled" bitfld.long 0x0C 26. " [130] ,Work flash large sector write permission SA130" "Disabled,Enabled" bitfld.long 0x0C 25. " [129] ,Work flash large sector write permission SA129" "Disabled,Enabled" bitfld.long 0x0C 24. " [128] ,Work flash large sector write permission SA128" "Disabled,Enabled" newline bitfld.long 0x0C 23. " [127] ,Work flash large sector write permission SA127" "Disabled,Enabled" bitfld.long 0x0C 22. " [126] ,Work flash large sector write permission SA126" "Disabled,Enabled" bitfld.long 0x0C 21. " [125] ,Work flash large sector write permission SA125" "Disabled,Enabled" bitfld.long 0x0C 20. " [124] ,Work flash large sector write permission SA124" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [123] ,Work flash large sector write permission SA123" "Disabled,Enabled" bitfld.long 0x0C 18. " [122] ,Work flash large sector write permission SA122" "Disabled,Enabled" bitfld.long 0x0C 17. " [121] ,Work flash large sector write permission SA121" "Disabled,Enabled" bitfld.long 0x0C 16. " [120] ,Work flash large sector write permission SA120" "Disabled,Enabled" newline bitfld.long 0x0C 15. " [119] ,Work flash large sector write permission SA119" "Disabled,Enabled" bitfld.long 0x0C 14. " [118] ,Work flash large sector write permission SA118" "Disabled,Enabled" bitfld.long 0x0C 13. " [117] ,Work flash large sector write permission SA117" "Disabled,Enabled" bitfld.long 0x0C 12. " [116] ,Work flash large sector write permission SA116" "Disabled,Enabled" newline bitfld.long 0x0C 11. " [115] ,Work flash large sector write permission SA115" "Disabled,Enabled" bitfld.long 0x0C 10. " [114] ,Work flash large sector write permission SA114" "Disabled,Enabled" bitfld.long 0x0C 9. " [113] ,Work flash large sector write permission SA113" "Disabled,Enabled" bitfld.long 0x0C 8. " [112] ,Work flash large sector write permission SA112" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [111] ,Work flash large sector write permission SA111" "Disabled,Enabled" bitfld.long 0x0C 6. " [110] ,Work flash large sector write permission SA110" "Disabled,Enabled" bitfld.long 0x0C 5. " [109] ,Work flash large sector write permission SA109" "Disabled,Enabled" bitfld.long 0x0C 4. " [108] ,Work flash large sector write permission SA108" "Disabled,Enabled" newline bitfld.long 0x0C 3. " [107] ,Work flash large sector write permission SA107" "Disabled,Enabled" bitfld.long 0x0C 2. " [106] ,Work flash large sector write permission SA106" "Disabled,Enabled" bitfld.long 0x0C 1. " [105] ,Work flash large sector write permission SA105" "Disabled,Enabled" bitfld.long 0x0C 0. " [104] ,Work flash large sector write permission SA104" "Disabled,Enabled" line.long 0x10 "CSWP5,Code Flash Large Sector Write Permissions Register 5" bitfld.long 0x10 31. " SWP_[39] ,Work flash large sector write permission SA39" "Disabled,Enabled" bitfld.long 0x10 30. " [38] ,Work flash large sector write permission SA38" "Disabled,Enabled" bitfld.long 0x10 29. " [37] ,Work flash large sector write permission SA37" "Disabled,Enabled" bitfld.long 0x10 28. " [36] ,Work flash large sector write permission SA36" "Disabled,Enabled" newline bitfld.long 0x10 27. " [35] ,Work flash large sector write permission SA35" "Disabled,Enabled" bitfld.long 0x10 26. " [34] ,Work flash large sector write permission SA34" "Disabled,Enabled" bitfld.long 0x10 25. " [33] ,Work flash large sector write permission SA33" "Disabled,Enabled" bitfld.long 0x10 24. " [32] ,Work flash large sector write permission SA32" "Disabled,Enabled" newline bitfld.long 0x10 23. " [31] ,Work flash large sector write permission SA31" "Disabled,Enabled" bitfld.long 0x10 22. " [30] ,Work flash large sector write permission SA30" "Disabled,Enabled" bitfld.long 0x10 21. " [29] ,Work flash large sector write permission SA29" "Disabled,Enabled" bitfld.long 0x10 20. " [28] ,Work flash large sector write permission SA28" "Disabled,Enabled" newline bitfld.long 0x10 19. " [27] ,Work flash large sector write permission SA27" "Disabled,Enabled" bitfld.long 0x10 18. " [26] ,Work flash large sector write permission SA26" "Disabled,Enabled" bitfld.long 0x10 17. " [25] ,Work flash large sector write permission SA25" "Disabled,Enabled" bitfld.long 0x10 16. " [24] ,Work flash large sector write permission SA24" "Disabled,Enabled" newline bitfld.long 0x10 15. " [23] ,Work flash large sector write permission SA23" "Disabled,Enabled" bitfld.long 0x10 14. " [22] ,Work flash large sector write permission SA22" "Disabled,Enabled" bitfld.long 0x10 13. " [21] ,Work flash large sector write permission SA21" "Disabled,Enabled" bitfld.long 0x10 12. " [20] ,Work flash large sector write permission SA20" "Disabled,Enabled" newline bitfld.long 0x10 11. " [19] ,Work flash large sector write permission SA19" "Disabled,Enabled" bitfld.long 0x10 10. " [18] ,Work flash large sector write permission SA18" "Disabled,Enabled" bitfld.long 0x10 9. " [17] ,Work flash large sector write permission SA17" "Disabled,Enabled" bitfld.long 0x10 8. " [16] ,Work flash large sector write permission SA16" "Disabled,Enabled" newline bitfld.long 0x10 7. " [15] ,Work flash large sector write permission SA15" "Disabled,Enabled" bitfld.long 0x10 6. " [14] ,Work flash large sector write permission SA14" "Disabled,Enabled" bitfld.long 0x10 5. " [13] ,Work flash large sector write permission SA13" "Disabled,Enabled" bitfld.long 0x10 4. " [12] ,Work flash large sector write permission SA12" "Disabled,Enabled" newline bitfld.long 0x10 3. " [11] ,Work flash large sector write permission SA11" "Disabled,Enabled" bitfld.long 0x10 2. " [10] ,Work flash large sector write permission SA10" "Disabled,Enabled" bitfld.long 0x10 1. " [9] ,Work flash large sector write permission SA9" "Disabled,Enabled" bitfld.long 0x10 0. " [8] ,Work flash large sector write permission SA8" "Disabled,Enabled" line.long 0x14 "CSWP6,Code Flash Large Sector Write Permissions Register 6" bitfld.long 0x14 31. " SWP_[71] ,Work flash large sector write permission SA71" "Disabled,Enabled" bitfld.long 0x14 30. " [70] ,Work flash large sector write permission SA70" "Disabled,Enabled" bitfld.long 0x14 29. " [69] ,Work flash large sector write permission SA69" "Disabled,Enabled" bitfld.long 0x14 28. " [68] ,Work flash large sector write permission SA68" "Disabled,Enabled" newline bitfld.long 0x14 27. " [67] ,Work flash large sector write permission SA67" "Disabled,Enabled" bitfld.long 0x14 26. " [66] ,Work flash large sector write permission SA66" "Disabled,Enabled" bitfld.long 0x14 25. " [65] ,Work flash large sector write permission SA65" "Disabled,Enabled" bitfld.long 0x14 24. " [64] ,Work flash large sector write permission SA64" "Disabled,Enabled" newline bitfld.long 0x14 23. " [63] ,Work flash large sector write permission SA63" "Disabled,Enabled" bitfld.long 0x14 22. " [62] ,Work flash large sector write permission SA62" "Disabled,Enabled" bitfld.long 0x14 21. " [61] ,Work flash large sector write permission SA61" "Disabled,Enabled" bitfld.long 0x14 20. " [60] ,Work flash large sector write permission SA60" "Disabled,Enabled" newline bitfld.long 0x14 19. " [59] ,Work flash large sector write permission SA59" "Disabled,Enabled" bitfld.long 0x14 18. " [58] ,Work flash large sector write permission SA58" "Disabled,Enabled" bitfld.long 0x14 17. " [57] ,Work flash large sector write permission SA57" "Disabled,Enabled" bitfld.long 0x14 16. " [56] ,Work flash large sector write permission SA56" "Disabled,Enabled" newline bitfld.long 0x14 15. " [55] ,Work flash large sector write permission SA55" "Disabled,Enabled" bitfld.long 0x14 14. " [54] ,Work flash large sector write permission SA54" "Disabled,Enabled" bitfld.long 0x14 13. " [53] ,Work flash large sector write permission SA53" "Disabled,Enabled" bitfld.long 0x14 12. " [52] ,Work flash large sector write permission SA52" "Disabled,Enabled" newline bitfld.long 0x14 11. " [51] ,Work flash large sector write permission SA51" "Disabled,Enabled" bitfld.long 0x14 10. " [50] ,Work flash large sector write permission SA50" "Disabled,Enabled" bitfld.long 0x14 9. " [49] ,Work flash large sector write permission SA49" "Disabled,Enabled" bitfld.long 0x14 8. " [48] ,Work flash large sector write permission SA48" "Disabled,Enabled" newline bitfld.long 0x14 7. " [47] ,Work flash large sector write permission SA47" "Disabled,Enabled" bitfld.long 0x14 6. " [46] ,Work flash large sector write permission SA46" "Disabled,Enabled" bitfld.long 0x14 5. " [45] ,Work flash large sector write permission SA45" "Disabled,Enabled" bitfld.long 0x14 4. " [44] ,Work flash large sector write permission SA44" "Disabled,Enabled" newline bitfld.long 0x14 3. " [43] ,Work flash large sector write permission SA43" "Disabled,Enabled" bitfld.long 0x14 2. " [42] ,Work flash large sector write permission SA42" "Disabled,Enabled" bitfld.long 0x14 1. " [41] ,Work flash large sector write permission SA41" "Disabled,Enabled" bitfld.long 0x14 0. " [40] ,Work flash large sector write permission SA40" "Disabled,Enabled" line.long 0x18 "CSWP7,Code Flash Large Sector Write Permissions Register 7" bitfld.long 0x18 31. " SWP_[103] ,Work flash large sector write permission SA103" "Disabled,Enabled" bitfld.long 0x18 30. " [102] ,Work flash large sector write permission SA102" "Disabled,Enabled" bitfld.long 0x18 29. " [101] ,Work flash large sector write permission SA101" "Disabled,Enabled" bitfld.long 0x18 28. " [100] ,Work flash large sector write permission SA100" "Disabled,Enabled" newline bitfld.long 0x18 27. " [99] ,Work flash large sector write permission SA99" "Disabled,Enabled" bitfld.long 0x18 26. " [98] ,Work flash large sector write permission SA98" "Disabled,Enabled" bitfld.long 0x18 25. " [97] ,Work flash large sector write permission SA97" "Disabled,Enabled" bitfld.long 0x18 24. " [96] ,Work flash large sector write permission SA96" "Disabled,Enabled" newline bitfld.long 0x18 23. " [95] ,Work flash large sector write permission SA95" "Disabled,Enabled" bitfld.long 0x18 22. " [94] ,Work flash large sector write permission SA94" "Disabled,Enabled" bitfld.long 0x18 21. " [93] ,Work flash large sector write permission SA93" "Disabled,Enabled" bitfld.long 0x18 20. " [92] ,Work flash large sector write permission SA92" "Disabled,Enabled" newline bitfld.long 0x18 19. " [91] ,Work flash large sector write permission SA91" "Disabled,Enabled" bitfld.long 0x18 18. " [90] ,Work flash large sector write permission SA90" "Disabled,Enabled" bitfld.long 0x18 17. " [89] ,Work flash large sector write permission SA89" "Disabled,Enabled" bitfld.long 0x18 16. " [88] ,Work flash large sector write permission SA88" "Disabled,Enabled" newline bitfld.long 0x18 15. " [87] ,Work flash large sector write permission SA87" "Disabled,Enabled" bitfld.long 0x18 14. " [86] ,Work flash large sector write permission SA86" "Disabled,Enabled" bitfld.long 0x18 13. " [85] ,Work flash large sector write permission SA85" "Disabled,Enabled" bitfld.long 0x18 12. " [84] ,Work flash large sector write permission SA84" "Disabled,Enabled" newline bitfld.long 0x18 11. " [83] ,Work flash large sector write permission SA83" "Disabled,Enabled" bitfld.long 0x18 10. " [82] ,Work flash large sector write permission SA82" "Disabled,Enabled" bitfld.long 0x18 9. " [81] ,Work flash large sector write permission SA81" "Disabled,Enabled" bitfld.long 0x18 8. " [80] ,Work flash large sector write permission SA80" "Disabled,Enabled" newline bitfld.long 0x18 7. " [79] ,Work flash large sector write permission SA79" "Disabled,Enabled" bitfld.long 0x18 6. " [78] ,Work flash large sector write permission SA78" "Disabled,Enabled" bitfld.long 0x18 5. " [77] ,Work flash large sector write permission SA77" "Disabled,Enabled" bitfld.long 0x18 4. " [76] ,Work flash large sector write permission SA76" "Disabled,Enabled" newline bitfld.long 0x18 3. " [75] ,Work flash large sector write permission SA75" "Disabled,Enabled" bitfld.long 0x18 2. " [74] ,Work flash large sector write permission SA74" "Disabled,Enabled" bitfld.long 0x18 1. " [73] ,Work flash large sector write permission SA73" "Disabled,Enabled" bitfld.long 0x18 0. " [72] ,Work flash large sector write permission SA72" "Disabled,Enabled" line.long 0x1C "CSWP8,Code Flash Large Sector Write Permissions Register 8" bitfld.long 0x1C 31. " SWP_[135] ,Work flash large sector write permission SA135" "Disabled,Enabled" bitfld.long 0x1C 30. " [134] ,Work flash large sector write permission SA134" "Disabled,Enabled" bitfld.long 0x1C 29. " [133] ,Work flash large sector write permission SA133" "Disabled,Enabled" bitfld.long 0x1C 28. " [132] ,Work flash large sector write permission SA132" "Disabled,Enabled" newline bitfld.long 0x1C 27. " [131] ,Work flash large sector write permission SA131" "Disabled,Enabled" bitfld.long 0x1C 26. " [130] ,Work flash large sector write permission SA130" "Disabled,Enabled" bitfld.long 0x1C 25. " [129] ,Work flash large sector write permission SA129" "Disabled,Enabled" bitfld.long 0x1C 24. " [128] ,Work flash large sector write permission SA128" "Disabled,Enabled" newline bitfld.long 0x1C 23. " [127] ,Work flash large sector write permission SA127" "Disabled,Enabled" bitfld.long 0x1C 22. " [126] ,Work flash large sector write permission SA126" "Disabled,Enabled" bitfld.long 0x1C 21. " [125] ,Work flash large sector write permission SA125" "Disabled,Enabled" bitfld.long 0x1C 20. " [124] ,Work flash large sector write permission SA124" "Disabled,Enabled" newline bitfld.long 0x1C 19. " [123] ,Work flash large sector write permission SA123" "Disabled,Enabled" bitfld.long 0x1C 18. " [122] ,Work flash large sector write permission SA122" "Disabled,Enabled" bitfld.long 0x1C 17. " [121] ,Work flash large sector write permission SA121" "Disabled,Enabled" bitfld.long 0x1C 16. " [120] ,Work flash large sector write permission SA120" "Disabled,Enabled" newline bitfld.long 0x1C 15. " [119] ,Work flash large sector write permission SA119" "Disabled,Enabled" bitfld.long 0x1C 14. " [118] ,Work flash large sector write permission SA118" "Disabled,Enabled" bitfld.long 0x1C 13. " [117] ,Work flash large sector write permission SA117" "Disabled,Enabled" bitfld.long 0x1C 12. " [116] ,Work flash large sector write permission SA116" "Disabled,Enabled" newline bitfld.long 0x1C 11. " [115] ,Work flash large sector write permission SA115" "Disabled,Enabled" bitfld.long 0x1C 10. " [114] ,Work flash large sector write permission SA114" "Disabled,Enabled" bitfld.long 0x1C 9. " [113] ,Work flash large sector write permission SA113" "Disabled,Enabled" bitfld.long 0x1C 8. " [112] ,Work flash large sector write permission SA112" "Disabled,Enabled" newline bitfld.long 0x1C 7. " [111] ,Work flash large sector write permission SA111" "Disabled,Enabled" bitfld.long 0x1C 6. " [110] ,Work flash large sector write permission SA110" "Disabled,Enabled" bitfld.long 0x1C 5. " [109] ,Work flash large sector write permission SA109" "Disabled,Enabled" bitfld.long 0x1C 4. " [108] ,Work flash large sector write permission SA108" "Disabled,Enabled" newline bitfld.long 0x1C 3. " [107] ,Work flash large sector write permission SA107" "Disabled,Enabled" bitfld.long 0x1C 2. " [106] ,Work flash large sector write permission SA106" "Disabled,Enabled" bitfld.long 0x1C 1. " [105] ,Work flash large sector write permission SA105" "Disabled,Enabled" bitfld.long 0x1C 0. " [104] ,Work flash large sector write permission SA104" "Disabled,Enabled" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "MPUXSHE" base ad:0xB4710000 width 8. if (((per.l(ad:0xB4710000))&0x10000)==0x10000) group.long 0x00++0x03 line.long 0x00 "CTRL0,MPU AXI Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" rbitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 10. " MPUSTOPEN ,MPU STOP feature enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU STOP status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" else group.long 0x00++0x03 line.long 0x00 "CTRL0,AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,MPU STOP feature enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU STOP status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" endif group.long 0x04++0x03 line.long 0x00 "NMIEN,MPU AXI NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" rgroup.long 0x08++0x0F line.long 0x00 "WERRC,MPU AXI Write Error Control Register" bitfld.long 0x00 8.--10. " AWSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " AWBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x00 2.--5. " AWLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " AWPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x00 0. " AWMPV ,AXI Write Memory Protection Violation" "0,1" line.long 0x04 "WERRA,MPU AXI Write Error Address Register" line.long 0x08 "RERRC,MPU AXI Read Error Control Register" bitfld.long 0x08 8.--10. " ARSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 6.--7. " ARBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x08 2.--5. " ARLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 1. " ARPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x08 0. " ARMPV ,AXI Read Memory Protection Violation" "0,1" line.long 0x0C "RERRA,MPU AXI Read Error Address Register" sif (cpuis("S6J336*")||cpuis("S6J337*")||cpuis("S6J342*")||cpuis("S6J351*")) if (((per.l(ad:0xB4710000+0x18))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x18++0x03 line.long 0x00 "CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x24))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x24++0x03 line.long 0x00 "CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x30))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x30++0x03 line.long 0x00 "CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x30++0x03 line.long 0x00 "CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x3C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x3C++0x03 line.long 0x00 "CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x48))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x48++0x03 line.long 0x00 "CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x54))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x54++0x03 line.long 0x00 "CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x60))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x60++0x03 line.long 0x00 "CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x6C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x6C++0x03 line.long 0x00 "CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x18))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x1C++0x03 line.long 0x00 "SADDR1,MPU AXI Start Address Register 1" else group.long 0x1C++0x03 line.long 0x00 "SADDR1,MPU AXI Start Address Register 1" endif if (((per.l(ad:0xB4710000+0x24))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x28++0x03 line.long 0x00 "SADDR2,MPU AXI Start Address Register 2" else group.long 0x28++0x03 line.long 0x00 "SADDR2,MPU AXI Start Address Register 2" endif if (((per.l(ad:0xB4710000+0x30))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x34++0x03 line.long 0x00 "SADDR3,MPU AXI Start Address Register 3" else group.long 0x34++0x03 line.long 0x00 "SADDR3,MPU AXI Start Address Register 3" endif if (((per.l(ad:0xB4710000+0x3C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x40++0x03 line.long 0x00 "SADDR4,MPU AXI Start Address Register 4" else group.long 0x40++0x03 line.long 0x00 "SADDR4,MPU AXI Start Address Register 4" endif if (((per.l(ad:0xB4710000+0x48))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x4C++0x03 line.long 0x00 "SADDR5,MPU AXI Start Address Register 5" else group.long 0x4C++0x03 line.long 0x00 "SADDR5,MPU AXI Start Address Register 5" endif if (((per.l(ad:0xB4710000+0x54))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x58++0x03 line.long 0x00 "SADDR6,MPU AXI Start Address Register 6" else group.long 0x58++0x03 line.long 0x00 "SADDR6,MPU AXI Start Address Register 6" endif if (((per.l(ad:0xB4710000+0x60))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x64++0x03 line.long 0x00 "SADDR7,MPU AXI Start Address Register 7" else group.long 0x64++0x03 line.long 0x00 "SADDR7,MPU AXI Start Address Register 7" endif if (((per.l(ad:0xB4710000+0x6C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x70++0x03 line.long 0x00 "SADDR8,MPU AXI Start Address Register 8" else group.long 0x70++0x03 line.long 0x00 "SADDR8,MPU AXI Start Address Register 8" endif if (((per.l(ad:0xB4710000+0x18))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x20++0x03 line.long 0x00 "EADDR1,MPU AXI End Address Register 1" else group.long 0x20++0x03 line.long 0x00 "EADDR1,MPU AXI End Address Register 1" endif if (((per.l(ad:0xB4710000+0x24))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x2C++0x03 line.long 0x00 "EADDR2,MPU AXI End Address Register 2" else group.long 0x2C++0x03 line.long 0x00 "EADDR2,MPU AXI End Address Register 2" endif if (((per.l(ad:0xB4710000+0x30))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x38++0x03 line.long 0x00 "EADDR3,MPU AXI End Address Register 3" else group.long 0x38++0x03 line.long 0x00 "EADDR3,MPU AXI End Address Register 3" endif if (((per.l(ad:0xB4710000+0x3C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x44++0x03 line.long 0x00 "EADDR4,MPU AXI End Address Register 4" else group.long 0x44++0x03 line.long 0x00 "EADDR4,MPU AXI End Address Register 4" endif if (((per.l(ad:0xB4710000+0x48))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x50++0x03 line.long 0x00 "EADDR5,MPU AXI End Address Register 5" else group.long 0x50++0x03 line.long 0x00 "EADDR5,MPU AXI End Address Register 5" endif if (((per.l(ad:0xB4710000+0x54))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x5C++0x03 line.long 0x00 "EADDR6,MPU AXI End Address Register 6" else group.long 0x5C++0x03 line.long 0x00 "EADDR6,MPU AXI End Address Register 6" endif if (((per.l(ad:0xB4710000+0x60))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x68++0x03 line.long 0x00 "EADDR7,MPU AXI End Address Register 7" else group.long 0x68++0x03 line.long 0x00 "EADDR7,MPU AXI End Address Register 7" endif if (((per.l(ad:0xB4710000+0x6C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x74++0x03 line.long 0x00 "EADDR8,MPU AXI End Address Register 8" else group.long 0x74++0x03 line.long 0x00 "EADDR8,MPU AXI End Address Register 8" endif else group.long 0x18++0x03 line.long 0x00 "CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "SADDR1,MPU AXI Start Address Register 1" group.long 0x28++0x03 line.long 0x00 "SADDR2,MPU AXI Start Address Register 2" group.long 0x34++0x03 line.long 0x00 "SADDR3,MPU AXI Start Address Register 3" group.long 0x40++0x03 line.long 0x00 "SADDR4,MPU AXI Start Address Register 4" group.long 0x4C++0x03 line.long 0x00 "SADDR5,MPU AXI Start Address Register 5" group.long 0x58++0x03 line.long 0x00 "SADDR6,MPU AXI Start Address Register 6" group.long 0x64++0x03 line.long 0x00 "SADDR7,MPU AXI Start Address Register 7" group.long 0x70++0x03 line.long 0x00 "SADDR8,MPU AXI Start Address Register 8" group.long 0x20++0x03 line.long 0x00 "EADDR1,MPU AXI End Address Register 1" group.long 0x2C++0x03 line.long 0x00 "EADDR2,MPU AXI End Address Register 2" group.long 0x38++0x03 line.long 0x00 "EADDR3,MPU AXI End Address Register 3" group.long 0x44++0x03 line.long 0x00 "EADDR4,MPU AXI End Address Register 4" group.long 0x50++0x03 line.long 0x00 "EADDR5,MPU AXI End Address Register 5" group.long 0x5C++0x03 line.long 0x00 "EADDR6,MPU AXI End Address Register 6" group.long 0x68++0x03 line.long 0x00 "EADDR7,MPU AXI End Address Register 7" group.long 0x74++0x03 line.long 0x00 "EADDR8,MPU AXI End Address Register 8" endif group.long 0x78++0x03 line.long 0x00 "UNLOCK,MPU AXI Unlock Register" rgroup.long 0x7C++0x03 line.long 0x00 "MID,MPU AXI Module ID Register" width 0x0B tree.end endif tree "SHE (SECURE HARDWARE EXTENSION)" base ad:0xB2000000 width 17. if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x00++0x03 "Configuration Registers For The Command Interface" hide.long 0x00 "SHE_CMD,Command Register" elif (((per.l(ad:0xB2000000+0x0C))&0x01)==0x01)||(((per.l(ad:0xB2000000+0x04))&0x01)==0x01) rgroup.long 0x00++0x03 "Configuration Registers For The Command Interface" line.long 0x00 "SHE_CMD,Command Register" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command opcode" else group.long 0x0++0x03 "Configuration Registers For The Command Interface" line.long 0x00 "SHE_CMD,Command Register" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command opcode" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x04++0x03 hide.long 0x00 "SHE_CMDCANCEL,Command Cancel Register" else group.long 0x04++0x03 line.long 0x00 "SHE_CMDCANCEL,Command Cancel Register" bitfld.long 0x00 0. " CANCELREQ ,Cancel request bit" "Not cancelled,Cancelled" endif group.long 0x08++0x03 line.long 0x00 "SHE_CLKCTRL,Clock Control Register" bitfld.long 0x00 16. " DISREQ ,Clock disable request bit" "No effect,Disabled" bitfld.long 0x00 0. " ENREQ ,Clock enable request bit" "No effect,Enabled" if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x0C++0x03 "Status Registers For The Command Interface" hide.long 0x00 "SHE_STATUS,Status Register" else rgroup.long 0x0C++0x03 "Status Registers For The Command Interface" line.long 0x00 "SHE_STATUS,Status Register" bitfld.long 0x00 24. " FATALERR ,Fatal error flag" "No error,Error" bitfld.long 0x00 19. " FLASHDED ,Flash double bit ECC error flag" "Not occurred,Occurred" bitfld.long 0x00 18. " FLASHSEC ,Flash single bit ECC warning flag" "Not occurred,Occurred" newline bitfld.long 0x00 17. " RAMDED ,RAM double bit ECC error flag" "Not occurred,Occurred" bitfld.long 0x00 16. " RAMSEC ,RAM single bit ECC warning flag" "Not occurred,Occurred" bitfld.long 0x00 9. " INITDONE ,SHE initialization status flag" "Not finished,Finished" newline bitfld.long 0x00 8. " DONE ,Done status flag" "No error,Error" bitfld.long 0x00 7. " INTDEBUGGER ,Internal debugger status flag" "Not activated,Activated" bitfld.long 0x00 6. " EXTDEBUGGER ,External debugger status flag" "Not connected,Connected" newline bitfld.long 0x00 5. " RNDINIT ,Random seed initialization status flag" "Not initialized,Initialized" bitfld.long 0x00 4. " BOOTOK ,Boot OK status flag" "Failed,Succeed" bitfld.long 0x00 3. " BOOTFINISHED ,Boot finished status flag" "Not completed,Completed" newline bitfld.long 0x00 2. " BOOTINIT ,Boot initialization status flag" "Not personalized,Personalized" bitfld.long 0x00 1. " SECUREBOOT ,Secure boot activated status flag" "Not activated,Activated" bitfld.long 0x00 0. " BUSY ,Busy status flag" "Not busy,Busy" endif hgroup.long 0x10++0x03 hide.long 0x00 "SHE_ERC,Error Code Register" in rgroup.long 0x14++0x03 line.long 0x00 "SHE_CLKSTAT,Clock Status Register" bitfld.long 0x00 0. " CLKOFF ,Clock disabled flag" "No,Yes" if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x18++0x03 hide.long 0x00 "SHE_MID,Module ID Register" hgroup.long 0x1C++0x03 "Interrupt Registers For Command Interface" hide.long 0x00 "SHE_IRQ_SET/CLR,Interrupt Request Register" else rgroup.long 0x18++0x03 line.long 0x00 "SHE_MID,Module ID Register" group.long 0x1C++0x03 "Interrupt Registers For Command Interface" line.long 0x00 "SHE_IRQ_SET/CLR,Interrupt Request Register" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " FATALERR ,Fatal error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " IFIFOLOCKERR ,Write to locked input FIFO interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " OMSTIFSELERR ,Output data channel interface selection error interrupt flag" "Not occurred,Occurred" newline setclrfld.long 0x00 20. 0x04 20. 0x08 20. " IMSTIFSELERR ,Input data channel interface selection error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OMSTERR ,Output channel master error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " IMSTERR ,Input channel master error interrupt flag" "Not occurred,Occurred" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " OFIFORDERR ,Read from empty output FIFO error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " IFIFOWRERR ,Write to full input FIFO error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 05. 0x04 05. 0x08 05. " OFIFORDTH ,Output FIFO above threshold interrupt flag" "Not greater,Greater" newline setclrfld.long 0x00 04. 0x04 04. 0x08 04. " IFIFOWRTH ,Input FIFO below threshold interrupt flag" "Not less,Less" setclrfld.long 0x00 03. 0x04 03. 0x08 03. " OMSTIDLE ,Output channel master idle interrupt flag" "Not idle,Idle" setclrfld.long 0x00 02. 0x04 02. 0x08 02. " IMSTIDLE ,Input channel master idle interrupt" "Not idle,Idle" newline setclrfld.long 0x00 01. 0x04 01. 0x08 01. " DONE ,Command execution done interrupt flag" "Not finished,Finished" setclrfld.long 0x00 00. 0x04 00. 0x08 00. " COMPAREMATCH ,Compare match interrupt flag" "Not transferred,Transferred" endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x28++0x03 "Configuration Registers For The Data Interface" hide.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register" else group.long 0x28++0x03 "Configuration Registers For The Data Interface" line.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x2C++0x03 hide.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register" else group.long 0x2C++0x03 line.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register" endif else if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x28++0x03 "Configuration Registers For The Data Interface" hide.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register" elif (((per.l(ad:0xB2000000+0x30))&0x1FFFFFFF)!=0x00) rgroup.long 0x28++0x03 "Configuration Registers For The Data Interface" line.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register" else group.long 0x28++0x03 "Configuration Registers For The Data Interface" line.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x2C++0x03 hide.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register" elif (((per.l(ad:0xB2000000+0x34))&0x1FFFFFFF)!=0x00) rgroup.long 0x2C++0x03 line.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register" else group.long 0x2C++0x03 line.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register" endif endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x30++0x03 hide.long 0x00 "SHE_IMSTCNT,Input Channel Master Data Transfer Counter" hgroup.long 0x34++0x03 hide.long 0x00 "SHE_OMSTCNT,Out Channel Master Data Transfer Counter" hgroup.long 0x38++0x03 hide.long 0x00 "SHE_IMSTSTART,Input Channel Master Start Trigger" hgroup.long 0x3C++0x03 hide.long 0x00 "SHE_OMSTSTART,Output Channel Master Start Trigger" else group.long 0x30++0x0F line.long 0x00 "SHE_IMSTCNT,Input Channel Master Data Transfer Counter" hexmask.long 0x00 0.--28. 1. " IMSTCNT ,Input channel master data transfer counter" line.long 0x04 "SHE_OMSTCNT,Out Channel Master Data Transfer Counter" hexmask.long 0x04 0.--28. 1. " OMSTCNT ,Output channel master data transfer counter" line.long 0x08 "SHE_IMSTSTART,Input Channel Master Start Trigger" bitfld.long 0x08 0. " IMSTSTART ,Input channel master start trigger" "No effect,Started" line.long 0x0C "SHE_OMSTSTART,Output Channel Master Start Trigger" bitfld.long 0x0C 0. " OMSTSTART ,Output channel master start trigger" "No effect,Started" endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x40++0x03 hide.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register" else group.long 0x40++0x03 line.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register" bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x44++0x03 hide.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register" else group.long 0x44++0x03 line.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register" bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif else if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x40++0x03 hide.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register" elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x30))&0x1FFFFFFF)==0x00) group.long 0x40++0x03 line.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register" bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x30))&0x1FFFFFFF)!=0x00) group.long 0x40++0x03 line.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register" rbitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x44++0x03 hide.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register" elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x34))&0x1FFFFFFF)==0x00) group.long 0x44++0x03 line.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register" bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x34))&0x1FFFFFFF)!=0x00) group.long 0x44++0x03 line.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register" rbitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x48++0x03 hide.long 0x00 "SHE_COMPARE0,Input FIFO Compare Value Register" hgroup.long 0x4C++0x03 hide.long 0x00 "SHE_COMPARE1,Input FIFO Compare Value Register" elif (((per.l(ad:0xB2000000+0x50))&0x01)==0x00) rgroup.long 0x48++0x07 line.long 0x00 "SHE_COMPARE0,Input FIFO Compare Value Register" line.long 0x04 "SHE_COMPARE1,Input FIFO Compare Value Register" hexmask.long 0x04 0.--26. 1. " COMPARE ,Most significant bits of the compare register" else group.long 0x48++0x07 line.long 0x00 "SHE_COMPARE0,Input FIFO Compare Value Register" line.long 0x04 "SHE_COMPARE1,Input FIFO Compare Value Register" hexmask.long 0x04 0.--26. 1. " COMPARE ,Most significant bits of the compare register" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x50++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_COMPACC,Access Status Register" hgroup.long 0x54++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_MSTSTATUS,Data Master Status Register" hgroup.long 0x58++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_IMSTERRADDR,Input Channel Master Error Response Address Register" hgroup.long 0x5C++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_OMSTERRADDR,Output Channel Master Error Response Address Register" hgroup.long 0x60++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_FIFOSTATUS,FIFO Status Register" hgroup.long 0x64++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_FIFOLOAD,FIFO Load Register" hgroup.long 0x68++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_DATACNT0,Input FIFO Data Counter Register" hgroup.long 0x6C++0x03 "Status Registers For Data Interface" hide.long 0x00 "SHE_DATACNT1,Input FIFO Data Counter Register" else rgroup.long 0x50++0x1F "Status Registers For Data Interface" line.long 0x00 "SHE_COMPACC,Access Status Register" bitfld.long 0x00 0. " CPUEN ,CPU write access enabled status flag" "Not allowed,Allowed" line.long 0x04 "SHE_MSTSTATUS,Data Master Status Register" bitfld.long 0x04 25.--26. " OMSTERRRESP ,Output data channel master error response code" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x04 24. " OMSTERR ,Output data channel master error response flag" "No error,Error" bitfld.long 0x04 17. " OMSTLOCK ,Output data channel master lock enabled flag" "Unlocked,Locked" newline bitfld.long 0x04 16. " OMSTIDLE ,Output data channel master idle flag" "Started,Idle" bitfld.long 0x04 9.--10. " IMSTERRRESP ,Input data channel master error response code" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x04 8. " IMSTERR ,Input data channel master error response flag" "No error,Error" newline bitfld.long 0x04 1. " IMSTLOCK ,Input data channel master lock enabled flag" "Unlocked,Locked" bitfld.long 0x04 0. " IMSTIDLE ,Input data channel master idle flag" "Started,Idle" line.long 0x08 "SHE_IMSTERRADDR,Input Channel Master Error Response Address Register" line.long 0x0C "SHE_OMSTERRADDR,Output Channel Master Error Response Address Register" line.long 0x10 "SHE_FIFOSTATUS,FIFO Status Register" bitfld.long 0x10 16. " COMPAREMATCH ,Compare march event flag" "Not transferred,Transferred" bitfld.long 0x10 8. " OFIFORDTH ,Output FIFO above threshold flag" "Not greater,Greater" bitfld.long 0x10 0. " IFIFOWRTH ,Input FIFO below threshold flag" "Not less,Less" line.long 0x14 "SHE_FIFOLOAD,FIFO Load Register" bitfld.long 0x14 24.--29. " OFIFOLOAD ,Amount of data stored in the output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " OFIFOFREE ,Amount of data which can be written into the output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--13. " IFIFOLOAD ,Amount of data stored in the input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 0.--5. " IFIFOFREE ,Amount of data which can be written into the input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "SHE_DATACNT0,Input FIFO Data Counter Register" line.long 0x1C "SHE_DATACNT1,Input FIFO Data Counter Register" hexmask.long 0x1C 0.--26. 1. " DATACNT ,Most significant bits of the data counter register" endif width 19. tree "Data transfer registers" sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x100++0x03 hide.long 0x00 "SHE_IFIFOWRDATA0,Input FIFO Write Data Register" in hgroup.long 0x104++0x03 hide.long 0x00 "SHE_IFIFOWRDATA1,Input FIFO Write Data Register" in hgroup.long 0x108++0x03 hide.long 0x00 "SHE_IFIFOWRDATA2,Input FIFO Write Data Register" in hgroup.long 0x10C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA3,Input FIFO Write Data Register" in hgroup.long 0x110++0x03 hide.long 0x00 "SHE_IFIFOWRDATA4,Input FIFO Write Data Register" in hgroup.long 0x114++0x03 hide.long 0x00 "SHE_IFIFOWRDATA5,Input FIFO Write Data Register" in hgroup.long 0x118++0x03 hide.long 0x00 "SHE_IFIFOWRDATA6,Input FIFO Write Data Register" in hgroup.long 0x11C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA7,Input FIFO Write Data Register" in hgroup.long 0x120++0x03 hide.long 0x00 "SHE_IFIFOWRDATA8,Input FIFO Write Data Register" in hgroup.long 0x124++0x03 hide.long 0x00 "SHE_IFIFOWRDATA9,Input FIFO Write Data Register" in hgroup.long 0x128++0x03 hide.long 0x00 "SHE_IFIFOWRDATA10,Input FIFO Write Data Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA11,Input FIFO Write Data Register" in hgroup.long 0x130++0x03 hide.long 0x00 "SHE_IFIFOWRDATA12,Input FIFO Write Data Register" in hgroup.long 0x134++0x03 hide.long 0x00 "SHE_IFIFOWRDATA13,Input FIFO Write Data Register" in hgroup.long 0x138++0x03 hide.long 0x00 "SHE_IFIFOWRDATA14,Input FIFO Write Data Register" in hgroup.long 0x13C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA15,Input FIFO Write Data Register" in hgroup.long 0x140++0x03 hide.long 0x00 "SHE_IFIFOWRDATA16,Input FIFO Write Data Register" in hgroup.long 0x144++0x03 hide.long 0x00 "SHE_IFIFOWRDATA17,Input FIFO Write Data Register" in hgroup.long 0x148++0x03 hide.long 0x00 "SHE_IFIFOWRDATA18,Input FIFO Write Data Register" in hgroup.long 0x14C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA19,Input FIFO Write Data Register" in hgroup.long 0x150++0x03 hide.long 0x00 "SHE_IFIFOWRDATA20,Input FIFO Write Data Register" in hgroup.long 0x154++0x03 hide.long 0x00 "SHE_IFIFOWRDATA21,Input FIFO Write Data Register" in hgroup.long 0x158++0x03 hide.long 0x00 "SHE_IFIFOWRDATA22,Input FIFO Write Data Register" in hgroup.long 0x15C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA23,Input FIFO Write Data Register" in hgroup.long 0x160++0x03 hide.long 0x00 "SHE_IFIFOWRDATA24,Input FIFO Write Data Register" in hgroup.long 0x164++0x03 hide.long 0x00 "SHE_IFIFOWRDATA25,Input FIFO Write Data Register" in hgroup.long 0x168++0x03 hide.long 0x00 "SHE_IFIFOWRDATA26,Input FIFO Write Data Register" in hgroup.long 0x16C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA27,Input FIFO Write Data Register" in hgroup.long 0x170++0x03 hide.long 0x00 "SHE_IFIFOWRDATA28,Input FIFO Write Data Register" in hgroup.long 0x174++0x03 hide.long 0x00 "SHE_IFIFOWRDATA29,Input FIFO Write Data Register" in hgroup.long 0x178++0x03 hide.long 0x00 "SHE_IFIFOWRDATA30,Input FIFO Write Data Register" in hgroup.long 0x17C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA31,Input FIFO Write Data Register" in hgroup.long 0x180++0x03 hide.long 0x00 "SHE_OFIFORDDATA0,Output FIFO Read Data Register" in hgroup.long 0x184++0x03 hide.long 0x00 "SHE_OFIFORDDATA1,Output FIFO Read Data Register" in hgroup.long 0x188++0x03 hide.long 0x00 "SHE_OFIFORDDATA2,Output FIFO Read Data Register" in hgroup.long 0x18C++0x03 hide.long 0x00 "SHE_OFIFORDDATA3,Output FIFO Read Data Register" in hgroup.long 0x190++0x03 hide.long 0x00 "SHE_OFIFORDDATA4,Output FIFO Read Data Register" in hgroup.long 0x194++0x03 hide.long 0x00 "SHE_OFIFORDDATA5,Output FIFO Read Data Register" in hgroup.long 0x198++0x03 hide.long 0x00 "SHE_OFIFORDDATA6,Output FIFO Read Data Register" in hgroup.long 0x19C++0x03 hide.long 0x00 "SHE_OFIFORDDATA7,Output FIFO Read Data Register" in hgroup.long 0x1A0++0x03 hide.long 0x00 "SHE_OFIFORDDATA8,Output FIFO Read Data Register" in hgroup.long 0x1A4++0x03 hide.long 0x00 "SHE_OFIFORDDATA9,Output FIFO Read Data Register" in hgroup.long 0x1A8++0x03 hide.long 0x00 "SHE_OFIFORDDATA10,Output FIFO Read Data Register" in hgroup.long 0x1AC++0x03 hide.long 0x00 "SHE_OFIFORDDATA11,Output FIFO Read Data Register" in hgroup.long 0x1B0++0x03 hide.long 0x00 "SHE_OFIFORDDATA12,Output FIFO Read Data Register" in hgroup.long 0x1B4++0x03 hide.long 0x00 "SHE_OFIFORDDATA13,Output FIFO Read Data Register" in hgroup.long 0x1B8++0x03 hide.long 0x00 "SHE_OFIFORDDATA14,Output FIFO Read Data Register" in hgroup.long 0x1BC++0x03 hide.long 0x00 "SHE_OFIFORDDATA15,Output FIFO Read Data Register" in hgroup.long 0x1C0++0x03 hide.long 0x00 "SHE_OFIFORDDATA16,Output FIFO Read Data Register" in hgroup.long 0x1C4++0x03 hide.long 0x00 "SHE_OFIFORDDATA17,Output FIFO Read Data Register" in hgroup.long 0x1C8++0x03 hide.long 0x00 "SHE_OFIFORDDATA18,Output FIFO Read Data Register" in hgroup.long 0x1CC++0x03 hide.long 0x00 "SHE_OFIFORDDATA19,Output FIFO Read Data Register" in hgroup.long 0x1D0++0x03 hide.long 0x00 "SHE_OFIFORDDATA20,Output FIFO Read Data Register" in hgroup.long 0x1D4++0x03 hide.long 0x00 "SHE_OFIFORDDATA21,Output FIFO Read Data Register" in hgroup.long 0x1D8++0x03 hide.long 0x00 "SHE_OFIFORDDATA22,Output FIFO Read Data Register" in hgroup.long 0x1DC++0x03 hide.long 0x00 "SHE_OFIFORDDATA23,Output FIFO Read Data Register" in hgroup.long 0x1E0++0x03 hide.long 0x00 "SHE_OFIFORDDATA24,Output FIFO Read Data Register" in hgroup.long 0x1E4++0x03 hide.long 0x00 "SHE_OFIFORDDATA25,Output FIFO Read Data Register" in hgroup.long 0x1E8++0x03 hide.long 0x00 "SHE_OFIFORDDATA26,Output FIFO Read Data Register" in hgroup.long 0x1EC++0x03 hide.long 0x00 "SHE_OFIFORDDATA27,Output FIFO Read Data Register" in hgroup.long 0x1F0++0x03 hide.long 0x00 "SHE_OFIFORDDATA28,Output FIFO Read Data Register" in hgroup.long 0x1F4++0x03 hide.long 0x00 "SHE_OFIFORDDATA29,Output FIFO Read Data Register" in hgroup.long 0x1F8++0x03 hide.long 0x00 "SHE_OFIFORDDATA30,Output FIFO Read Data Register" in hgroup.long 0x1FC++0x03 hide.long 0x00 "SHE_OFIFORDDATA31,Output FIFO Read Data Register" in else if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x100++0x03 hide.long 0x00 "SHE_IFIFOWRDATA0,Input FIFO Write Data Register" hgroup.long 0x104++0x03 hide.long 0x00 "SHE_IFIFOWRDATA1,Input FIFO Write Data Register" hgroup.long 0x108++0x03 hide.long 0x00 "SHE_IFIFOWRDATA2,Input FIFO Write Data Register" hgroup.long 0x10C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA3,Input FIFO Write Data Register" hgroup.long 0x110++0x03 hide.long 0x00 "SHE_IFIFOWRDATA4,Input FIFO Write Data Register" hgroup.long 0x114++0x03 hide.long 0x00 "SHE_IFIFOWRDATA5,Input FIFO Write Data Register" hgroup.long 0x118++0x03 hide.long 0x00 "SHE_IFIFOWRDATA6,Input FIFO Write Data Register" hgroup.long 0x11C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA7,Input FIFO Write Data Register" hgroup.long 0x120++0x03 hide.long 0x00 "SHE_IFIFOWRDATA8,Input FIFO Write Data Register" hgroup.long 0x124++0x03 hide.long 0x00 "SHE_IFIFOWRDATA9,Input FIFO Write Data Register" hgroup.long 0x128++0x03 hide.long 0x00 "SHE_IFIFOWRDATA10,Input FIFO Write Data Register" hgroup.long 0x12C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA11,Input FIFO Write Data Register" hgroup.long 0x130++0x03 hide.long 0x00 "SHE_IFIFOWRDATA12,Input FIFO Write Data Register" hgroup.long 0x134++0x03 hide.long 0x00 "SHE_IFIFOWRDATA13,Input FIFO Write Data Register" hgroup.long 0x138++0x03 hide.long 0x00 "SHE_IFIFOWRDATA14,Input FIFO Write Data Register" hgroup.long 0x13C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA15,Input FIFO Write Data Register" hgroup.long 0x140++0x03 hide.long 0x00 "SHE_IFIFOWRDATA16,Input FIFO Write Data Register" hgroup.long 0x144++0x03 hide.long 0x00 "SHE_IFIFOWRDATA17,Input FIFO Write Data Register" hgroup.long 0x148++0x03 hide.long 0x00 "SHE_IFIFOWRDATA18,Input FIFO Write Data Register" hgroup.long 0x14C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA19,Input FIFO Write Data Register" hgroup.long 0x150++0x03 hide.long 0x00 "SHE_IFIFOWRDATA20,Input FIFO Write Data Register" hgroup.long 0x154++0x03 hide.long 0x00 "SHE_IFIFOWRDATA21,Input FIFO Write Data Register" hgroup.long 0x158++0x03 hide.long 0x00 "SHE_IFIFOWRDATA22,Input FIFO Write Data Register" hgroup.long 0x15C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA23,Input FIFO Write Data Register" hgroup.long 0x160++0x03 hide.long 0x00 "SHE_IFIFOWRDATA24,Input FIFO Write Data Register" hgroup.long 0x164++0x03 hide.long 0x00 "SHE_IFIFOWRDATA25,Input FIFO Write Data Register" hgroup.long 0x168++0x03 hide.long 0x00 "SHE_IFIFOWRDATA26,Input FIFO Write Data Register" hgroup.long 0x16C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA27,Input FIFO Write Data Register" hgroup.long 0x170++0x03 hide.long 0x00 "SHE_IFIFOWRDATA28,Input FIFO Write Data Register" hgroup.long 0x174++0x03 hide.long 0x00 "SHE_IFIFOWRDATA29,Input FIFO Write Data Register" hgroup.long 0x178++0x03 hide.long 0x00 "SHE_IFIFOWRDATA30,Input FIFO Write Data Register" hgroup.long 0x17C++0x03 hide.long 0x00 "SHE_IFIFOWRDATA31,Input FIFO Write Data Register" hgroup.long 0x180++0x03 hide.long 0x00 "SHE_OFIFORDDATA0,Output FIFO Read Data Register" hgroup.long 0x184++0x03 hide.long 0x00 "SHE_OFIFORDDATA1,Output FIFO Read Data Register" hgroup.long 0x188++0x03 hide.long 0x00 "SHE_OFIFORDDATA2,Output FIFO Read Data Register" hgroup.long 0x18C++0x03 hide.long 0x00 "SHE_OFIFORDDATA3,Output FIFO Read Data Register" hgroup.long 0x190++0x03 hide.long 0x00 "SHE_OFIFORDDATA4,Output FIFO Read Data Register" hgroup.long 0x194++0x03 hide.long 0x00 "SHE_OFIFORDDATA5,Output FIFO Read Data Register" hgroup.long 0x198++0x03 hide.long 0x00 "SHE_OFIFORDDATA6,Output FIFO Read Data Register" hgroup.long 0x19C++0x03 hide.long 0x00 "SHE_OFIFORDDATA7,Output FIFO Read Data Register" hgroup.long 0x1A0++0x03 hide.long 0x00 "SHE_OFIFORDDATA8,Output FIFO Read Data Register" hgroup.long 0x1A4++0x03 hide.long 0x00 "SHE_OFIFORDDATA9,Output FIFO Read Data Register" hgroup.long 0x1A8++0x03 hide.long 0x00 "SHE_OFIFORDDATA10,Output FIFO Read Data Register" hgroup.long 0x1AC++0x03 hide.long 0x00 "SHE_OFIFORDDATA11,Output FIFO Read Data Register" hgroup.long 0x1B0++0x03 hide.long 0x00 "SHE_OFIFORDDATA12,Output FIFO Read Data Register" hgroup.long 0x1B4++0x03 hide.long 0x00 "SHE_OFIFORDDATA13,Output FIFO Read Data Register" hgroup.long 0x1B8++0x03 hide.long 0x00 "SHE_OFIFORDDATA14,Output FIFO Read Data Register" hgroup.long 0x1BC++0x03 hide.long 0x00 "SHE_OFIFORDDATA15,Output FIFO Read Data Register" hgroup.long 0x1C0++0x03 hide.long 0x00 "SHE_OFIFORDDATA16,Output FIFO Read Data Register" hgroup.long 0x1C4++0x03 hide.long 0x00 "SHE_OFIFORDDATA17,Output FIFO Read Data Register" hgroup.long 0x1C8++0x03 hide.long 0x00 "SHE_OFIFORDDATA18,Output FIFO Read Data Register" hgroup.long 0x1CC++0x03 hide.long 0x00 "SHE_OFIFORDDATA19,Output FIFO Read Data Register" hgroup.long 0x1D0++0x03 hide.long 0x00 "SHE_OFIFORDDATA20,Output FIFO Read Data Register" hgroup.long 0x1D4++0x03 hide.long 0x00 "SHE_OFIFORDDATA21,Output FIFO Read Data Register" hgroup.long 0x1D8++0x03 hide.long 0x00 "SHE_OFIFORDDATA22,Output FIFO Read Data Register" hgroup.long 0x1DC++0x03 hide.long 0x00 "SHE_OFIFORDDATA23,Output FIFO Read Data Register" hgroup.long 0x1E0++0x03 hide.long 0x00 "SHE_OFIFORDDATA24,Output FIFO Read Data Register" hgroup.long 0x1E4++0x03 hide.long 0x00 "SHE_OFIFORDDATA25,Output FIFO Read Data Register" hgroup.long 0x1E8++0x03 hide.long 0x00 "SHE_OFIFORDDATA26,Output FIFO Read Data Register" hgroup.long 0x1EC++0x03 hide.long 0x00 "SHE_OFIFORDDATA27,Output FIFO Read Data Register" hgroup.long 0x1F0++0x03 hide.long 0x00 "SHE_OFIFORDDATA28,Output FIFO Read Data Register" hgroup.long 0x1F4++0x03 hide.long 0x00 "SHE_OFIFORDDATA29,Output FIFO Read Data Register" hgroup.long 0x1F8++0x03 hide.long 0x00 "SHE_OFIFORDDATA30,Output FIFO Read Data Register" hgroup.long 0x1FC++0x03 hide.long 0x00 "SHE_OFIFORDDATA31,Output FIFO Read Data Register" else group.long 0x100++0x03 line.long 0x00 "SHE_IFIFOWRDATA0,Input FIFO Write Data Register" group.long 0x104++0x03 line.long 0x00 "SHE_IFIFOWRDATA1,Input FIFO Write Data Register" group.long 0x108++0x03 line.long 0x00 "SHE_IFIFOWRDATA2,Input FIFO Write Data Register" group.long 0x10C++0x03 line.long 0x00 "SHE_IFIFOWRDATA3,Input FIFO Write Data Register" group.long 0x110++0x03 line.long 0x00 "SHE_IFIFOWRDATA4,Input FIFO Write Data Register" group.long 0x114++0x03 line.long 0x00 "SHE_IFIFOWRDATA5,Input FIFO Write Data Register" group.long 0x118++0x03 line.long 0x00 "SHE_IFIFOWRDATA6,Input FIFO Write Data Register" group.long 0x11C++0x03 line.long 0x00 "SHE_IFIFOWRDATA7,Input FIFO Write Data Register" group.long 0x120++0x03 line.long 0x00 "SHE_IFIFOWRDATA8,Input FIFO Write Data Register" group.long 0x124++0x03 line.long 0x00 "SHE_IFIFOWRDATA9,Input FIFO Write Data Register" group.long 0x128++0x03 line.long 0x00 "SHE_IFIFOWRDATA10,Input FIFO Write Data Register" group.long 0x12C++0x03 line.long 0x00 "SHE_IFIFOWRDATA11,Input FIFO Write Data Register" group.long 0x130++0x03 line.long 0x00 "SHE_IFIFOWRDATA12,Input FIFO Write Data Register" group.long 0x134++0x03 line.long 0x00 "SHE_IFIFOWRDATA13,Input FIFO Write Data Register" group.long 0x138++0x03 line.long 0x00 "SHE_IFIFOWRDATA14,Input FIFO Write Data Register" group.long 0x13C++0x03 line.long 0x00 "SHE_IFIFOWRDATA15,Input FIFO Write Data Register" group.long 0x140++0x03 line.long 0x00 "SHE_IFIFOWRDATA16,Input FIFO Write Data Register" group.long 0x144++0x03 line.long 0x00 "SHE_IFIFOWRDATA17,Input FIFO Write Data Register" group.long 0x148++0x03 line.long 0x00 "SHE_IFIFOWRDATA18,Input FIFO Write Data Register" group.long 0x14C++0x03 line.long 0x00 "SHE_IFIFOWRDATA19,Input FIFO Write Data Register" group.long 0x150++0x03 line.long 0x00 "SHE_IFIFOWRDATA20,Input FIFO Write Data Register" group.long 0x154++0x03 line.long 0x00 "SHE_IFIFOWRDATA21,Input FIFO Write Data Register" group.long 0x158++0x03 line.long 0x00 "SHE_IFIFOWRDATA22,Input FIFO Write Data Register" group.long 0x15C++0x03 line.long 0x00 "SHE_IFIFOWRDATA23,Input FIFO Write Data Register" group.long 0x160++0x03 line.long 0x00 "SHE_IFIFOWRDATA24,Input FIFO Write Data Register" group.long 0x164++0x03 line.long 0x00 "SHE_IFIFOWRDATA25,Input FIFO Write Data Register" group.long 0x168++0x03 line.long 0x00 "SHE_IFIFOWRDATA26,Input FIFO Write Data Register" group.long 0x16C++0x03 line.long 0x00 "SHE_IFIFOWRDATA27,Input FIFO Write Data Register" group.long 0x170++0x03 line.long 0x00 "SHE_IFIFOWRDATA28,Input FIFO Write Data Register" group.long 0x174++0x03 line.long 0x00 "SHE_IFIFOWRDATA29,Input FIFO Write Data Register" group.long 0x178++0x03 line.long 0x00 "SHE_IFIFOWRDATA30,Input FIFO Write Data Register" group.long 0x17C++0x03 line.long 0x00 "SHE_IFIFOWRDATA31,Input FIFO Write Data Register" group.long 0x180++0x03 line.long 0x00 "SHE_OFIFORDDATA0,Output FIFO Read Data Register" group.long 0x184++0x03 line.long 0x00 "SHE_OFIFORDDATA1,Output FIFO Read Data Register" group.long 0x188++0x03 line.long 0x00 "SHE_OFIFORDDATA2,Output FIFO Read Data Register" group.long 0x18C++0x03 line.long 0x00 "SHE_OFIFORDDATA3,Output FIFO Read Data Register" group.long 0x190++0x03 line.long 0x00 "SHE_OFIFORDDATA4,Output FIFO Read Data Register" group.long 0x194++0x03 line.long 0x00 "SHE_OFIFORDDATA5,Output FIFO Read Data Register" group.long 0x198++0x03 line.long 0x00 "SHE_OFIFORDDATA6,Output FIFO Read Data Register" group.long 0x19C++0x03 line.long 0x00 "SHE_OFIFORDDATA7,Output FIFO Read Data Register" group.long 0x1A0++0x03 line.long 0x00 "SHE_OFIFORDDATA8,Output FIFO Read Data Register" group.long 0x1A4++0x03 line.long 0x00 "SHE_OFIFORDDATA9,Output FIFO Read Data Register" group.long 0x1A8++0x03 line.long 0x00 "SHE_OFIFORDDATA10,Output FIFO Read Data Register" group.long 0x1AC++0x03 line.long 0x00 "SHE_OFIFORDDATA11,Output FIFO Read Data Register" group.long 0x1B0++0x03 line.long 0x00 "SHE_OFIFORDDATA12,Output FIFO Read Data Register" group.long 0x1B4++0x03 line.long 0x00 "SHE_OFIFORDDATA13,Output FIFO Read Data Register" group.long 0x1B8++0x03 line.long 0x00 "SHE_OFIFORDDATA14,Output FIFO Read Data Register" group.long 0x1BC++0x03 line.long 0x00 "SHE_OFIFORDDATA15,Output FIFO Read Data Register" group.long 0x1C0++0x03 line.long 0x00 "SHE_OFIFORDDATA16,Output FIFO Read Data Register" group.long 0x1C4++0x03 line.long 0x00 "SHE_OFIFORDDATA17,Output FIFO Read Data Register" group.long 0x1C8++0x03 line.long 0x00 "SHE_OFIFORDDATA18,Output FIFO Read Data Register" group.long 0x1CC++0x03 line.long 0x00 "SHE_OFIFORDDATA19,Output FIFO Read Data Register" group.long 0x1D0++0x03 line.long 0x00 "SHE_OFIFORDDATA20,Output FIFO Read Data Register" group.long 0x1D4++0x03 line.long 0x00 "SHE_OFIFORDDATA21,Output FIFO Read Data Register" group.long 0x1D8++0x03 line.long 0x00 "SHE_OFIFORDDATA22,Output FIFO Read Data Register" group.long 0x1DC++0x03 line.long 0x00 "SHE_OFIFORDDATA23,Output FIFO Read Data Register" group.long 0x1E0++0x03 line.long 0x00 "SHE_OFIFORDDATA24,Output FIFO Read Data Register" group.long 0x1E4++0x03 line.long 0x00 "SHE_OFIFORDDATA25,Output FIFO Read Data Register" group.long 0x1E8++0x03 line.long 0x00 "SHE_OFIFORDDATA26,Output FIFO Read Data Register" group.long 0x1EC++0x03 line.long 0x00 "SHE_OFIFORDDATA27,Output FIFO Read Data Register" group.long 0x1F0++0x03 line.long 0x00 "SHE_OFIFORDDATA28,Output FIFO Read Data Register" group.long 0x1F4++0x03 line.long 0x00 "SHE_OFIFORDDATA29,Output FIFO Read Data Register" group.long 0x1F8++0x03 line.long 0x00 "SHE_OFIFORDDATA30,Output FIFO Read Data Register" group.long 0x1FC++0x03 line.long 0x00 "SHE_OFIFORDDATA31,Output FIFO Read Data Register" endif endif tree.end width 0x0B tree.end tree "DMA CONTROLLER" base ad:0xB4700000 sif (cpuis("S6J336*")||cpuis("S6J337*")) width 13. group.long 0x1000++0x03 line.long 0x00 "DMA0_R,DMA Controller Global Configuration Register" bitfld.long 0x00 31. " DE ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 30. " DSHR ,DMA stop/halt request flag" "Not requested,Requested" bitfld.long 0x00 29. " DBE ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 27.--28. " PR ,Priority type" "Fixed,Dynamic,Round robin,?..." bitfld.long 0x00 26. " DH ,DMA halt" "Not halted,Halted" bitfld.long 0x00 24.--25. " DB ,Debug behavior" "Continues,Halted,Stopped,?..." newline rbitfld.long 0x00 0. " DSHS ,DMA stop/halt status flag" "Running,Halted" rgroup.long 0x1004++0x03 line.long 0x00 "DMA0_DIRQ1,DMA Controller Global Completion Interrupt 1 Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") bitfld.long 0x00 31. " DIRQ_[31] ,Global Completion interrupt 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Global Completion interrupt 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Global Completion interrupt 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Global Completion interrupt 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Global Completion interrupt 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Global Completion interrupt 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Global Completion interrupt 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Global Completion interrupt 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Global Completion interrupt 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Global Completion interrupt 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Global Completion interrupt 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Global Completion interrupt 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Global Completion interrupt 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Global Completion interrupt 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Global Completion interrupt 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Global Completion interrupt 16" "No interrupt,Interrupt" newline endif bitfld.long 0x00 15. " [15] ,Global Completion interrupt 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Global Completion interrupt 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Global Completion interrupt 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Global Completion interrupt 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Global Completion interrupt 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Global Completion interrupt 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Global Completion interrupt 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Global Completion interrupt 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Global Completion interrupt 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Global Completion interrupt 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Global Completion interrupt 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Global Completion interrupt 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Global Completion interrupt 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Global Completion interrupt 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Global Completion interrupt 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Global Completion interrupt 0" "No interrupt,Interrupt" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") rgroup.long 0x1008++0x03 line.long 0x00 "DMA0_DIRQ2,DMA Controller Global Completion Interrupt 2 Register" bitfld.long 0x00 31. " DIRQ_[63] ,Global Completion interrupt 63" "No interrupt,Interrupt" bitfld.long 0x00 30. " [62] ,Global Completion interrupt 62" "No interrupt,Interrupt" bitfld.long 0x00 29. " [61] ,Global Completion interrupt 61" "No interrupt,Interrupt" bitfld.long 0x00 28. " [60] ,Global Completion interrupt 60" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [59] ,Global Completion interrupt 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " [58] ,Global Completion interrupt 58" "No interrupt,Interrupt" bitfld.long 0x00 25. " [57] ,Global Completion interrupt 57" "No interrupt,Interrupt" bitfld.long 0x00 24. " [56] ,Global Completion interrupt 56" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [55] ,Global Completion interrupt 55" "No interrupt,Interrupt" bitfld.long 0x00 22. " [54] ,Global Completion interrupt 54" "No interrupt,Interrupt" bitfld.long 0x00 21. " [53] ,Global Completion interrupt 53" "No interrupt,Interrupt" bitfld.long 0x00 20. " [52] ,Global Completion interrupt 52" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [51] ,Global Completion interrupt 51" "No interrupt,Interrupt" bitfld.long 0x00 18. " [50] ,Global Completion interrupt 50" "No interrupt,Interrupt" bitfld.long 0x00 17. " [49] ,Global Completion interrupt 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " [48] ,Global Completion interrupt 48" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [47] ,Global Completion interrupt 47" "No interrupt,Interrupt" bitfld.long 0x00 14. " [46] ,Global Completion interrupt 46" "No interrupt,Interrupt" bitfld.long 0x00 13. " [45] ,Global Completion interrupt 45" "No interrupt,Interrupt" bitfld.long 0x00 12. " [44] ,Global Completion interrupt 44" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [43] ,Global Completion interrupt 43" "No interrupt,Interrupt" bitfld.long 0x00 10. " [42] ,Global Completion interrupt 42" "No interrupt,Interrupt" bitfld.long 0x00 9. " [41] ,Global Completion interrupt 41" "No interrupt,Interrupt" bitfld.long 0x00 8. " [40] ,Global Completion interrupt 40" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [39] ,Global Completion interrupt 39" "No interrupt,Interrupt" bitfld.long 0x00 6. " [38] ,Global Completion interrupt 38" "No interrupt,Interrupt" bitfld.long 0x00 5. " [37] ,Global Completion interrupt 37" "No interrupt,Interrupt" bitfld.long 0x00 4. " [36] ,Global Completion interrupt 36" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [35] ,Global Completion interrupt 35" "No interrupt,Interrupt" bitfld.long 0x00 2. " [34] ,Global Completion interrupt 34" "No interrupt,Interrupt" bitfld.long 0x00 1. " [33] ,Global Completion interrupt 33" "No interrupt,Interrupt" bitfld.long 0x00 0. " [32] ,Global Completion interrupt 32" "No interrupt,Interrupt" endif rgroup.long 0x100C++0x03 line.long 0x00 "DMA0_EDIRQ1,DMA Controller Global Error Interrupt 1 Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") bitfld.long 0x00 31. " EDIRQ_[31] ,Global error interrupt 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,Global error interrupt 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,Global error interrupt 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,Global error interrupt 28" "Not occurred,Occurred" newline bitfld.long 0x00 27. " [27] ,Global error interrupt 27" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,Global error interrupt 26" "Not occurred,Occurred" bitfld.long 0x00 25. " [25] ,Global error interrupt 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,Global error interrupt 24" "Not occurred,Occurred" newline bitfld.long 0x00 23. " [23] ,Global error interrupt 23" "Not occurred,Occurred" bitfld.long 0x00 22. " [22] ,Global error interrupt 22" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,Global error interrupt 21" "Not occurred,Occurred" bitfld.long 0x00 20. " [20] ,Global error interrupt 20" "Not occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Global error interrupt 19" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,Global error interrupt 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,Global error interrupt 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,Global error interrupt 16" "Not occurred,Occurred" newline endif bitfld.long 0x00 15. " [15] ,Global error interrupt 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,Global error interrupt 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,Global error interrupt 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,Global error interrupt 12" "Not occurred,Occurred" newline bitfld.long 0x00 11. " [11] ,Global error interrupt 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,Global error interrupt 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,Global error interrupt 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,Global error interrupt 8" "Not occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Global error interrupt 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,Global error interrupt 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,Global error interrupt 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Global error interrupt 4" "Not occurred,Occurred" newline bitfld.long 0x00 3. " [3] ,Global error interrupt 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Global error interrupt 2" "Not occurred,Occurred" bitfld.long 0x00 1. " [1] ,Global error interrupt 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Global error interrupt 0" "Not occurred,Occurred" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") rgroup.long 0x1010++0x03 line.long 0x00 "DMA0_EDIRQ2,DMA Controller Global Error Interrupt 2 Register" bitfld.long 0x00 31. " EDIRQ_[63] ,Global error interrupt 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,Global error interrupt 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,Global error interrupt 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,Global error interrupt 60" "Not occurred,Occurred" newline bitfld.long 0x00 27. " [59] ,Global error interrupt 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,Global error interrupt 58" "Not occurred,Occurred" bitfld.long 0x00 25. " [57] ,Global error interrupt 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,Global error interrupt 56" "Not occurred,Occurred" newline bitfld.long 0x00 23. " [55] ,Global error interrupt 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,Global error interrupt 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,Global error interrupt 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,Global error interrupt 52" "Not occurred,Occurred" newline bitfld.long 0x00 19. " [51] ,Global error interrupt 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,Global error interrupt 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,Global error interrupt 49" "Not occurred,Occurred" bitfld.long 0x00 16. " [48] ,Global error interrupt 48" "Not occurred,Occurred" newline bitfld.long 0x00 15. " [47] ,Global error interrupt 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,Global error interrupt 46" "Not occurred,Occurred" bitfld.long 0x00 13. " [45] ,Global error interrupt 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,Global error interrupt 44" "Not occurred,Occurred" newline bitfld.long 0x00 11. " [43] ,Global error interrupt 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,Global error interrupt 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,Global error interrupt 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,Global error interrupt 40" "Not occurred,Occurred" newline bitfld.long 0x00 7. " [39] ,Global error interrupt 39" "Not occurred,Occurred" bitfld.long 0x00 6. " [38] ,Global error interrupt 38" "Not occurred,Occurred" bitfld.long 0x00 5. " [37] ,Global error interrupt 37" "Not occurred,Occurred" bitfld.long 0x00 4. " [36] ,Global error interrupt 36" "Not occurred,Occurred" newline bitfld.long 0x00 3. " [35] ,Global error interrupt 35" "Not occurred,Occurred" bitfld.long 0x00 2. " [34] ,Global error interrupt 34" "Not occurred,Occurred" bitfld.long 0x00 1. " [33] ,Global error interrupt 33" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,Global error interrupt 32" "Not occurred,Occurred" endif rgroup.long 0x1014++0x03 line.long 0x00 "DMA0_ID,DMA Controller ID Register" width 12. tree "DMA_A 0--15" group.long 0x0++0x03 line.long 0x00 "DMA0_A0,DMA Controller Channel Configuration A Register Channel 0" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x40++0x03 line.long 0x00 "DMA0_A1,DMA Controller Channel Configuration A Register Channel 1" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x80++0x03 line.long 0x00 "DMA0_A2,DMA Controller Channel Configuration A Register Channel 2" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0xC0++0x03 line.long 0x00 "DMA0_A3,DMA Controller Channel Configuration A Register Channel 3" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x100++0x03 line.long 0x00 "DMA0_A4,DMA Controller Channel Configuration A Register Channel 4" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x140++0x03 line.long 0x00 "DMA0_A5,DMA Controller Channel Configuration A Register Channel 5" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x180++0x03 line.long 0x00 "DMA0_A6,DMA Controller Channel Configuration A Register Channel 6" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x1C0++0x03 line.long 0x00 "DMA0_A7,DMA Controller Channel Configuration A Register Channel 7" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x200++0x03 line.long 0x00 "DMA0_A8,DMA Controller Channel Configuration A Register Channel 8" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x240++0x03 line.long 0x00 "DMA0_A9,DMA Controller Channel Configuration A Register Channel 9" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x280++0x03 line.long 0x00 "DMA0_A10,DMA Controller Channel Configuration A Register Channel 10" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x2C0++0x03 line.long 0x00 "DMA0_A11,DMA Controller Channel Configuration A Register Channel 11" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x300++0x03 line.long 0x00 "DMA0_A12,DMA Controller Channel Configuration A Register Channel 12" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x340++0x03 line.long 0x00 "DMA0_A13,DMA Controller Channel Configuration A Register Channel 13" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x380++0x03 line.long 0x00 "DMA0_A14,DMA Controller Channel Configuration A Register Channel 14" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x3C0++0x03 line.long 0x00 "DMA0_A15,DMA Controller Channel Configuration A Register Channel 15" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" tree.end tree "DMA_B 0--15" group.long 0x4++0x03 line.long 0x00 "DMA0_B0,DMA Controller Channel Configuration B Register Channel 0" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x44++0x03 line.long 0x00 "DMA0_B1,DMA Controller Channel Configuration B Register Channel 1" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x84++0x03 line.long 0x00 "DMA0_B2,DMA Controller Channel Configuration B Register Channel 2" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0xC4++0x03 line.long 0x00 "DMA0_B3,DMA Controller Channel Configuration B Register Channel 3" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x104++0x03 line.long 0x00 "DMA0_B4,DMA Controller Channel Configuration B Register Channel 4" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x144++0x03 line.long 0x00 "DMA0_B5,DMA Controller Channel Configuration B Register Channel 5" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x184++0x03 line.long 0x00 "DMA0_B6,DMA Controller Channel Configuration B Register Channel 6" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x1C4++0x03 line.long 0x00 "DMA0_B7,DMA Controller Channel Configuration B Register Channel 7" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x204++0x03 line.long 0x00 "DMA0_B8,DMA Controller Channel Configuration B Register Channel 8" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x244++0x03 line.long 0x00 "DMA0_B9,DMA Controller Channel Configuration B Register Channel 9" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x284++0x03 line.long 0x00 "DMA0_B10,DMA Controller Channel Configuration B Register Channel 10" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x2C4++0x03 line.long 0x00 "DMA0_B11,DMA Controller Channel Configuration B Register Channel 11" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x304++0x03 line.long 0x00 "DMA0_B12,DMA Controller Channel Configuration B Register Channel 12" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x344++0x03 line.long 0x00 "DMA0_B13,DMA Controller Channel Configuration B Register Channel 13" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x384++0x03 line.long 0x00 "DMA0_B14,DMA Controller Channel Configuration B Register Channel 14" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x3C4++0x03 line.long 0x00 "DMA0_B15,DMA Controller Channel Configuration B Register Channel 15" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" tree.end tree "DMA_SA 0--15" group.long 0x8++0x03 line.long 0x00 "DMA0_SA0,DMA Controller Channel Configuration Source Address Register Channel 0" group.long 0x48++0x03 line.long 0x00 "DMA0_SA1,DMA Controller Channel Configuration Source Address Register Channel 1" group.long 0x88++0x03 line.long 0x00 "DMA0_SA2,DMA Controller Channel Configuration Source Address Register Channel 2" group.long 0xC8++0x03 line.long 0x00 "DMA0_SA3,DMA Controller Channel Configuration Source Address Register Channel 3" group.long 0x108++0x03 line.long 0x00 "DMA0_SA4,DMA Controller Channel Configuration Source Address Register Channel 4" group.long 0x148++0x03 line.long 0x00 "DMA0_SA5,DMA Controller Channel Configuration Source Address Register Channel 5" group.long 0x188++0x03 line.long 0x00 "DMA0_SA6,DMA Controller Channel Configuration Source Address Register Channel 6" group.long 0x1C8++0x03 line.long 0x00 "DMA0_SA7,DMA Controller Channel Configuration Source Address Register Channel 7" group.long 0x208++0x03 line.long 0x00 "DMA0_SA8,DMA Controller Channel Configuration Source Address Register Channel 8" group.long 0x248++0x03 line.long 0x00 "DMA0_SA9,DMA Controller Channel Configuration Source Address Register Channel 9" group.long 0x288++0x03 line.long 0x00 "DMA0_SA10,DMA Controller Channel Configuration Source Address Register Channel 10" group.long 0x2C8++0x03 line.long 0x00 "DMA0_SA11,DMA Controller Channel Configuration Source Address Register Channel 11" group.long 0x308++0x03 line.long 0x00 "DMA0_SA12,DMA Controller Channel Configuration Source Address Register Channel 12" group.long 0x348++0x03 line.long 0x00 "DMA0_SA13,DMA Controller Channel Configuration Source Address Register Channel 13" group.long 0x388++0x03 line.long 0x00 "DMA0_SA14,DMA Controller Channel Configuration Source Address Register Channel 14" group.long 0x3C8++0x03 line.long 0x00 "DMA0_SA15,DMA Controller Channel Configuration Source Address Register Channel 15" tree.end tree "DMA_DA 0--15" group.long 0xC++0x03 line.long 0x00 "DMA0_DA0,DMA Controller Channel Configuration Destination Address Register Channel 0" group.long 0x4C++0x03 line.long 0x00 "DMA0_DA1,DMA Controller Channel Configuration Destination Address Register Channel 1" group.long 0x8C++0x03 line.long 0x00 "DMA0_DA2,DMA Controller Channel Configuration Destination Address Register Channel 2" group.long 0xCC++0x03 line.long 0x00 "DMA0_DA3,DMA Controller Channel Configuration Destination Address Register Channel 3" group.long 0x10C++0x03 line.long 0x00 "DMA0_DA4,DMA Controller Channel Configuration Destination Address Register Channel 4" group.long 0x14C++0x03 line.long 0x00 "DMA0_DA5,DMA Controller Channel Configuration Destination Address Register Channel 5" group.long 0x18C++0x03 line.long 0x00 "DMA0_DA6,DMA Controller Channel Configuration Destination Address Register Channel 6" group.long 0x1CC++0x03 line.long 0x00 "DMA0_DA7,DMA Controller Channel Configuration Destination Address Register Channel 7" group.long 0x20C++0x03 line.long 0x00 "DMA0_DA8,DMA Controller Channel Configuration Destination Address Register Channel 8" group.long 0x24C++0x03 line.long 0x00 "DMA0_DA9,DMA Controller Channel Configuration Destination Address Register Channel 9" group.long 0x28C++0x03 line.long 0x00 "DMA0_DA10,DMA Controller Channel Configuration Destination Address Register Channel 10" group.long 0x2CC++0x03 line.long 0x00 "DMA0_DA11,DMA Controller Channel Configuration Destination Address Register Channel 11" group.long 0x30C++0x03 line.long 0x00 "DMA0_DA12,DMA Controller Channel Configuration Destination Address Register Channel 12" group.long 0x34C++0x03 line.long 0x00 "DMA0_DA13,DMA Controller Channel Configuration Destination Address Register Channel 13" group.long 0x38C++0x03 line.long 0x00 "DMA0_DA14,DMA Controller Channel Configuration Destination Address Register Channel 14" group.long 0x3CC++0x03 line.long 0x00 "DMA0_DA15,DMA Controller Channel Configuration Destination Address Register Channel 15" tree.end tree "DMA_C 0--15" group.long 0x10++0x03 line.long 0x00 "DMA0_C0,DMA Controller Channel Configuration C Register Channel 0" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x50++0x03 line.long 0x00 "DMA0_C1,DMA Controller Channel Configuration C Register Channel 1" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x90++0x03 line.long 0x00 "DMA0_C2,DMA Controller Channel Configuration C Register Channel 2" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0xD0++0x03 line.long 0x00 "DMA0_C3,DMA Controller Channel Configuration C Register Channel 3" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x110++0x03 line.long 0x00 "DMA0_C4,DMA Controller Channel Configuration C Register Channel 4" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x150++0x03 line.long 0x00 "DMA0_C5,DMA Controller Channel Configuration C Register Channel 5" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x190++0x03 line.long 0x00 "DMA0_C6,DMA Controller Channel Configuration C Register Channel 6" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x1D0++0x03 line.long 0x00 "DMA0_C7,DMA Controller Channel Configuration C Register Channel 7" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x210++0x03 line.long 0x00 "DMA0_C8,DMA Controller Channel Configuration C Register Channel 8" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x250++0x03 line.long 0x00 "DMA0_C9,DMA Controller Channel Configuration C Register Channel 9" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x290++0x03 line.long 0x00 "DMA0_C10,DMA Controller Channel Configuration C Register Channel 10" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x2D0++0x03 line.long 0x00 "DMA0_C11,DMA Controller Channel Configuration C Register Channel 11" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x310++0x03 line.long 0x00 "DMA0_C12,DMA Controller Channel Configuration C Register Channel 12" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x350++0x03 line.long 0x00 "DMA0_C13,DMA Controller Channel Configuration C Register Channel 13" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x390++0x03 line.long 0x00 "DMA0_C14,DMA Controller Channel Configuration C Register Channel 14" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x3D0++0x03 line.long 0x00 "DMA0_C15,DMA Controller Channel Configuration C Register Channel 15" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" tree.end tree "DMA_D 0--15" sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00) group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00) group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00) group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00) group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00) group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00) group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00) group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00) group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00) group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00) group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00) group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00) group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00) group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00) group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00) group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00) group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00) group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00) group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00) group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00) group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00) group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00) group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00) group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00) group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00) group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00) group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00) group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00) group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00) group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00) group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00) group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00) group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00) group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00) group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00) group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00) group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00) group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00) group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00) group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00) group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00) group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00) group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00) group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00) group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00) group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00) group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00) group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00) group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00) group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00) group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00) group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00) group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00) group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00) group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00) group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00) group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00) group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00) group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00) group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00) group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00) group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00) group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00) group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00) group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00) group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00) group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00) group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00) group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00) group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00) group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00) group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00) group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00) group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00) group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00) group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00) group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00) group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00) group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00) group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00) group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00) group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00) group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00) group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00) group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00) group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00) group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00) group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00) group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00) group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00) group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00) group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00) group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00) group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00) group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00) group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00) group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif tree.end sif !cpuis("S6J320CKSA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J336*")&&!cpuis("S6J337*") tree "DMA_E 0--15" group.long 0x20++0x03 line.long 0x00 "DMA0_E0,DMA Controller Channel Configuration E Register Channel 0" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x60++0x03 line.long 0x00 "DMA0_E1,DMA Controller Channel Configuration E Register Channel 1" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0xA0++0x03 line.long 0x00 "DMA0_E2,DMA Controller Channel Configuration E Register Channel 2" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0xE0++0x03 line.long 0x00 "DMA0_E3,DMA Controller Channel Configuration E Register Channel 3" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x120++0x03 line.long 0x00 "DMA0_E4,DMA Controller Channel Configuration E Register Channel 4" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x160++0x03 line.long 0x00 "DMA0_E5,DMA Controller Channel Configuration E Register Channel 5" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x1A0++0x03 line.long 0x00 "DMA0_E6,DMA Controller Channel Configuration E Register Channel 6" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x1E0++0x03 line.long 0x00 "DMA0_E7,DMA Controller Channel Configuration E Register Channel 7" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x220++0x03 line.long 0x00 "DMA0_E8,DMA Controller Channel Configuration E Register Channel 8" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x260++0x03 line.long 0x00 "DMA0_E9,DMA Controller Channel Configuration E Register Channel 9" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x2A0++0x03 line.long 0x00 "DMA0_E10,DMA Controller Channel Configuration E Register Channel 10" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x2E0++0x03 line.long 0x00 "DMA0_E11,DMA Controller Channel Configuration E Register Channel 11" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x320++0x03 line.long 0x00 "DMA0_E12,DMA Controller Channel Configuration E Register Channel 12" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x360++0x03 line.long 0x00 "DMA0_E13,DMA Controller Channel Configuration E Register Channel 13" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x3A0++0x03 line.long 0x00 "DMA0_E14,DMA Controller Channel Configuration E Register Channel 14" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x3E0++0x03 line.long 0x00 "DMA0_E15,DMA Controller Channel Configuration E Register Channel 15" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif tree.end endif width 15. tree "DMA_SASHDW DMA_DASHDW 0-15" rgroup.long 0x18++0x03 line.long 0x00 "DMA0_SASHDW0,DMA Controller Channel Configuration Source Address Shadow Register Channel 0" rgroup.long 0x58++0x03 line.long 0x00 "DMA0_SASHDW1,DMA Controller Channel Configuration Source Address Shadow Register Channel 1" rgroup.long 0x98++0x03 line.long 0x00 "DMA0_SASHDW2,DMA Controller Channel Configuration Source Address Shadow Register Channel 2" rgroup.long 0xD8++0x03 line.long 0x00 "DMA0_SASHDW3,DMA Controller Channel Configuration Source Address Shadow Register Channel 3" rgroup.long 0x118++0x03 line.long 0x00 "DMA0_SASHDW4,DMA Controller Channel Configuration Source Address Shadow Register Channel 4" rgroup.long 0x158++0x03 line.long 0x00 "DMA0_SASHDW5,DMA Controller Channel Configuration Source Address Shadow Register Channel 5" rgroup.long 0x198++0x03 line.long 0x00 "DMA0_SASHDW6,DMA Controller Channel Configuration Source Address Shadow Register Channel 6" rgroup.long 0x1D8++0x03 line.long 0x00 "DMA0_SASHDW7,DMA Controller Channel Configuration Source Address Shadow Register Channel 7" rgroup.long 0x218++0x03 line.long 0x00 "DMA0_SASHDW8,DMA Controller Channel Configuration Source Address Shadow Register Channel 8" rgroup.long 0x258++0x03 line.long 0x00 "DMA0_SASHDW9,DMA Controller Channel Configuration Source Address Shadow Register Channel 9" rgroup.long 0x298++0x03 line.long 0x00 "DMA0_SASHDW10,DMA Controller Channel Configuration Source Address Shadow Register Channel 10" rgroup.long 0x2D8++0x03 line.long 0x00 "DMA0_SASHDW11,DMA Controller Channel Configuration Source Address Shadow Register Channel 11" rgroup.long 0x318++0x03 line.long 0x00 "DMA0_SASHDW12,DMA Controller Channel Configuration Source Address Shadow Register Channel 12" rgroup.long 0x358++0x03 line.long 0x00 "DMA0_SASHDW13,DMA Controller Channel Configuration Source Address Shadow Register Channel 13" rgroup.long 0x398++0x03 line.long 0x00 "DMA0_SASHDW14,DMA Controller Channel Configuration Source Address Shadow Register Channel 14" rgroup.long 0x3D8++0x03 line.long 0x00 "DMA0_SASHDW15,DMA Controller Channel Configuration Source Address Shadow Register Channel 15" rgroup.long 0x1C++0x03 line.long 0x00 "DMA0_DASHDW0,DMA Controller Channel Configuration Destination Address Shadow Register Channel 0" rgroup.long 0x5C++0x03 line.long 0x00 "DMA0_DASHDW1,DMA Controller Channel Configuration Destination Address Shadow Register Channel 1" rgroup.long 0x9C++0x03 line.long 0x00 "DMA0_DASHDW2,DMA Controller Channel Configuration Destination Address Shadow Register Channel 2" rgroup.long 0xDC++0x03 line.long 0x00 "DMA0_DASHDW3,DMA Controller Channel Configuration Destination Address Shadow Register Channel 3" rgroup.long 0x11C++0x03 line.long 0x00 "DMA0_DASHDW4,DMA Controller Channel Configuration Destination Address Shadow Register Channel 4" rgroup.long 0x15C++0x03 line.long 0x00 "DMA0_DASHDW5,DMA Controller Channel Configuration Destination Address Shadow Register Channel 5" rgroup.long 0x19C++0x03 line.long 0x00 "DMA0_DASHDW6,DMA Controller Channel Configuration Destination Address Shadow Register Channel 6" rgroup.long 0x1DC++0x03 line.long 0x00 "DMA0_DASHDW7,DMA Controller Channel Configuration Destination Address Shadow Register Channel 7" rgroup.long 0x21C++0x03 line.long 0x00 "DMA0_DASHDW8,DMA Controller Channel Configuration Destination Address Shadow Register Channel 8" rgroup.long 0x25C++0x03 line.long 0x00 "DMA0_DASHDW9,DMA Controller Channel Configuration Destination Address Shadow Register Channel 9" rgroup.long 0x29C++0x03 line.long 0x00 "DMA0_DASHDW10,DMA Controller Channel Configuration Destination Address Shadow Register Channel 10" rgroup.long 0x2DC++0x03 line.long 0x00 "DMA0_DASHDW11,DMA Controller Channel Configuration Destination Address Shadow Register Channel 11" rgroup.long 0x31C++0x03 line.long 0x00 "DMA0_DASHDW12,DMA Controller Channel Configuration Destination Address Shadow Register Channel 12" rgroup.long 0x35C++0x03 line.long 0x00 "DMA0_DASHDW13,DMA Controller Channel Configuration Destination Address Shadow Register Channel 13" rgroup.long 0x39C++0x03 line.long 0x00 "DMA0_DASHDW14,DMA Controller Channel Configuration Destination Address Shadow Register Channel 14" rgroup.long 0x3DC++0x03 line.long 0x00 "DMA0_DASHDW15,DMA Controller Channel Configuration Destination Address Shadow Register Channel 15" tree.end tree "CMICIC" sif (cpuis("S6J336*")||cpuis("S6J337*")) group.long 0x2024++0x03 line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2028++0x03 line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x202C++0x03 line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2030++0x03 line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2034++0x03 line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2038++0x03 line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x203C++0x03 line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2040++0x03 line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2044++0x03 line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2048++0x03 line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x204C++0x03 line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2050++0x03 line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2054++0x03 line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2058++0x03 line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x205C++0x03 line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2060++0x03 line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2064++0x03 line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2068++0x03 line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x206C++0x03 line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2070++0x03 line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2074++0x03 line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2078++0x03 line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x207C++0x03 line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2080++0x03 line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2084++0x03 line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2088++0x03 line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x208C++0x03 line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2090++0x03 line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2094++0x03 line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2098++0x03 line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x209C++0x03 line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20A0++0x03 line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20A4++0x03 line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20E0++0x03 line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20E4++0x03 line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20E8++0x03 line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20EC++0x03 line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20F0++0x03 line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20F4++0x03 line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20F8++0x03 line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20FC++0x03 line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2100++0x03 line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2104++0x03 line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2108++0x03 line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x210C++0x03 line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2110++0x03 line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2114++0x03 line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2118++0x03 line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x211C++0x03 line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2120++0x03 line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2124++0x03 line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2128++0x03 line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x212C++0x03 line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2130++0x03 line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2134++0x03 line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2138++0x03 line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x213C++0x03 line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2140++0x03 line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2144++0x03 line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2148++0x03 line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x214C++0x03 line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2150++0x03 line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2154++0x03 line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2158++0x03 line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x215C++0x03 line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2160++0x03 line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2164++0x03 line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2168++0x03 line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x216C++0x03 line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2170++0x03 line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2174++0x03 line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2178++0x03 line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x218C++0x03 line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2190++0x03 line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2194++0x03 line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2198++0x03 line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x219C++0x03 line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21A8++0x03 line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21AC++0x03 line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21B0++0x03 line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21B4++0x03 line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21B8++0x03 line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21BC++0x03 line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21C0++0x03 line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21C8++0x03 line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21CC++0x03 line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21D0++0x03 line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21D4++0x03 line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21D8++0x03 line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21DC++0x03 line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21E0++0x03 line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21E4++0x03 line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21E8++0x03 line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21EC++0x03 line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21F0++0x03 line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21F4++0x03 line.long 0x00 "DMA0_CMICIC125,DMA Controller Client Matrix Internal Client Interface Configuration Register 125" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" else group.long 0x2020++0x03 line.long 0x00 "DMA0_CMICIC8,DMA Controller Client Matrix Internal Client Interface Configuration Register 8" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2024++0x03 line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2028++0x03 line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x202C++0x03 line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2030++0x03 line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2034++0x03 line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2038++0x03 line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x203C++0x03 line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2040++0x03 line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2044++0x03 line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2048++0x03 line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x204C++0x03 line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2050++0x03 line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2054++0x03 line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2058++0x03 line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x205C++0x03 line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2060++0x03 line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2064++0x03 line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2068++0x03 line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x206C++0x03 line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2070++0x03 line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2074++0x03 line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2078++0x03 line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x207C++0x03 line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2080++0x03 line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2084++0x03 line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2088++0x03 line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x208C++0x03 line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2090++0x03 line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2094++0x03 line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2098++0x03 line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x209C++0x03 line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20A0++0x03 line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20A4++0x03 line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20A8++0x03 line.long 0x00 "DMA0_CMICIC42,DMA Controller Client Matrix Internal Client Interface Configuration Register 42" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20AC++0x03 line.long 0x00 "DMA0_CMICIC43,DMA Controller Client Matrix Internal Client Interface Configuration Register 43" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20B0++0x03 line.long 0x00 "DMA0_CMICIC44,DMA Controller Client Matrix Internal Client Interface Configuration Register 44" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20B4++0x03 line.long 0x00 "DMA0_CMICIC45,DMA Controller Client Matrix Internal Client Interface Configuration Register 45" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20B8++0x03 line.long 0x00 "DMA0_CMICIC46,DMA Controller Client Matrix Internal Client Interface Configuration Register 46" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20BC++0x03 line.long 0x00 "DMA0_CMICIC47,DMA Controller Client Matrix Internal Client Interface Configuration Register 47" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20C0++0x03 line.long 0x00 "DMA0_CMICIC48,DMA Controller Client Matrix Internal Client Interface Configuration Register 48" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20C4++0x03 line.long 0x00 "DMA0_CMICIC49,DMA Controller Client Matrix Internal Client Interface Configuration Register 49" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20C8++0x03 line.long 0x00 "DMA0_CMICIC50,DMA Controller Client Matrix Internal Client Interface Configuration Register 50" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20CC++0x03 line.long 0x00 "DMA0_CMICIC51,DMA Controller Client Matrix Internal Client Interface Configuration Register 51" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20D0++0x03 line.long 0x00 "DMA0_CMICIC52,DMA Controller Client Matrix Internal Client Interface Configuration Register 52" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20D4++0x03 line.long 0x00 "DMA0_CMICIC53,DMA Controller Client Matrix Internal Client Interface Configuration Register 53" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20D8++0x03 line.long 0x00 "DMA0_CMICIC54,DMA Controller Client Matrix Internal Client Interface Configuration Register 54" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20DC++0x03 line.long 0x00 "DMA0_CMICIC55,DMA Controller Client Matrix Internal Client Interface Configuration Register 55" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20E0++0x03 line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20E4++0x03 line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20E8++0x03 line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20EC++0x03 line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20F0++0x03 line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20F4++0x03 line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20F8++0x03 line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20FC++0x03 line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2100++0x03 line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2104++0x03 line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2108++0x03 line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x210C++0x03 line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2110++0x03 line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2114++0x03 line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2118++0x03 line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x211C++0x03 line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2120++0x03 line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2124++0x03 line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2128++0x03 line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x212C++0x03 line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2130++0x03 line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2134++0x03 line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2138++0x03 line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x213C++0x03 line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2140++0x03 line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2144++0x03 line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2148++0x03 line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x214C++0x03 line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2150++0x03 line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2154++0x03 line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2158++0x03 line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x215C++0x03 line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2160++0x03 line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2164++0x03 line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2168++0x03 line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x216C++0x03 line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2170++0x03 line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2174++0x03 line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2178++0x03 line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x217C++0x03 line.long 0x00 "DMA0_CMICIC95,DMA Controller Client Matrix Internal Client Interface Configuration Register 95" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2180++0x03 line.long 0x00 "DMA0_CMICIC96,DMA Controller Client Matrix Internal Client Interface Configuration Register 96" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2184++0x03 line.long 0x00 "DMA0_CMICIC97,DMA Controller Client Matrix Internal Client Interface Configuration Register 97" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2188++0x03 line.long 0x00 "DMA0_CMICIC98,DMA Controller Client Matrix Internal Client Interface Configuration Register 98" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x218C++0x03 line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2190++0x03 line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2194++0x03 line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2198++0x03 line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x219C++0x03 line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21A0++0x03 line.long 0x00 "DMA0_CMICIC104,DMA Controller Client Matrix Internal Client Interface Configuration Register 104" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21A4++0x03 line.long 0x00 "DMA0_CMICIC105,DMA Controller Client Matrix Internal Client Interface Configuration Register 105" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21A8++0x03 line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21AC++0x03 line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21B0++0x03 line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21B4++0x03 line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21B8++0x03 line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21BC++0x03 line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21C0++0x03 line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21C4++0x03 line.long 0x00 "DMA0_CMICIC113,DMA Controller Client Matrix Internal Client Interface Configuration Register 113" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21C8++0x03 line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21CC++0x03 line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21D0++0x03 line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21D4++0x03 line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21D8++0x03 line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21DC++0x03 line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21E0++0x03 line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21E4++0x03 line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21E8++0x03 line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21EC++0x03 line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21F0++0x03 line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" endif tree.end tree "CMCHIC 0-15" group.long 0x2800++0x03 line.long 0x00 "DMA0_CMCHIC0,DMA Controller Client Matrix Channel Interface Configuration Register 0" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2804++0x03 line.long 0x00 "DMA0_CMCHIC1,DMA Controller Client Matrix Channel Interface Configuration Register 1" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2808++0x03 line.long 0x00 "DMA0_CMCHIC2,DMA Controller Client Matrix Channel Interface Configuration Register 2" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x280C++0x03 line.long 0x00 "DMA0_CMCHIC3,DMA Controller Client Matrix Channel Interface Configuration Register 3" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2810++0x03 line.long 0x00 "DMA0_CMCHIC4,DMA Controller Client Matrix Channel Interface Configuration Register 4" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2814++0x03 line.long 0x00 "DMA0_CMCHIC5,DMA Controller Client Matrix Channel Interface Configuration Register 5" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2818++0x03 line.long 0x00 "DMA0_CMCHIC6,DMA Controller Client Matrix Channel Interface Configuration Register 6" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x281C++0x03 line.long 0x00 "DMA0_CMCHIC7,DMA Controller Client Matrix Channel Interface Configuration Register 7" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2820++0x03 line.long 0x00 "DMA0_CMCHIC8,DMA Controller Client Matrix Channel Interface Configuration Register 8" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2824++0x03 line.long 0x00 "DMA0_CMCHIC9,DMA Controller Client Matrix Channel Interface Configuration Register 9" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2828++0x03 line.long 0x00 "DMA0_CMCHIC10,DMA Controller Client Matrix Channel Interface Configuration Register 10" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x282C++0x03 line.long 0x00 "DMA0_CMCHIC11,DMA Controller Client Matrix Channel Interface Configuration Register 11" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2830++0x03 line.long 0x00 "DMA0_CMCHIC12,DMA Controller Client Matrix Channel Interface Configuration Register 12" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2834++0x03 line.long 0x00 "DMA0_CMCHIC13,DMA Controller Client Matrix Channel Interface Configuration Register 13" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2838++0x03 line.long 0x00 "DMA0_CMCHIC14,DMA Controller Client Matrix Channel Interface Configuration Register 14" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x283C++0x03 line.long 0x00 "DMA0_CMCHIC15,DMA Controller Client Matrix Channel Interface Configuration Register 15" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif tree.end width 0x0B else width 13. group.long 0x1000++0x03 line.long 0x00 "DMA0_R,DMA Controller Global Configuration Register" bitfld.long 0x00 31. " DE ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 30. " DSHR ,DMA stop/halt request flag" "Not requested,Requested" bitfld.long 0x00 29. " DBE ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 27.--28. " PR ,Priority type" "Fixed,Dynamic,Round robin,?..." bitfld.long 0x00 26. " DH ,DMA halt" "Not halted,Halted" bitfld.long 0x00 24.--25. " DB ,Debug behavior" "Continues,Halted,Stopped,?..." newline rbitfld.long 0x00 0. " DSHS ,DMA stop/halt status flag" "Running,Halted" rgroup.long 0x1004++0x03 line.long 0x00 "DMA0_DIRQ1,DMA Controller Global Completion Interrupt 1 Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") bitfld.long 0x00 31. " DIRQ_[31] ,Global Completion interrupt 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Global Completion interrupt 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Global Completion interrupt 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Global Completion interrupt 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Global Completion interrupt 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Global Completion interrupt 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Global Completion interrupt 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Global Completion interrupt 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Global Completion interrupt 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Global Completion interrupt 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Global Completion interrupt 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Global Completion interrupt 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Global Completion interrupt 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Global Completion interrupt 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Global Completion interrupt 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Global Completion interrupt 16" "No interrupt,Interrupt" newline endif bitfld.long 0x00 15. " [15] ,Global Completion interrupt 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Global Completion interrupt 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Global Completion interrupt 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Global Completion interrupt 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Global Completion interrupt 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Global Completion interrupt 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Global Completion interrupt 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Global Completion interrupt 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Global Completion interrupt 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Global Completion interrupt 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Global Completion interrupt 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Global Completion interrupt 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Global Completion interrupt 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Global Completion interrupt 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Global Completion interrupt 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Global Completion interrupt 0" "No interrupt,Interrupt" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") rgroup.long 0x1008++0x03 line.long 0x00 "DMA0_DIRQ2,DMA Controller Global Completion Interrupt 2 Register" bitfld.long 0x00 31. " DIRQ_[63] ,Global Completion interrupt 63" "No interrupt,Interrupt" bitfld.long 0x00 30. " [62] ,Global Completion interrupt 62" "No interrupt,Interrupt" bitfld.long 0x00 29. " [61] ,Global Completion interrupt 61" "No interrupt,Interrupt" bitfld.long 0x00 28. " [60] ,Global Completion interrupt 60" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [59] ,Global Completion interrupt 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " [58] ,Global Completion interrupt 58" "No interrupt,Interrupt" bitfld.long 0x00 25. " [57] ,Global Completion interrupt 57" "No interrupt,Interrupt" bitfld.long 0x00 24. " [56] ,Global Completion interrupt 56" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [55] ,Global Completion interrupt 55" "No interrupt,Interrupt" bitfld.long 0x00 22. " [54] ,Global Completion interrupt 54" "No interrupt,Interrupt" bitfld.long 0x00 21. " [53] ,Global Completion interrupt 53" "No interrupt,Interrupt" bitfld.long 0x00 20. " [52] ,Global Completion interrupt 52" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [51] ,Global Completion interrupt 51" "No interrupt,Interrupt" bitfld.long 0x00 18. " [50] ,Global Completion interrupt 50" "No interrupt,Interrupt" bitfld.long 0x00 17. " [49] ,Global Completion interrupt 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " [48] ,Global Completion interrupt 48" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [47] ,Global Completion interrupt 47" "No interrupt,Interrupt" bitfld.long 0x00 14. " [46] ,Global Completion interrupt 46" "No interrupt,Interrupt" bitfld.long 0x00 13. " [45] ,Global Completion interrupt 45" "No interrupt,Interrupt" bitfld.long 0x00 12. " [44] ,Global Completion interrupt 44" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [43] ,Global Completion interrupt 43" "No interrupt,Interrupt" bitfld.long 0x00 10. " [42] ,Global Completion interrupt 42" "No interrupt,Interrupt" bitfld.long 0x00 9. " [41] ,Global Completion interrupt 41" "No interrupt,Interrupt" bitfld.long 0x00 8. " [40] ,Global Completion interrupt 40" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [39] ,Global Completion interrupt 39" "No interrupt,Interrupt" bitfld.long 0x00 6. " [38] ,Global Completion interrupt 38" "No interrupt,Interrupt" bitfld.long 0x00 5. " [37] ,Global Completion interrupt 37" "No interrupt,Interrupt" bitfld.long 0x00 4. " [36] ,Global Completion interrupt 36" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [35] ,Global Completion interrupt 35" "No interrupt,Interrupt" bitfld.long 0x00 2. " [34] ,Global Completion interrupt 34" "No interrupt,Interrupt" bitfld.long 0x00 1. " [33] ,Global Completion interrupt 33" "No interrupt,Interrupt" bitfld.long 0x00 0. " [32] ,Global Completion interrupt 32" "No interrupt,Interrupt" endif rgroup.long 0x100C++0x03 line.long 0x00 "DMA0_EDIRQ1,DMA Controller Global Error Interrupt 1 Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") bitfld.long 0x00 31. " EDIRQ_[31] ,Global error interrupt 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,Global error interrupt 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,Global error interrupt 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,Global error interrupt 28" "Not occurred,Occurred" newline bitfld.long 0x00 27. " [27] ,Global error interrupt 27" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,Global error interrupt 26" "Not occurred,Occurred" bitfld.long 0x00 25. " [25] ,Global error interrupt 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,Global error interrupt 24" "Not occurred,Occurred" newline bitfld.long 0x00 23. " [23] ,Global error interrupt 23" "Not occurred,Occurred" bitfld.long 0x00 22. " [22] ,Global error interrupt 22" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,Global error interrupt 21" "Not occurred,Occurred" bitfld.long 0x00 20. " [20] ,Global error interrupt 20" "Not occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Global error interrupt 19" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,Global error interrupt 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,Global error interrupt 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,Global error interrupt 16" "Not occurred,Occurred" newline endif bitfld.long 0x00 15. " [15] ,Global error interrupt 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,Global error interrupt 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,Global error interrupt 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,Global error interrupt 12" "Not occurred,Occurred" newline bitfld.long 0x00 11. " [11] ,Global error interrupt 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,Global error interrupt 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,Global error interrupt 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,Global error interrupt 8" "Not occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Global error interrupt 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,Global error interrupt 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,Global error interrupt 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Global error interrupt 4" "Not occurred,Occurred" newline bitfld.long 0x00 3. " [3] ,Global error interrupt 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Global error interrupt 2" "Not occurred,Occurred" bitfld.long 0x00 1. " [1] ,Global error interrupt 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Global error interrupt 0" "Not occurred,Occurred" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") rgroup.long 0x1010++0x03 line.long 0x00 "DMA0_EDIRQ2,DMA Controller Global Error Interrupt 2 Register" bitfld.long 0x00 31. " EDIRQ_[63] ,Global error interrupt 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,Global error interrupt 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,Global error interrupt 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,Global error interrupt 60" "Not occurred,Occurred" newline bitfld.long 0x00 27. " [59] ,Global error interrupt 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,Global error interrupt 58" "Not occurred,Occurred" bitfld.long 0x00 25. " [57] ,Global error interrupt 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,Global error interrupt 56" "Not occurred,Occurred" newline bitfld.long 0x00 23. " [55] ,Global error interrupt 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,Global error interrupt 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,Global error interrupt 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,Global error interrupt 52" "Not occurred,Occurred" newline bitfld.long 0x00 19. " [51] ,Global error interrupt 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,Global error interrupt 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,Global error interrupt 49" "Not occurred,Occurred" bitfld.long 0x00 16. " [48] ,Global error interrupt 48" "Not occurred,Occurred" newline bitfld.long 0x00 15. " [47] ,Global error interrupt 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,Global error interrupt 46" "Not occurred,Occurred" bitfld.long 0x00 13. " [45] ,Global error interrupt 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,Global error interrupt 44" "Not occurred,Occurred" newline bitfld.long 0x00 11. " [43] ,Global error interrupt 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,Global error interrupt 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,Global error interrupt 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,Global error interrupt 40" "Not occurred,Occurred" newline bitfld.long 0x00 7. " [39] ,Global error interrupt 39" "Not occurred,Occurred" bitfld.long 0x00 6. " [38] ,Global error interrupt 38" "Not occurred,Occurred" bitfld.long 0x00 5. " [37] ,Global error interrupt 37" "Not occurred,Occurred" bitfld.long 0x00 4. " [36] ,Global error interrupt 36" "Not occurred,Occurred" newline bitfld.long 0x00 3. " [35] ,Global error interrupt 35" "Not occurred,Occurred" bitfld.long 0x00 2. " [34] ,Global error interrupt 34" "Not occurred,Occurred" bitfld.long 0x00 1. " [33] ,Global error interrupt 33" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,Global error interrupt 32" "Not occurred,Occurred" endif rgroup.long 0x1014++0x03 line.long 0x00 "DMA0_ID,DMA Controller ID Register" width 12. tree "DMA_A 0--15" group.long 0x0++0x03 line.long 0x00 "DMA0_A0,DMA Controller Channel Configuration A Register Channel 0" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x40++0x03 line.long 0x00 "DMA0_A1,DMA Controller Channel Configuration A Register Channel 1" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x80++0x03 line.long 0x00 "DMA0_A2,DMA Controller Channel Configuration A Register Channel 2" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0xC0++0x03 line.long 0x00 "DMA0_A3,DMA Controller Channel Configuration A Register Channel 3" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x100++0x03 line.long 0x00 "DMA0_A4,DMA Controller Channel Configuration A Register Channel 4" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x140++0x03 line.long 0x00 "DMA0_A5,DMA Controller Channel Configuration A Register Channel 5" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x180++0x03 line.long 0x00 "DMA0_A6,DMA Controller Channel Configuration A Register Channel 6" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x1C0++0x03 line.long 0x00 "DMA0_A7,DMA Controller Channel Configuration A Register Channel 7" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x200++0x03 line.long 0x00 "DMA0_A8,DMA Controller Channel Configuration A Register Channel 8" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x240++0x03 line.long 0x00 "DMA0_A9,DMA Controller Channel Configuration A Register Channel 9" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x280++0x03 line.long 0x00 "DMA0_A10,DMA Controller Channel Configuration A Register Channel 10" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x2C0++0x03 line.long 0x00 "DMA0_A11,DMA Controller Channel Configuration A Register Channel 11" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x300++0x03 line.long 0x00 "DMA0_A12,DMA Controller Channel Configuration A Register Channel 12" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x340++0x03 line.long 0x00 "DMA0_A13,DMA Controller Channel Configuration A Register Channel 13" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x380++0x03 line.long 0x00 "DMA0_A14,DMA Controller Channel Configuration A Register Channel 14" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x3C0++0x03 line.long 0x00 "DMA0_A15,DMA Controller Channel Configuration A Register Channel 15" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" tree.end tree "DMA_B 0--15" group.long 0x4++0x03 line.long 0x00 "DMA0_B0,DMA Controller Channel Configuration B Register Channel 0" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x44++0x03 line.long 0x00 "DMA0_B1,DMA Controller Channel Configuration B Register Channel 1" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x84++0x03 line.long 0x00 "DMA0_B2,DMA Controller Channel Configuration B Register Channel 2" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0xC4++0x03 line.long 0x00 "DMA0_B3,DMA Controller Channel Configuration B Register Channel 3" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x104++0x03 line.long 0x00 "DMA0_B4,DMA Controller Channel Configuration B Register Channel 4" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x144++0x03 line.long 0x00 "DMA0_B5,DMA Controller Channel Configuration B Register Channel 5" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x184++0x03 line.long 0x00 "DMA0_B6,DMA Controller Channel Configuration B Register Channel 6" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x1C4++0x03 line.long 0x00 "DMA0_B7,DMA Controller Channel Configuration B Register Channel 7" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x204++0x03 line.long 0x00 "DMA0_B8,DMA Controller Channel Configuration B Register Channel 8" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x244++0x03 line.long 0x00 "DMA0_B9,DMA Controller Channel Configuration B Register Channel 9" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x284++0x03 line.long 0x00 "DMA0_B10,DMA Controller Channel Configuration B Register Channel 10" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x2C4++0x03 line.long 0x00 "DMA0_B11,DMA Controller Channel Configuration B Register Channel 11" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x304++0x03 line.long 0x00 "DMA0_B12,DMA Controller Channel Configuration B Register Channel 12" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x344++0x03 line.long 0x00 "DMA0_B13,DMA Controller Channel Configuration B Register Channel 13" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x384++0x03 line.long 0x00 "DMA0_B14,DMA Controller Channel Configuration B Register Channel 14" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x3C4++0x03 line.long 0x00 "DMA0_B15,DMA Controller Channel Configuration B Register Channel 15" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable" bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable" bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" tree.end tree "DMA_SA 0--15" group.long 0x8++0x03 line.long 0x00 "DMA0_SA0,DMA Controller Channel Configuration Source Address Register Channel 0" group.long 0x48++0x03 line.long 0x00 "DMA0_SA1,DMA Controller Channel Configuration Source Address Register Channel 1" group.long 0x88++0x03 line.long 0x00 "DMA0_SA2,DMA Controller Channel Configuration Source Address Register Channel 2" group.long 0xC8++0x03 line.long 0x00 "DMA0_SA3,DMA Controller Channel Configuration Source Address Register Channel 3" group.long 0x108++0x03 line.long 0x00 "DMA0_SA4,DMA Controller Channel Configuration Source Address Register Channel 4" group.long 0x148++0x03 line.long 0x00 "DMA0_SA5,DMA Controller Channel Configuration Source Address Register Channel 5" group.long 0x188++0x03 line.long 0x00 "DMA0_SA6,DMA Controller Channel Configuration Source Address Register Channel 6" group.long 0x1C8++0x03 line.long 0x00 "DMA0_SA7,DMA Controller Channel Configuration Source Address Register Channel 7" group.long 0x208++0x03 line.long 0x00 "DMA0_SA8,DMA Controller Channel Configuration Source Address Register Channel 8" group.long 0x248++0x03 line.long 0x00 "DMA0_SA9,DMA Controller Channel Configuration Source Address Register Channel 9" group.long 0x288++0x03 line.long 0x00 "DMA0_SA10,DMA Controller Channel Configuration Source Address Register Channel 10" group.long 0x2C8++0x03 line.long 0x00 "DMA0_SA11,DMA Controller Channel Configuration Source Address Register Channel 11" group.long 0x308++0x03 line.long 0x00 "DMA0_SA12,DMA Controller Channel Configuration Source Address Register Channel 12" group.long 0x348++0x03 line.long 0x00 "DMA0_SA13,DMA Controller Channel Configuration Source Address Register Channel 13" group.long 0x388++0x03 line.long 0x00 "DMA0_SA14,DMA Controller Channel Configuration Source Address Register Channel 14" group.long 0x3C8++0x03 line.long 0x00 "DMA0_SA15,DMA Controller Channel Configuration Source Address Register Channel 15" tree.end tree "DMA_DA 0--15" group.long 0xC++0x03 line.long 0x00 "DMA0_DA0,DMA Controller Channel Configuration Destination Address Register Channel 0" group.long 0x4C++0x03 line.long 0x00 "DMA0_DA1,DMA Controller Channel Configuration Destination Address Register Channel 1" group.long 0x8C++0x03 line.long 0x00 "DMA0_DA2,DMA Controller Channel Configuration Destination Address Register Channel 2" group.long 0xCC++0x03 line.long 0x00 "DMA0_DA3,DMA Controller Channel Configuration Destination Address Register Channel 3" group.long 0x10C++0x03 line.long 0x00 "DMA0_DA4,DMA Controller Channel Configuration Destination Address Register Channel 4" group.long 0x14C++0x03 line.long 0x00 "DMA0_DA5,DMA Controller Channel Configuration Destination Address Register Channel 5" group.long 0x18C++0x03 line.long 0x00 "DMA0_DA6,DMA Controller Channel Configuration Destination Address Register Channel 6" group.long 0x1CC++0x03 line.long 0x00 "DMA0_DA7,DMA Controller Channel Configuration Destination Address Register Channel 7" group.long 0x20C++0x03 line.long 0x00 "DMA0_DA8,DMA Controller Channel Configuration Destination Address Register Channel 8" group.long 0x24C++0x03 line.long 0x00 "DMA0_DA9,DMA Controller Channel Configuration Destination Address Register Channel 9" group.long 0x28C++0x03 line.long 0x00 "DMA0_DA10,DMA Controller Channel Configuration Destination Address Register Channel 10" group.long 0x2CC++0x03 line.long 0x00 "DMA0_DA11,DMA Controller Channel Configuration Destination Address Register Channel 11" group.long 0x30C++0x03 line.long 0x00 "DMA0_DA12,DMA Controller Channel Configuration Destination Address Register Channel 12" group.long 0x34C++0x03 line.long 0x00 "DMA0_DA13,DMA Controller Channel Configuration Destination Address Register Channel 13" group.long 0x38C++0x03 line.long 0x00 "DMA0_DA14,DMA Controller Channel Configuration Destination Address Register Channel 14" group.long 0x3CC++0x03 line.long 0x00 "DMA0_DA15,DMA Controller Channel Configuration Destination Address Register Channel 15" tree.end tree "DMA_C 0--15" group.long 0x10++0x03 line.long 0x00 "DMA0_C0,DMA Controller Channel Configuration C Register Channel 0" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x50++0x03 line.long 0x00 "DMA0_C1,DMA Controller Channel Configuration C Register Channel 1" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x90++0x03 line.long 0x00 "DMA0_C2,DMA Controller Channel Configuration C Register Channel 2" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0xD0++0x03 line.long 0x00 "DMA0_C3,DMA Controller Channel Configuration C Register Channel 3" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x110++0x03 line.long 0x00 "DMA0_C4,DMA Controller Channel Configuration C Register Channel 4" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x150++0x03 line.long 0x00 "DMA0_C5,DMA Controller Channel Configuration C Register Channel 5" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x190++0x03 line.long 0x00 "DMA0_C6,DMA Controller Channel Configuration C Register Channel 6" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x1D0++0x03 line.long 0x00 "DMA0_C7,DMA Controller Channel Configuration C Register Channel 7" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x210++0x03 line.long 0x00 "DMA0_C8,DMA Controller Channel Configuration C Register Channel 8" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x250++0x03 line.long 0x00 "DMA0_C9,DMA Controller Channel Configuration C Register Channel 9" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x290++0x03 line.long 0x00 "DMA0_C10,DMA Controller Channel Configuration C Register Channel 10" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x2D0++0x03 line.long 0x00 "DMA0_C11,DMA Controller Channel Configuration C Register Channel 11" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x310++0x03 line.long 0x00 "DMA0_C12,DMA Controller Channel Configuration C Register Channel 12" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x350++0x03 line.long 0x00 "DMA0_C13,DMA Controller Channel Configuration C Register Channel 13" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x390++0x03 line.long 0x00 "DMA0_C14,DMA Controller Channel Configuration C Register Channel 14" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x3D0++0x03 line.long 0x00 "DMA0_C15,DMA Controller Channel Configuration C Register Channel 15" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" tree.end tree "DMA_D 0--15" sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00) group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00) group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00) group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x15++0x00 line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00) group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00) group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00) group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x55++0x00 line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00) group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00) group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00) group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x95++0x00 line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00) group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00) group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00) group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0xD5++0x00 line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00) group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00) group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00) group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x115++0x00 line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00) group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00) group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00) group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x155++0x00 line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00) group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00) group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00) group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x195++0x00 line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00) group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00) group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00) group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x1D5++0x00 line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00) group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00) group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00) group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x215++0x00 line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00) group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00) group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00) group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x255++0x00 line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00) group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00) group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00) group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x295++0x00 line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00) group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00) group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00) group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x2D5++0x00 line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00) group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00) group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00) group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x315++0x00 line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00) group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00) group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00) group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x355++0x00 line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00) group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00) group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00) group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x395++0x00 line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00) group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" endif else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00) group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated" bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00) group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed" else group.byte 0x3D5++0x00 line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00) group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00) group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00) group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x17++0x00 line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00) group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00) group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00) group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x57++0x00 line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00) group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00) group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00) group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x97++0x00 line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00) group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00) group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00) group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0xD7++0x00 line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00) group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00) group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00) group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x117++0x00 line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00) group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00) group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00) group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x157++0x00 line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00) group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00) group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00) group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x197++0x00 line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00) group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00) group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00) group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x1D7++0x00 line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00) group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00) group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00) group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x217++0x00 line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00) group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00) group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00) group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x257++0x00 line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00) group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00) group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00) group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x297++0x00 line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00) group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00) group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00) group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x2D7++0x00 line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00) group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00) group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00) group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x317++0x00 line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00) group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00) group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00) group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x357++0x00 line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00) group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00) group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00) group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x397++0x00 line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000) if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00) group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline textfld " " bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" endif else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00) if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00) group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented" newline bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated" bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif else if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00) group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" newline bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed" else group.byte 0x3D7++0x00 line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register" bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed" endif endif endif tree.end sif !cpuis("S6J320CKSA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J336*")&&!cpuis("S6J337*") tree "DMA_E 0--15" group.long 0x20++0x03 line.long 0x00 "DMA0_E0,DMA Controller Channel Configuration E Register Channel 0" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x60++0x03 line.long 0x00 "DMA0_E1,DMA Controller Channel Configuration E Register Channel 1" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0xA0++0x03 line.long 0x00 "DMA0_E2,DMA Controller Channel Configuration E Register Channel 2" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0xE0++0x03 line.long 0x00 "DMA0_E3,DMA Controller Channel Configuration E Register Channel 3" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x120++0x03 line.long 0x00 "DMA0_E4,DMA Controller Channel Configuration E Register Channel 4" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x160++0x03 line.long 0x00 "DMA0_E5,DMA Controller Channel Configuration E Register Channel 5" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x1A0++0x03 line.long 0x00 "DMA0_E6,DMA Controller Channel Configuration E Register Channel 6" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x1E0++0x03 line.long 0x00 "DMA0_E7,DMA Controller Channel Configuration E Register Channel 7" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x220++0x03 line.long 0x00 "DMA0_E8,DMA Controller Channel Configuration E Register Channel 8" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x260++0x03 line.long 0x00 "DMA0_E9,DMA Controller Channel Configuration E Register Channel 9" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x2A0++0x03 line.long 0x00 "DMA0_E10,DMA Controller Channel Configuration E Register Channel 10" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x2E0++0x03 line.long 0x00 "DMA0_E11,DMA Controller Channel Configuration E Register Channel 11" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x320++0x03 line.long 0x00 "DMA0_E12,DMA Controller Channel Configuration E Register Channel 12" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x360++0x03 line.long 0x00 "DMA0_E13,DMA Controller Channel Configuration E Register Channel 13" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x3A0++0x03 line.long 0x00 "DMA0_E14,DMA Controller Channel Configuration E Register Channel 14" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif group.long 0x3E0++0x03 line.long 0x00 "DMA0_E15,DMA Controller Channel Configuration E Register Channel 15" sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA") bitfld.long 0x00 31. " EE ,EE" "0,1" hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" newline else hexmask.long.word 0x00 16.--30. 1. " DC ,DC" hexmask.long.word 0x00 0.--15. 1. " IC ,IC" endif tree.end endif width 15. tree "DMA_SASHDW DMA_DASHDW 0-15" rgroup.long 0x18++0x03 line.long 0x00 "DMA0_SASHDW0,DMA Controller Channel Configuration Source Address Shadow Register Channel 0" rgroup.long 0x58++0x03 line.long 0x00 "DMA0_SASHDW1,DMA Controller Channel Configuration Source Address Shadow Register Channel 1" rgroup.long 0x98++0x03 line.long 0x00 "DMA0_SASHDW2,DMA Controller Channel Configuration Source Address Shadow Register Channel 2" rgroup.long 0xD8++0x03 line.long 0x00 "DMA0_SASHDW3,DMA Controller Channel Configuration Source Address Shadow Register Channel 3" rgroup.long 0x118++0x03 line.long 0x00 "DMA0_SASHDW4,DMA Controller Channel Configuration Source Address Shadow Register Channel 4" rgroup.long 0x158++0x03 line.long 0x00 "DMA0_SASHDW5,DMA Controller Channel Configuration Source Address Shadow Register Channel 5" rgroup.long 0x198++0x03 line.long 0x00 "DMA0_SASHDW6,DMA Controller Channel Configuration Source Address Shadow Register Channel 6" rgroup.long 0x1D8++0x03 line.long 0x00 "DMA0_SASHDW7,DMA Controller Channel Configuration Source Address Shadow Register Channel 7" rgroup.long 0x218++0x03 line.long 0x00 "DMA0_SASHDW8,DMA Controller Channel Configuration Source Address Shadow Register Channel 8" rgroup.long 0x258++0x03 line.long 0x00 "DMA0_SASHDW9,DMA Controller Channel Configuration Source Address Shadow Register Channel 9" rgroup.long 0x298++0x03 line.long 0x00 "DMA0_SASHDW10,DMA Controller Channel Configuration Source Address Shadow Register Channel 10" rgroup.long 0x2D8++0x03 line.long 0x00 "DMA0_SASHDW11,DMA Controller Channel Configuration Source Address Shadow Register Channel 11" rgroup.long 0x318++0x03 line.long 0x00 "DMA0_SASHDW12,DMA Controller Channel Configuration Source Address Shadow Register Channel 12" rgroup.long 0x358++0x03 line.long 0x00 "DMA0_SASHDW13,DMA Controller Channel Configuration Source Address Shadow Register Channel 13" rgroup.long 0x398++0x03 line.long 0x00 "DMA0_SASHDW14,DMA Controller Channel Configuration Source Address Shadow Register Channel 14" rgroup.long 0x3D8++0x03 line.long 0x00 "DMA0_SASHDW15,DMA Controller Channel Configuration Source Address Shadow Register Channel 15" rgroup.long 0x1C++0x03 line.long 0x00 "DMA0_DASHDW0,DMA Controller Channel Configuration Destination Address Shadow Register Channel 0" rgroup.long 0x5C++0x03 line.long 0x00 "DMA0_DASHDW1,DMA Controller Channel Configuration Destination Address Shadow Register Channel 1" rgroup.long 0x9C++0x03 line.long 0x00 "DMA0_DASHDW2,DMA Controller Channel Configuration Destination Address Shadow Register Channel 2" rgroup.long 0xDC++0x03 line.long 0x00 "DMA0_DASHDW3,DMA Controller Channel Configuration Destination Address Shadow Register Channel 3" rgroup.long 0x11C++0x03 line.long 0x00 "DMA0_DASHDW4,DMA Controller Channel Configuration Destination Address Shadow Register Channel 4" rgroup.long 0x15C++0x03 line.long 0x00 "DMA0_DASHDW5,DMA Controller Channel Configuration Destination Address Shadow Register Channel 5" rgroup.long 0x19C++0x03 line.long 0x00 "DMA0_DASHDW6,DMA Controller Channel Configuration Destination Address Shadow Register Channel 6" rgroup.long 0x1DC++0x03 line.long 0x00 "DMA0_DASHDW7,DMA Controller Channel Configuration Destination Address Shadow Register Channel 7" rgroup.long 0x21C++0x03 line.long 0x00 "DMA0_DASHDW8,DMA Controller Channel Configuration Destination Address Shadow Register Channel 8" rgroup.long 0x25C++0x03 line.long 0x00 "DMA0_DASHDW9,DMA Controller Channel Configuration Destination Address Shadow Register Channel 9" rgroup.long 0x29C++0x03 line.long 0x00 "DMA0_DASHDW10,DMA Controller Channel Configuration Destination Address Shadow Register Channel 10" rgroup.long 0x2DC++0x03 line.long 0x00 "DMA0_DASHDW11,DMA Controller Channel Configuration Destination Address Shadow Register Channel 11" rgroup.long 0x31C++0x03 line.long 0x00 "DMA0_DASHDW12,DMA Controller Channel Configuration Destination Address Shadow Register Channel 12" rgroup.long 0x35C++0x03 line.long 0x00 "DMA0_DASHDW13,DMA Controller Channel Configuration Destination Address Shadow Register Channel 13" rgroup.long 0x39C++0x03 line.long 0x00 "DMA0_DASHDW14,DMA Controller Channel Configuration Destination Address Shadow Register Channel 14" rgroup.long 0x3DC++0x03 line.long 0x00 "DMA0_DASHDW15,DMA Controller Channel Configuration Destination Address Shadow Register Channel 15" tree.end tree "CMICIC" sif (cpuis("S6J336*")||cpuis("S6J337*")) group.long 0x2024++0x03 line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2028++0x03 line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x202C++0x03 line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2030++0x03 line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2034++0x03 line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2038++0x03 line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x203C++0x03 line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2040++0x03 line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2044++0x03 line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2048++0x03 line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x204C++0x03 line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2050++0x03 line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2054++0x03 line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2058++0x03 line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x205C++0x03 line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2060++0x03 line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2064++0x03 line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2068++0x03 line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x206C++0x03 line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2070++0x03 line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2074++0x03 line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2078++0x03 line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x207C++0x03 line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2080++0x03 line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2084++0x03 line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2088++0x03 line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x208C++0x03 line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2090++0x03 line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2094++0x03 line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2098++0x03 line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x209C++0x03 line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20A0++0x03 line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20A4++0x03 line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20E0++0x03 line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20E4++0x03 line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20E8++0x03 line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20EC++0x03 line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20F0++0x03 line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20F4++0x03 line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20F8++0x03 line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x20FC++0x03 line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2100++0x03 line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2104++0x03 line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2108++0x03 line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x210C++0x03 line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2110++0x03 line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2114++0x03 line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2118++0x03 line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x211C++0x03 line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2120++0x03 line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2124++0x03 line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2128++0x03 line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x212C++0x03 line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2130++0x03 line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2134++0x03 line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2138++0x03 line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x213C++0x03 line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2140++0x03 line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2144++0x03 line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2148++0x03 line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x214C++0x03 line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2150++0x03 line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2154++0x03 line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2158++0x03 line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x215C++0x03 line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2160++0x03 line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2164++0x03 line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2168++0x03 line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x216C++0x03 line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2170++0x03 line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2174++0x03 line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2178++0x03 line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x218C++0x03 line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2190++0x03 line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2194++0x03 line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2198++0x03 line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x219C++0x03 line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21A8++0x03 line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21AC++0x03 line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21B0++0x03 line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21B4++0x03 line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21B8++0x03 line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21BC++0x03 line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21C0++0x03 line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21C8++0x03 line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21CC++0x03 line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21D0++0x03 line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21D4++0x03 line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21D8++0x03 line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21DC++0x03 line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21E0++0x03 line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21E4++0x03 line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21E8++0x03 line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21EC++0x03 line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21F0++0x03 line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21F4++0x03 line.long 0x00 "DMA0_CMICIC125,DMA Controller Client Matrix Internal Client Interface Configuration Register 125" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21F8++0x03 line.long 0x00 "DMA0_CMICIC126,DMA Controller Client Matrix Internal Client Interface Configuration Register 126" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x21FC++0x03 line.long 0x00 "DMA0_CMICIC127,DMA Controller Client Matrix Internal Client Interface Configuration Register 127" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2200++0x03 line.long 0x00 "DMA0_CMICIC128,DMA Controller Client Matrix Internal Client Interface Configuration Register 128" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2204++0x03 line.long 0x00 "DMA0_CMICIC129,DMA Controller Client Matrix Internal Client Interface Configuration Register 129" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2208++0x03 line.long 0x00 "DMA0_CMICIC130,DMA Controller Client Matrix Internal Client Interface Configuration Register 130" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x220C++0x03 line.long 0x00 "DMA0_CMICIC131,DMA Controller Client Matrix Internal Client Interface Configuration Register 131" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2210++0x03 line.long 0x00 "DMA0_CMICIC132,DMA Controller Client Matrix Internal Client Interface Configuration Register 132" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2214++0x03 line.long 0x00 "DMA0_CMICIC133,DMA Controller Client Matrix Internal Client Interface Configuration Register 133" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2218++0x03 line.long 0x00 "DMA0_CMICIC134,DMA Controller Client Matrix Internal Client Interface Configuration Register 134" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x221C++0x03 line.long 0x00 "DMA0_CMICIC135,DMA Controller Client Matrix Internal Client Interface Configuration Register 135" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2220++0x03 line.long 0x00 "DMA0_CMICIC136,DMA Controller Client Matrix Internal Client Interface Configuration Register 136" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2224++0x03 line.long 0x00 "DMA0_CMICIC137,DMA Controller Client Matrix Internal Client Interface Configuration Register 137" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2228++0x03 line.long 0x00 "DMA0_CMICIC138,DMA Controller Client Matrix Internal Client Interface Configuration Register 138" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x222C++0x03 line.long 0x00 "DMA0_CMICIC139,DMA Controller Client Matrix Internal Client Interface Configuration Register 139" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2230++0x03 line.long 0x00 "DMA0_CMICIC140,DMA Controller Client Matrix Internal Client Interface Configuration Register 140" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2234++0x03 line.long 0x00 "DMA0_CMICIC141,DMA Controller Client Matrix Internal Client Interface Configuration Register 141" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2238++0x03 line.long 0x00 "DMA0_CMICIC142,DMA Controller Client Matrix Internal Client Interface Configuration Register 142" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x223C++0x03 line.long 0x00 "DMA0_CMICIC143,DMA Controller Client Matrix Internal Client Interface Configuration Register 143" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" else group.long 0x2020++0x03 line.long 0x00 "DMA0_CMICIC8,DMA Controller Client Matrix Internal Client Interface Configuration Register 8" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2024++0x03 line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled" group.long 0x2028++0x03 line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x202C++0x03 line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2030++0x03 line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2034++0x03 line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2038++0x03 line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x203C++0x03 line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2040++0x03 line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2044++0x03 line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2048++0x03 line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x204C++0x03 line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2050++0x03 line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2054++0x03 line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2058++0x03 line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x205C++0x03 line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2060++0x03 line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2064++0x03 line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2068++0x03 line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x206C++0x03 line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2070++0x03 line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2074++0x03 line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2078++0x03 line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x207C++0x03 line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2080++0x03 line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2084++0x03 line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2088++0x03 line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x208C++0x03 line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2090++0x03 line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2094++0x03 line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2098++0x03 line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x209C++0x03 line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20A0++0x03 line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20A4++0x03 line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20A8++0x03 line.long 0x00 "DMA0_CMICIC42,DMA Controller Client Matrix Internal Client Interface Configuration Register 42" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20AC++0x03 line.long 0x00 "DMA0_CMICIC43,DMA Controller Client Matrix Internal Client Interface Configuration Register 43" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20B0++0x03 line.long 0x00 "DMA0_CMICIC44,DMA Controller Client Matrix Internal Client Interface Configuration Register 44" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20B4++0x03 line.long 0x00 "DMA0_CMICIC45,DMA Controller Client Matrix Internal Client Interface Configuration Register 45" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20B8++0x03 line.long 0x00 "DMA0_CMICIC46,DMA Controller Client Matrix Internal Client Interface Configuration Register 46" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20BC++0x03 line.long 0x00 "DMA0_CMICIC47,DMA Controller Client Matrix Internal Client Interface Configuration Register 47" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20C0++0x03 line.long 0x00 "DMA0_CMICIC48,DMA Controller Client Matrix Internal Client Interface Configuration Register 48" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20C4++0x03 line.long 0x00 "DMA0_CMICIC49,DMA Controller Client Matrix Internal Client Interface Configuration Register 49" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20C8++0x03 line.long 0x00 "DMA0_CMICIC50,DMA Controller Client Matrix Internal Client Interface Configuration Register 50" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20CC++0x03 line.long 0x00 "DMA0_CMICIC51,DMA Controller Client Matrix Internal Client Interface Configuration Register 51" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20D0++0x03 line.long 0x00 "DMA0_CMICIC52,DMA Controller Client Matrix Internal Client Interface Configuration Register 52" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20D4++0x03 line.long 0x00 "DMA0_CMICIC53,DMA Controller Client Matrix Internal Client Interface Configuration Register 53" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20D8++0x03 line.long 0x00 "DMA0_CMICIC54,DMA Controller Client Matrix Internal Client Interface Configuration Register 54" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20DC++0x03 line.long 0x00 "DMA0_CMICIC55,DMA Controller Client Matrix Internal Client Interface Configuration Register 55" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20E0++0x03 line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20E4++0x03 line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20E8++0x03 line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20EC++0x03 line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20F0++0x03 line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20F4++0x03 line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20F8++0x03 line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x20FC++0x03 line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2100++0x03 line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2104++0x03 line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2108++0x03 line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x210C++0x03 line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2110++0x03 line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2114++0x03 line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2118++0x03 line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x211C++0x03 line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2120++0x03 line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2124++0x03 line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2128++0x03 line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x212C++0x03 line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2130++0x03 line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2134++0x03 line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2138++0x03 line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x213C++0x03 line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2140++0x03 line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2144++0x03 line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2148++0x03 line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x214C++0x03 line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2150++0x03 line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2154++0x03 line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2158++0x03 line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x215C++0x03 line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2160++0x03 line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2164++0x03 line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2168++0x03 line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x216C++0x03 line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2170++0x03 line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2174++0x03 line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2178++0x03 line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x217C++0x03 line.long 0x00 "DMA0_CMICIC95,DMA Controller Client Matrix Internal Client Interface Configuration Register 95" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2180++0x03 line.long 0x00 "DMA0_CMICIC96,DMA Controller Client Matrix Internal Client Interface Configuration Register 96" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2184++0x03 line.long 0x00 "DMA0_CMICIC97,DMA Controller Client Matrix Internal Client Interface Configuration Register 97" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2188++0x03 line.long 0x00 "DMA0_CMICIC98,DMA Controller Client Matrix Internal Client Interface Configuration Register 98" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x218C++0x03 line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2190++0x03 line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2194++0x03 line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2198++0x03 line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x219C++0x03 line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21A0++0x03 line.long 0x00 "DMA0_CMICIC104,DMA Controller Client Matrix Internal Client Interface Configuration Register 104" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21A4++0x03 line.long 0x00 "DMA0_CMICIC105,DMA Controller Client Matrix Internal Client Interface Configuration Register 105" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21A8++0x03 line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21AC++0x03 line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21B0++0x03 line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21B4++0x03 line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21B8++0x03 line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21BC++0x03 line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21C0++0x03 line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21C4++0x03 line.long 0x00 "DMA0_CMICIC113,DMA Controller Client Matrix Internal Client Interface Configuration Register 113" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21C8++0x03 line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21CC++0x03 line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21D0++0x03 line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21D4++0x03 line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21D8++0x03 line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21DC++0x03 line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21E0++0x03 line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21E4++0x03 line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21E8++0x03 line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21EC++0x03 line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21F0++0x03 line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21F4++0x03 line.long 0x00 "DMA0_CMICIC125,DMA Controller Client Matrix Internal Client Interface Configuration Register 125" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21F8++0x03 line.long 0x00 "DMA0_CMICIC126,DMA Controller Client Matrix Internal Client Interface Configuration Register 126" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x21FC++0x03 line.long 0x00 "DMA0_CMICIC127,DMA Controller Client Matrix Internal Client Interface Configuration Register 127" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2200++0x03 line.long 0x00 "DMA0_CMICIC128,DMA Controller Client Matrix Internal Client Interface Configuration Register 128" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2204++0x03 line.long 0x00 "DMA0_CMICIC129,DMA Controller Client Matrix Internal Client Interface Configuration Register 129" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2208++0x03 line.long 0x00 "DMA0_CMICIC130,DMA Controller Client Matrix Internal Client Interface Configuration Register 130" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x220C++0x03 line.long 0x00 "DMA0_CMICIC131,DMA Controller Client Matrix Internal Client Interface Configuration Register 131" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2210++0x03 line.long 0x00 "DMA0_CMICIC132,DMA Controller Client Matrix Internal Client Interface Configuration Register 132" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2214++0x03 line.long 0x00 "DMA0_CMICIC133,DMA Controller Client Matrix Internal Client Interface Configuration Register 133" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2218++0x03 line.long 0x00 "DMA0_CMICIC134,DMA Controller Client Matrix Internal Client Interface Configuration Register 134" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x221C++0x03 line.long 0x00 "DMA0_CMICIC135,DMA Controller Client Matrix Internal Client Interface Configuration Register 135" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2220++0x03 line.long 0x00 "DMA0_CMICIC136,DMA Controller Client Matrix Internal Client Interface Configuration Register 136" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2224++0x03 line.long 0x00 "DMA0_CMICIC137,DMA Controller Client Matrix Internal Client Interface Configuration Register 137" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2228++0x03 line.long 0x00 "DMA0_CMICIC138,DMA Controller Client Matrix Internal Client Interface Configuration Register 138" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x222C++0x03 line.long 0x00 "DMA0_CMICIC139,DMA Controller Client Matrix Internal Client Interface Configuration Register 139" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2230++0x03 line.long 0x00 "DMA0_CMICIC140,DMA Controller Client Matrix Internal Client Interface Configuration Register 140" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2234++0x03 line.long 0x00 "DMA0_CMICIC141,DMA Controller Client Matrix Internal Client Interface Configuration Register 141" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" group.long 0x2238++0x03 line.long 0x00 "DMA0_CMICIC142,DMA Controller Client Matrix Internal Client Interface Configuration Register 142" rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled" endif tree.end tree "CMCHIC 0-15" group.long 0x2800++0x03 line.long 0x00 "DMA0_CMCHIC0,DMA Controller Client Matrix Channel Interface Configuration Register 0" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2804++0x03 line.long 0x00 "DMA0_CMCHIC1,DMA Controller Client Matrix Channel Interface Configuration Register 1" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2808++0x03 line.long 0x00 "DMA0_CMCHIC2,DMA Controller Client Matrix Channel Interface Configuration Register 2" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x280C++0x03 line.long 0x00 "DMA0_CMCHIC3,DMA Controller Client Matrix Channel Interface Configuration Register 3" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2810++0x03 line.long 0x00 "DMA0_CMCHIC4,DMA Controller Client Matrix Channel Interface Configuration Register 4" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2814++0x03 line.long 0x00 "DMA0_CMCHIC5,DMA Controller Client Matrix Channel Interface Configuration Register 5" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2818++0x03 line.long 0x00 "DMA0_CMCHIC6,DMA Controller Client Matrix Channel Interface Configuration Register 6" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x281C++0x03 line.long 0x00 "DMA0_CMCHIC7,DMA Controller Client Matrix Channel Interface Configuration Register 7" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2820++0x03 line.long 0x00 "DMA0_CMCHIC8,DMA Controller Client Matrix Channel Interface Configuration Register 8" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2824++0x03 line.long 0x00 "DMA0_CMCHIC9,DMA Controller Client Matrix Channel Interface Configuration Register 9" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2828++0x03 line.long 0x00 "DMA0_CMCHIC10,DMA Controller Client Matrix Channel Interface Configuration Register 10" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x282C++0x03 line.long 0x00 "DMA0_CMCHIC11,DMA Controller Client Matrix Channel Interface Configuration Register 11" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2830++0x03 line.long 0x00 "DMA0_CMCHIC12,DMA Controller Client Matrix Channel Interface Configuration Register 12" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2834++0x03 line.long 0x00 "DMA0_CMCHIC13,DMA Controller Client Matrix Channel Interface Configuration Register 13" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x2838++0x03 line.long 0x00 "DMA0_CMCHIC14,DMA Controller Client Matrix Channel Interface Configuration Register 14" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif group.long 0x283C++0x03 line.long 0x00 "DMA0_CMCHIC15,DMA Controller Client Matrix Channel Interface Configuration Register 15" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected" bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" newline sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface" newline else hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" endif tree.end width 0x0B endif tree.end tree "DMA COMPLEX SUBSYSTEM" base ad:0xB4714000 width 12. rgroup.long 0x000++0x07 line.long 0x00 "ASR0,DMA Additional Control Additional Status Register 0" bitfld.long 0x00 0. " HBUSREQ ,HBUSREQ status" "Completed,Started" line.long 0x04 "ASR1,DMA Additional Control Additional Status Register 1" bitfld.long 0x04 16.--21. " BC_READ ,Block count for reading" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " BC_WRITE ,Block count for writing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x008++0x07 line.long 0x00 "ASR2,DMA Additional Control Additional Status Register 2" bitfld.long 0x00 15. " SELECTED_[15] ,Current selected channel by DMA arbiter 15" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Current selected channel by DMA arbiter 14" "Not selected,Selected" bitfld.long 0x00 13. " [13] ,Current selected channel by DMA arbiter 13" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Current selected channel by DMA arbiter 12" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Current selected channel by DMA arbiter 11" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Current selected channel by DMA arbiter 10" "Not selected,Selected" bitfld.long 0x00 9. " [9] ,Current selected channel by DMA arbiter 9" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Current selected channel by DMA arbiter 8" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Current selected channel by DMA arbiter 7" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Current selected channel by DMA arbiter 6" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,Current selected channel by DMA arbiter 5" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Current selected channel by DMA arbiter 4" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Current selected channel by DMA arbiter 3" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Current selected channel by DMA arbiter 2" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,Current selected channel by DMA arbiter 1" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Current selected channel by DMA arbiter 0" "Not selected,Selected" line.long 0x04 "ASR3,DMA Additional Control Additional Status Register 3" bitfld.long 0x04 15. " REQ_[15] ,Request bit 15" "Not requested,Requested" bitfld.long 0x04 14. " [14] ,Request bit 14" "Not requested,Requested" bitfld.long 0x04 13. " [13] ,Request bit 13" "Not requested,Requested" bitfld.long 0x04 12. " [12] ,Request bit 12" "Not requested,Requested" newline bitfld.long 0x04 11. " [11] ,Request bit 11" "Not requested,Requested" bitfld.long 0x04 10. " [10] ,Request bit 10" "Not requested,Requested" bitfld.long 0x04 9. " [9] ,Request bit 9" "Not requested,Requested" bitfld.long 0x04 8. " [8] ,Request bit 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Request bit 7" "Not requested,Requested" bitfld.long 0x04 6. " [6] ,Request bit 6" "Not requested,Requested" bitfld.long 0x04 5. " [5] ,Request bit 5" "Not requested,Requested" bitfld.long 0x04 4. " [4] ,Request bit 4" "Not requested,Requested" newline bitfld.long 0x04 3. " [3] ,Request bit 3" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Request bit 2" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Request bit 1" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Request bit 0" "Not requested,Requested" rgroup.long 0x10++0x03 line.long 0x00 "ASR4,DMA Additional Control Additional Status Register 4" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 0" rgroup.long 0x14++0x03 line.long 0x00 "ASR5,DMA Additional Control Additional Status Register 5" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 1" rgroup.long 0x18++0x03 line.long 0x00 "ASR6,DMA Additional Control Additional Status Register 6" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 2" rgroup.long 0x1C++0x03 line.long 0x00 "ASR7,DMA Additional Control Additional Status Register 7" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 3" rgroup.long 0x20++0x03 line.long 0x00 "ASR8,DMA Additional Control Additional Status Register 8" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 4" rgroup.long 0x24++0x03 line.long 0x00 "ASR9,DMA Additional Control Additional Status Register 9" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 5" rgroup.long 0x28++0x03 line.long 0x00 "ASR10,DMA Additional Control Additional Status Register 10" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 6" rgroup.long 0x2C++0x03 line.long 0x00 "ASR11,DMA Additional Control Additional Status Register 11" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 7" rgroup.long 0x30++0x03 line.long 0x00 "ASR12,DMA Additional Control Additional Status Register 12" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 8" rgroup.long 0x34++0x03 line.long 0x00 "ASR13,DMA Additional Control Additional Status Register 13" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 9" rgroup.long 0x38++0x03 line.long 0x00 "ASR14,DMA Additional Control Additional Status Register 14" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 10" rgroup.long 0x3C++0x03 line.long 0x00 "ASR15,DMA Additional Control Additional Status Register 15" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 11" rgroup.long 0x40++0x03 line.long 0x00 "ASR16,DMA Additional Control Additional Status Register 16" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 12" rgroup.long 0x44++0x03 line.long 0x00 "ASR17,DMA Additional Control Additional Status Register 17" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 13" rgroup.long 0x48++0x03 line.long 0x00 "ASR18,DMA Additional Control Additional Status Register 18" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 14" rgroup.long 0x4C++0x03 line.long 0x00 "ASR19,DMA Additional Control Additional Status Register 19" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 15" newline group.long 0x80++0x03 line.long 0x00 "CMCHICRDB0,DMA Additional Control CMCHIC Reload Data Bank Register 0" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x84++0x03 line.long 0x00 "CMCHICRDB1,DMA Additional Control CMCHIC Reload Data Bank Register 1" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x88++0x03 line.long 0x00 "CMCHICRDB2,DMA Additional Control CMCHIC Reload Data Bank Register 2" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x8C++0x03 line.long 0x00 "CMCHICRDB3,DMA Additional Control CMCHIC Reload Data Bank Register 3" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x90++0x03 line.long 0x00 "CMCHICRDB4,DMA Additional Control CMCHIC Reload Data Bank Register 4" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x94++0x03 line.long 0x00 "CMCHICRDB5,DMA Additional Control CMCHIC Reload Data Bank Register 5" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x98++0x03 line.long 0x00 "CMCHICRDB6,DMA Additional Control CMCHIC Reload Data Bank Register 6" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif group.long 0x9C++0x03 line.long 0x00 "CMCHICRDB7,DMA Additional Control CMCHIC Reload Data Bank Register 7" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA") hexmask.long.byte 0x00 0.--7. 1. " CI ,CI" else hexmask.long.word 0x00 0.--8. 1. " CI ,CI" endif newline group.long 0x100++0x03 line.long 0x00 "RTTSR,DMA Additional Control Reload Timer Trigger Select Register" hexmask.long.byte 0x00 24.--30. 1. " RLT3TS ,Reload timer 3 trigger select" hexmask.long.byte 0x00 16.--22. 1. " RLT2TS ,Reload timer 2 trigger select" hexmask.long.byte 0x00 8.--14. 1. " RLT1TS ,Reload timer 1 trigger select" hexmask.long.byte 0x00 0.--6. 1. " RLT0TS ,Reload timer 0 trigger select" group.long 0x120++0x03 line.long 0x00 "RTSSSR,DMA Additional Control Reload Timer Synchronous Software Start Register" bitfld.long 0x00 3. " SSSR3 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" bitfld.long 0x00 2. " SSSR2 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" bitfld.long 0x00 1. " SSSR1 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" bitfld.long 0x00 0. " SSSR0 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" width 0x0B tree "RLT0" base ad:0xB4714800 width 15. group.long 0x00++0x03 line.long 0x00 "RLT0_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4714800+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4714800+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT0_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT0_TMR,32-Bit Timer Register" width 0x0B tree.end tree "RLT1" base ad:0xB4714820 width 15. group.long 0x00++0x03 line.long 0x00 "RLT1_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4714820+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4714820+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT1_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT1_TMR,32-Bit Timer Register" width 0x0B tree.end tree "RLT2" base ad:0xB4714840 width 15. group.long 0x00++0x03 line.long 0x00 "RLT2_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4714840+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4714840+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT2_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT2_TMR,32-Bit Timer Register" width 0x0B tree.end tree "RLT3" base ad:0xB4714860 width 15. group.long 0x00++0x03 line.long 0x00 "RLT3_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4714860+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4714860+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT3_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT3_TMR,32-Bit Timer Register" width 0x0B tree.end tree.end tree "MPUH (Memory Protection Unit for the AMBA Advanced High Speed Bus)" base ad:0xB4710000 width 15. if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x10000) group.long 0x000++0x03 line.long 0x00 "MPUH0_CTRL0,MPU16 AHB Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged mode,Privileged mode" rbitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" newline bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not occurred,Occurred" else group.long 0x000++0x03 line.long 0x00 "MPUH0_CTRL0,MPU16 AHB Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged mode,Privileged mode" bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" newline bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not occurred,Occurred" endif group.long 0x004++0x03 line.long 0x00 "MPUH0_NMIEN,MPU16 AHB NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" rgroup.long 0x008++0x07 line.long 0x00 "MPUH0_MERRC,MPU16 AHB Memory Error Control Register" bitfld.long 0x00 1. " HPROT ,AHB transfer privileged mode" "Not detected,Detected" bitfld.long 0x00 0. " HWRITE ,AHB transfer mode" "Not detected,Detected" line.long 0x04 "MPUH0_MERRA,MPU AHB Memory Error Address Register" newline sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x10))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "MPUH0_CTRL1,MPU16 AHB Region Control Register 1" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "MPUH0_CTRL1,MPU16 AHB Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x1C))&0x01)==0x01) group.long 0x1C++0x03 line.long 0x00 "MPUH0_CTRL2,MPU16 AHB Region Control Register 2" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "MPUH0_CTRL2,MPU16 AHB Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x28))&0x01)==0x01) group.long 0x28++0x03 line.long 0x00 "MPUH0_CTRL3,MPU16 AHB Region Control Register 3" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x28++0x03 line.long 0x00 "MPUH0_CTRL3,MPU16 AHB Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x34))&0x01)==0x01) group.long 0x34++0x03 line.long 0x00 "MPUH0_CTRL4,MPU16 AHB Region Control Register 4" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "MPUH0_CTRL4,MPU16 AHB Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x40))&0x01)==0x01) group.long 0x40++0x03 line.long 0x00 "MPUH0_CTRL5,MPU16 AHB Region Control Register 5" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x40++0x03 line.long 0x00 "MPUH0_CTRL5,MPU16 AHB Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x4C))&0x01)==0x01) group.long 0x4C++0x03 line.long 0x00 "MPUH0_CTRL6,MPU16 AHB Region Control Register 6" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x4C++0x03 line.long 0x00 "MPUH0_CTRL6,MPU16 AHB Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x58))&0x01)==0x01) group.long 0x58++0x03 line.long 0x00 "MPUH0_CTRL7,MPU16 AHB Region Control Register 7" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x58++0x03 line.long 0x00 "MPUH0_CTRL7,MPU16 AHB Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x64))&0x01)==0x01) group.long 0x64++0x03 line.long 0x00 "MPUH0_CTRL8,MPU16 AHB Region Control Register 8" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x64++0x03 line.long 0x00 "MPUH0_CTRL8,MPU16 AHB Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x110))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "MPUH0_CTRL9,MPU16 AHB Region Control Register 9" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x110++0x03 line.long 0x00 "MPUH0_CTRL9,MPU16 AHB Region Control Register 9" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x11C))&0x01)==0x01) group.long 0x11C++0x03 line.long 0x00 "MPUH0_CTRL10,MPU16 AHB Region Control Register 10" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x11C++0x03 line.long 0x00 "MPUH0_CTRL10,MPU16 AHB Region Control Register 10" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x128))&0x01)==0x01) group.long 0x128++0x03 line.long 0x00 "MPUH0_CTRL11,MPU16 AHB Region Control Register 11" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x128++0x03 line.long 0x00 "MPUH0_CTRL11,MPU16 AHB Region Control Register 11" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x134))&0x01)==0x01) group.long 0x134++0x03 line.long 0x00 "MPUH0_CTRL12,MPU16 AHB Region Control Register 12" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x134++0x03 line.long 0x00 "MPUH0_CTRL12,MPU16 AHB Region Control Register 12" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x140))&0x01)==0x01) group.long 0x140++0x03 line.long 0x00 "MPUH0_CTRL13,MPU16 AHB Region Control Register 13" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "MPUH0_CTRL13,MPU16 AHB Region Control Register 13" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x14C))&0x01)==0x01) group.long 0x14C++0x03 line.long 0x00 "MPUH0_CTRL14,MPU16 AHB Region Control Register 14" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x14C++0x03 line.long 0x00 "MPUH0_CTRL14,MPU16 AHB Region Control Register 14" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x158))&0x01)==0x01) group.long 0x158++0x03 line.long 0x00 "MPUH0_CTRL15,MPU16 AHB Region Control Register 15" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x158++0x03 line.long 0x00 "MPUH0_CTRL15,MPU16 AHB Region Control Register 15" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x164))&0x01)==0x01) group.long 0x164++0x03 line.long 0x00 "MPUH0_CTRL16,MPU16 AHB Region Control Register 16" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x164++0x03 line.long 0x00 "MPUH0_CTRL16,MPU16 AHB Region Control Register 16" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif elif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") group.byte 0x10++0x01 line.byte 0x00 "MPUH0_CTRL1_0,MPU16 AHB Region Control Register 1" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL1_1,MPU16 AHB Region Control Register 1" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x1C++0x01 line.byte 0x00 "MPUH0_CTRL2_0,MPU16 AHB Region Control Register 2" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL2_1,MPU16 AHB Region Control Register 2" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x28++0x01 line.byte 0x00 "MPUH0_CTRL3_0,MPU16 AHB Region Control Register 3" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL3_1,MPU16 AHB Region Control Register 3" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x34++0x01 line.byte 0x00 "MPUH0_CTRL4_0,MPU16 AHB Region Control Register 4" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL4_1,MPU16 AHB Region Control Register 4" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x40++0x01 line.byte 0x00 "MPUH0_CTRL5_0,MPU16 AHB Region Control Register 5" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL5_1,MPU16 AHB Region Control Register 5" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x4C++0x01 line.byte 0x00 "MPUH0_CTRL6_0,MPU16 AHB Region Control Register 6" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL6_1,MPU16 AHB Region Control Register 6" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x58++0x01 line.byte 0x00 "MPUH0_CTRL7_0,MPU16 AHB Region Control Register 7" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL7_1,MPU16 AHB Region Control Register 7" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x64++0x01 line.byte 0x00 "MPUH0_CTRL8_0,MPU16 AHB Region Control Register 8" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL8_1,MPU16 AHB Region Control Register 8" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x110++0x01 line.byte 0x00 "MPUH0_CTRL9_0,MPU16 AHB Region Control Register 9" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL9_1,MPU16 AHB Region Control Register 9" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x11C++0x01 line.byte 0x00 "MPUH0_CTRL10_0,MPU16 AHB Region Control Register 10" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL10_1,MPU16 AHB Region Control Register 10" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x128++0x01 line.byte 0x00 "MPUH0_CTRL11_0,MPU16 AHB Region Control Register 11" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL11_1,MPU16 AHB Region Control Register 11" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x134++0x01 line.byte 0x00 "MPUH0_CTRL12_0,MPU16 AHB Region Control Register 12" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL12_1,MPU16 AHB Region Control Register 12" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x140++0x01 line.byte 0x00 "MPUH0_CTRL13_0,MPU16 AHB Region Control Register 13" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL13_1,MPU16 AHB Region Control Register 13" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x14C++0x01 line.byte 0x00 "MPUH0_CTRL14_0,MPU16 AHB Region Control Register 14" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL14_1,MPU16 AHB Region Control Register 14" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x158++0x01 line.byte 0x00 "MPUH0_CTRL15_0,MPU16 AHB Region Control Register 15" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL15_1,MPU16 AHB Region Control Register 15" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x164++0x01 line.byte 0x00 "MPUH0_CTRL16_0,MPU16 AHB Region Control Register 16" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL16_1,MPU16 AHB Region Control Register 16" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" else group.byte 0x10++0x01 line.byte 0x00 "MPUH0_CTRL1_1,MPU16 AHB Region Control Register 1" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL1_2,MPU16 AHB Region Control Register 1" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x1C++0x01 line.byte 0x00 "MPUH0_CTRL2_1,MPU16 AHB Region Control Register 2" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL2_2,MPU16 AHB Region Control Register 2" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x28++0x01 line.byte 0x00 "MPUH0_CTRL3_1,MPU16 AHB Region Control Register 3" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL3_2,MPU16 AHB Region Control Register 3" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x34++0x01 line.byte 0x00 "MPUH0_CTRL4_1,MPU16 AHB Region Control Register 4" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL4_2,MPU16 AHB Region Control Register 4" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x40++0x01 line.byte 0x00 "MPUH0_CTRL5_1,MPU16 AHB Region Control Register 5" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL5_2,MPU16 AHB Region Control Register 5" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x4C++0x01 line.byte 0x00 "MPUH0_CTRL6_1,MPU16 AHB Region Control Register 6" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL6_2,MPU16 AHB Region Control Register 6" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x58++0x01 line.byte 0x00 "MPUH0_CTRL7_1,MPU16 AHB Region Control Register 7" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL7_2,MPU16 AHB Region Control Register 7" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x64++0x01 line.byte 0x00 "MPUH0_CTRL8_1,MPU16 AHB Region Control Register 8" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL8_2,MPU16 AHB Region Control Register 8" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x110++0x01 line.byte 0x00 "MPUH0_CTRL9_1,MPU16 AHB Region Control Register 9" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL9_2,MPU16 AHB Region Control Register 9" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x11C++0x01 line.byte 0x00 "MPUH0_CTRL10_1,MPU16 AHB Region Control Register 10" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL10_2,MPU16 AHB Region Control Register 10" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x128++0x01 line.byte 0x00 "MPUH0_CTRL11_1,MPU16 AHB Region Control Register 11" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL11_2,MPU16 AHB Region Control Register 11" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x134++0x01 line.byte 0x00 "MPUH0_CTRL12_1,MPU16 AHB Region Control Register 12" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL12_2,MPU16 AHB Region Control Register 12" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x140++0x01 line.byte 0x00 "MPUH0_CTRL13_1,MPU16 AHB Region Control Register 13" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL13_2,MPU16 AHB Region Control Register 13" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x14C++0x01 line.byte 0x00 "MPUH0_CTRL14_1,MPU16 AHB Region Control Register 14" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL14_2,MPU16 AHB Region Control Register 14" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x158++0x01 line.byte 0x00 "MPUH0_CTRL15_1,MPU16 AHB Region Control Register 15" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL15_2,MPU16 AHB Region Control Register 15" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" group.byte 0x164++0x01 line.byte 0x00 "MPUH0_CTRL16_1,MPU16 AHB Region Control Register 16" bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.byte 0x01 "MPUH0_CTRL16_2,MPU16 AHB Region Control Register 16" bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7" endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x14-0x04))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1" else rgroup.long 0x14++0x03 line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x14-0x04))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1" else rgroup.long 0x14++0x03 line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x20-0x04))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2" else rgroup.long 0x20++0x03 line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x20-0x04))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2" else rgroup.long 0x20++0x03 line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x2C-0x04))&0x01)==0x00) group.long 0x2C++0x03 line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3" else rgroup.long 0x2C++0x03 line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x2C-0x04))&0x01)==0x00) group.long 0x2C++0x03 line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3" else rgroup.long 0x2C++0x03 line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x38-0x04))&0x01)==0x00) group.long 0x38++0x03 line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4" else rgroup.long 0x38++0x03 line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x38-0x04))&0x01)==0x00) group.long 0x38++0x03 line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4" else rgroup.long 0x38++0x03 line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x44-0x04))&0x01)==0x00) group.long 0x44++0x03 line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5" else rgroup.long 0x44++0x03 line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x44-0x04))&0x01)==0x00) group.long 0x44++0x03 line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5" else rgroup.long 0x44++0x03 line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x50-0x04))&0x01)==0x00) group.long 0x50++0x03 line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6" else rgroup.long 0x50++0x03 line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x50-0x04))&0x01)==0x00) group.long 0x50++0x03 line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6" else rgroup.long 0x50++0x03 line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x5C-0x04))&0x01)==0x00) group.long 0x5C++0x03 line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7" else rgroup.long 0x5C++0x03 line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x5C-0x04))&0x01)==0x00) group.long 0x5C++0x03 line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7" else rgroup.long 0x5C++0x03 line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x68-0x04))&0x01)==0x00) group.long 0x68++0x03 line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8" else rgroup.long 0x68++0x03 line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x68-0x04))&0x01)==0x00) group.long 0x68++0x03 line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8" else rgroup.long 0x68++0x03 line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x114-0x04))&0x01)==0x00) group.long 0x114++0x03 line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9" else rgroup.long 0x114++0x03 line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x114-0x04))&0x01)==0x00) group.long 0x114++0x03 line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9" else rgroup.long 0x114++0x03 line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x120-0x04))&0x01)==0x00) group.long 0x120++0x03 line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10" else rgroup.long 0x120++0x03 line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x120-0x04))&0x01)==0x00) group.long 0x120++0x03 line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10" else rgroup.long 0x120++0x03 line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x12C-0x04))&0x01)==0x00) group.long 0x12C++0x03 line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11" else rgroup.long 0x12C++0x03 line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x12C-0x04))&0x01)==0x00) group.long 0x12C++0x03 line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11" else rgroup.long 0x12C++0x03 line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x138-0x04))&0x01)==0x00) group.long 0x138++0x03 line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12" else rgroup.long 0x138++0x03 line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x138-0x04))&0x01)==0x00) group.long 0x138++0x03 line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12" else rgroup.long 0x138++0x03 line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x144-0x04))&0x01)==0x00) group.long 0x144++0x03 line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13" else rgroup.long 0x144++0x03 line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x144-0x04))&0x01)==0x00) group.long 0x144++0x03 line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13" else rgroup.long 0x144++0x03 line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x150-0x04))&0x01)==0x00) group.long 0x150++0x03 line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14" else rgroup.long 0x150++0x03 line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x150-0x04))&0x01)==0x00) group.long 0x150++0x03 line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14" else rgroup.long 0x150++0x03 line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x15C-0x04))&0x01)==0x00) group.long 0x15C++0x03 line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15" else rgroup.long 0x15C++0x03 line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x15C-0x04))&0x01)==0x00) group.long 0x15C++0x03 line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15" else rgroup.long 0x15C++0x03 line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x168-0x04))&0x01)==0x00) group.long 0x168++0x03 line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16" else rgroup.long 0x168++0x03 line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x168-0x04))&0x01)==0x00) group.long 0x168++0x03 line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16" else rgroup.long 0x168++0x03 line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x18-0x08))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1" else rgroup.long 0x18++0x03 line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x18-0x08))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1" else rgroup.long 0x18++0x03 line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x24-0x08))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2" else rgroup.long 0x24++0x03 line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x24-0x08))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2" else rgroup.long 0x24++0x03 line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x30-0x08))&0x01)==0x00) group.long 0x30++0x03 line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3" else rgroup.long 0x30++0x03 line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x30-0x08))&0x01)==0x00) group.long 0x30++0x03 line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3" else rgroup.long 0x30++0x03 line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x3C-0x08))&0x01)==0x00) group.long 0x3C++0x03 line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4" else rgroup.long 0x3C++0x03 line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x3C-0x08))&0x01)==0x00) group.long 0x3C++0x03 line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4" else rgroup.long 0x3C++0x03 line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x48-0x08))&0x01)==0x00) group.long 0x48++0x03 line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5" else rgroup.long 0x48++0x03 line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x48-0x08))&0x01)==0x00) group.long 0x48++0x03 line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5" else rgroup.long 0x48++0x03 line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x54-0x08))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6" else rgroup.long 0x54++0x03 line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x54-0x08))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6" else rgroup.long 0x54++0x03 line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x60-0x08))&0x01)==0x00) group.long 0x60++0x03 line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7" else rgroup.long 0x60++0x03 line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x60-0x08))&0x01)==0x00) group.long 0x60++0x03 line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7" else rgroup.long 0x60++0x03 line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x6C-0x08))&0x01)==0x00) group.long 0x6C++0x03 line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8" else rgroup.long 0x6C++0x03 line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x6C-0x08))&0x01)==0x00) group.long 0x6C++0x03 line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8" else rgroup.long 0x6C++0x03 line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x118-0x08))&0x01)==0x00) group.long 0x118++0x03 line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9" else rgroup.long 0x118++0x03 line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x118-0x08))&0x01)==0x00) group.long 0x118++0x03 line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9" else rgroup.long 0x118++0x03 line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x124-0x08))&0x01)==0x00) group.long 0x124++0x03 line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10" else rgroup.long 0x124++0x03 line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x124-0x08))&0x01)==0x00) group.long 0x124++0x03 line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10" else rgroup.long 0x124++0x03 line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x130-0x08))&0x01)==0x00) group.long 0x130++0x03 line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11" else rgroup.long 0x130++0x03 line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x130-0x08))&0x01)==0x00) group.long 0x130++0x03 line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11" else rgroup.long 0x130++0x03 line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x13C-0x08))&0x01)==0x00) group.long 0x13C++0x03 line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12" else rgroup.long 0x13C++0x03 line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x13C-0x08))&0x01)==0x00) group.long 0x13C++0x03 line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12" else rgroup.long 0x13C++0x03 line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x148-0x08))&0x01)==0x00) group.long 0x148++0x03 line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13" else rgroup.long 0x148++0x03 line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x148-0x08))&0x01)==0x00) group.long 0x148++0x03 line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13" else rgroup.long 0x148++0x03 line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x154-0x08))&0x01)==0x00) group.long 0x154++0x03 line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14" else rgroup.long 0x154++0x03 line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x154-0x08))&0x01)==0x00) group.long 0x154++0x03 line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14" else rgroup.long 0x154++0x03 line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x160-0x08))&0x01)==0x00) group.long 0x160++0x03 line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15" else rgroup.long 0x160++0x03 line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x160-0x08))&0x01)==0x00) group.long 0x160++0x03 line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15" else rgroup.long 0x160++0x03 line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15" endif endif sif (cpuis("S6J33*")) if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x16C-0x08))&0x01)==0x00) group.long 0x16C++0x03 line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16" else rgroup.long 0x16C++0x03 line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16" endif else if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x16C-0x08))&0x01)==0x00) group.long 0x16C++0x03 line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16" else rgroup.long 0x16C++0x03 line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16" endif endif group.long 0x070++0x03 line.long 0x00 "MPUH0_UNLOCK,MPU16 AHB Unlock Register" rgroup.long 0x074++0x03 line.long 0x00 "MPUH0_MID,MPU16 AHB Module ID Register" width 0x0B tree.end tree.open "CAN-FD" tree "Channel 0" base ad:0xB4900000 width 8. if (((per.l(ad:0xB4900000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4900000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4900000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4900000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4900000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4900000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4900000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4900000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4900000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4900000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 1" base ad:0xB4910000 width 8. if (((per.l(ad:0xB4910000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4910000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4910000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4910000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4910000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4910000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4910000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4910000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4910000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4910000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 2" base ad:0xB4920000 width 8. if (((per.l(ad:0xB4920000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4920000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4920000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4920000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4920000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4920000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4920000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4920000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4920000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4920000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 3" base ad:0xB4930000 width 8. if (((per.l(ad:0xB4930000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4930000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4930000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4930000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4930000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4930000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4930000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4930000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4930000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4930000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 4" base ad:0xB4940000 width 8. if (((per.l(ad:0xB4940000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4940000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4940000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4940000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4940000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4940000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4940000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4940000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4940000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4940000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end endif sif (cpuis("S6J335*")) tree "Channel 5" base ad:0xB06C0000 width 8. if (((per.l(ad:0xB06C0000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB06C0000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB06C0000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB06C0000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB06C0000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB06C0000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB06C0000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB06C0000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB06C0000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB06C0000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB06C0000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end endif sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 6" base ad:0xB06D0000 width 8. if (((per.l(ad:0xB06D0000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB06D0000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB06D0000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB06D0000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB06D0000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB06D0000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB06D0000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB06D0000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB06D0000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB06D0000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB06D0000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end endif sif (cpuis("S6J335*")) tree "Channel 7" base ad:0xB06E0000 width 8. if (((per.l(ad:0xB06E0000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB06E0000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB06E0000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB06E0000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB06E0000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB06E0000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB06E0000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB06E0000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB06E0000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB06E0000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB06E0000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end endif tree.end tree.open "TS (EXTERNAL TIMESTAMP COUNTER FOR CAN FD)" sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "MCU Config Group" sif (cpuis("S6J335*")) tree "Channel 0" base ad:0xB06C0000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS0_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS0_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB06C0000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS0_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS0_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB06C0000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS0_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS0_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS0_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB06C0000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS0_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS0_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end endif tree "Channel 1" base ad:0xB06D0000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS1_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS1_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB06D0000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS1_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS1_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB06D0000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS1_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS1_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS1_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB06D0000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS1_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS1_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end sif (cpuis("S6J335*")) tree "Channel 2" base ad:0xB06E0000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS2_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS2_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB06E0000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS2_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS2_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB06E0000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS2_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS2_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS2_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB06E0000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS2_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS2_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end endif tree.end endif tree "Common Peripheral #0 Group" tree "Channel 0" base ad:0xB4900000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS0_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS0_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4900000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS0_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS0_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4900000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS0_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS0_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS0_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4900000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS0_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS0_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 1" base ad:0xB4910000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS1_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS1_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4910000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS1_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS1_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4910000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS1_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS1_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS1_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4910000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS1_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS1_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 2" base ad:0xB4920000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS2_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS2_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4920000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS2_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS2_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4920000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS2_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS2_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS2_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4920000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS2_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS2_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 3" base ad:0xB4930000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS3_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS3_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4930000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS3_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS3_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4930000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS3_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS3_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS3_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4930000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS3_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS3_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 4" base ad:0xB4940000 width 13. wgroup.word 0x300++0x01 line.word 0x00 "TS4_TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TS4_TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4940000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TS4_TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TS4_TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4940000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TS4_TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TS4_TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TS4_TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4940000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TS4_TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TS4_TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end endif tree.end tree.end tree "CANP (CAN PRESCALER)" base ad:0xB0688C00 width 10. group.long 0x00++0x03 line.long 0x00 "CANP_CTR,CAN Prescaler Control Register" bitfld.long 0x00 8. " CPCKS ,CAN prescaler source clock selection bit" "PLL clock,Main clock" bitfld.long 0x00 0.--5. " CANPRE ,CAN prescaler division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" sif (!cpuis("S6J311?JAA"))&&(!cpuis("S6J311?HAA"))&&(!cpuis("S6J312?HAA")) rgroup.long 0x04++0x03 line.long 0x00 "CANP_STR,CAN Prescaler Status Register" bitfld.long 0x00 1.--2. " SCKM ,Source clock display" "Stopped,PLL clock,Main clock,In the middle" bitfld.long 0x00 0. " BUSY ,Busy" "Idle,Busy" else rgroup.long 0x04++0x03 line.long 0x00 "CANP_STR,CAN Prescaler Status Register" bitfld.long 0x00 1.--2. " SCKM ,Source clock display" "On-chip,PLL clock,Main clock,On-chip" bitfld.long 0x00 0. " BUSY ,Busy" "Idle,Busy" endif width 0x0B tree.end tree.open "MFS (MULTI-FUNCTION SERIAL INTERFACE)" tree "Channel 0" base ad:0xB4800000 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4800000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS0_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS0_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS0_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS0_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS0_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS0_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS0_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS0_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS0_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS0_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS0_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS0_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS0_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS0_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS0_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS0_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800000+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS0_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS0_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS0_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS0_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS0_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS0_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS0_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS0_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS0_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS0_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS0_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS0_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS0_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS0_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS0_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS0_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS0_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS0_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS0_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS0_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS0_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS0_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS0_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS0_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS0_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS0_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS0_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS0_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS0_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS0_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS0_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS0_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS0_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS0_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS0_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS0_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS0_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS0_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS0_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS0_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS0_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS0_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS0_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS0_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS0_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS0_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS0_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS0_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS0_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS0_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS0_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS0_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS0_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS0_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS0_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS0_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS0_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4800000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS0_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4800000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS0_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS0_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS0_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS0_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS0_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS0_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS0_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS0_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS0_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS0_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS0_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS0_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS0_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS0_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS0_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS0_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4800000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800000+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS0_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS0_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS0_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4800000+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS0_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS0_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800000+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS0_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS0_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS0_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS0_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS0_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS0_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS0_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS0_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4800000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4800000+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS0_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS0_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS0_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) if (((per.w(ad:0xB4800000+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS0_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4800000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800000+0x08))&0x20)==0x20) if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4800000+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS0_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS0_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4800000+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS0_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS0_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS0_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS0_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS0_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4800000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4800000+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS0_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS0_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS0_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS0_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS0_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS0_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS0_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4800000+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS0_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS0_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800000+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4800000+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4800000+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS0_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS0_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS0_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS0_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS0_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS0_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS0_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS0_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS0_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS0_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS0_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS0_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS0_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS0_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS0_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS0_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS0_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS0_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS0_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS0_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS0_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS0_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS0_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS0_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS0_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS0_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS0_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS0_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4800000+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS0_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS0_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS0_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4800000+0x08))&0x20)==0x00) if (((per.l(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS0_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS0_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS0_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS0_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4800000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS0_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS0_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS0_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS0_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS0_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS0_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS0_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS0_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS0_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS0_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS0_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS0_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS0_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS0_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS0_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS0_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS0_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS0_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS0_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS0_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS0_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS0_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS0_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 1" base ad:0xB4800400 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4800400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS1_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS1_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS1_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS1_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS1_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS1_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS1_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS1_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS1_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS1_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS1_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS1_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS1_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS1_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS1_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS1_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800400+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS1_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS1_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS1_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS1_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS1_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS1_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS1_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS1_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS1_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS1_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS1_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS1_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS1_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS1_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS1_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS1_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS1_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS1_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS1_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS1_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS1_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS1_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS1_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS1_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS1_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS1_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS1_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS1_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS1_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS1_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS1_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS1_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS1_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS1_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS1_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS1_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS1_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS1_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS1_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS1_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS1_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS1_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS1_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS1_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS1_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS1_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS1_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS1_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS1_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS1_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS1_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS1_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS1_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS1_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS1_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS1_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS1_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4800400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS1_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4800400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS1_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS1_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS1_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS1_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS1_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS1_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS1_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS1_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS1_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS1_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS1_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS1_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS1_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS1_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS1_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS1_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4800400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800400+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS1_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS1_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS1_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4800400+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS1_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS1_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800400+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS1_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS1_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS1_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS1_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS1_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS1_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS1_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS1_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4800400+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4800400+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS1_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS1_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS1_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) if (((per.w(ad:0xB4800400+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS1_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4800400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800400+0x08))&0x20)==0x20) if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800400+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800400+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4800400+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS1_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS1_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4800400+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS1_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS1_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS1_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS1_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS1_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4800400+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4800400+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS1_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS1_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS1_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS1_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS1_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS1_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS1_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4800400+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS1_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS1_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800400+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4800400+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4800400+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS1_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS1_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS1_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS1_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS1_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS1_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS1_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS1_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS1_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS1_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS1_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS1_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS1_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS1_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS1_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS1_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS1_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS1_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS1_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS1_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS1_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS1_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS1_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS1_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS1_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS1_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS1_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS1_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4800400+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS1_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS1_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS1_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4800400+0x08))&0x20)==0x00) if (((per.l(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS1_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS1_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS1_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS1_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4800400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS1_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS1_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS1_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS1_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS1_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS1_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS1_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS1_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS1_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS1_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS1_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS1_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS1_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS1_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS1_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS1_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS1_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS1_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS1_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS1_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS1_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS1_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS1_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 2" base ad:0xB4800800 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4800800))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS2_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS2_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS2_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS2_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS2_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS2_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS2_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS2_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS2_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS2_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS2_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS2_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800800+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS2_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS2_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS2_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS2_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800800+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS2_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS2_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800800+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800800+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS2_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS2_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS2_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS2_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS2_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS2_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS2_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS2_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS2_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS2_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS2_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS2_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS2_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS2_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS2_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS2_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS2_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS2_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS2_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS2_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS2_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS2_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS2_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS2_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS2_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS2_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS2_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS2_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS2_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS2_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS2_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS2_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS2_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS2_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS2_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS2_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS2_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS2_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS2_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS2_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS2_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS2_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS2_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS2_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS2_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS2_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS2_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS2_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS2_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS2_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS2_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS2_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS2_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS2_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS2_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4800800))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS2_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4800800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS2_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS2_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS2_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS2_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS2_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS2_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS2_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS2_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS2_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS2_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS2_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS2_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS2_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS2_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS2_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS2_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4800800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800800+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS2_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS2_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS2_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4800800+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS2_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS2_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800800+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS2_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS2_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS2_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS2_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS2_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS2_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS2_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS2_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4800800+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4800800+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS2_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS2_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS2_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) if (((per.w(ad:0xB4800800+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS2_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4800800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800800+0x08))&0x20)==0x20) if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800800+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800800+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4800800+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS2_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS2_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4800800+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS2_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS2_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS2_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS2_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS2_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4800800+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4800800+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS2_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS2_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS2_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS2_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS2_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS2_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS2_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4800800+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS2_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS2_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800800+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4800800+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4800800+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS2_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS2_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS2_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS2_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS2_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS2_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS2_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS2_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS2_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS2_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS2_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS2_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS2_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS2_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS2_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS2_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS2_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS2_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS2_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS2_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS2_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS2_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS2_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS2_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS2_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS2_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS2_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS2_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4800800+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS2_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS2_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS2_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4800800+0x08))&0x20)==0x00) if (((per.l(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS2_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS2_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS2_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS2_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4800800+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS2_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS2_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS2_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS2_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS2_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS2_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS2_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS2_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS2_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS2_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS2_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS2_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS2_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS2_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS2_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS2_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS2_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS2_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS2_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS2_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS2_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS2_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS2_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 3" base ad:0xB4800C00 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4800C00))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS3_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS3_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS3_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS3_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS3_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS3_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS3_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS3_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS3_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS3_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS3_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS3_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800C00+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS3_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS3_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS3_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS3_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800C00+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS3_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS3_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800C00+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800C00+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS3_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS3_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS3_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS3_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS3_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS3_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS3_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS3_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS3_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS3_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS3_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS3_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS3_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS3_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS3_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS3_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS3_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS3_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS3_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS3_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS3_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS3_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS3_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS3_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS3_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS3_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS3_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS3_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS3_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS3_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS3_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS3_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS3_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS3_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS3_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS3_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS3_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS3_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS3_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS3_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS3_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS3_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS3_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS3_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS3_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS3_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS3_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS3_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS3_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS3_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS3_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS3_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS3_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS3_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS3_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4800C00))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS3_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4800C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS3_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS3_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS3_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS3_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS3_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS3_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS3_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS3_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS3_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS3_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS3_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS3_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS3_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS3_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS3_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS3_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4800C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800C00+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS3_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS3_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS3_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS3_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS3_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800C00+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS3_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS3_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS3_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS3_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS3_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS3_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS3_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS3_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4800C00+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS3_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS3_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS3_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) if (((per.w(ad:0xB4800C00+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS3_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4800C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800C00+0x08))&0x20)==0x20) if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800C00+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4800C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800C00+0x08))&0x20)==0x00) if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4800C00+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS3_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS3_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4800C00+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS3_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS3_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS3_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS3_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS3_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x00) if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS3_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS3_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS3_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS3_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS3_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS3_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS3_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4800C00+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS3_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS3_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4800C00+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS3_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS3_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS3_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS3_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS3_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS3_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS3_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS3_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS3_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS3_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS3_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS3_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS3_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS3_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS3_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS3_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS3_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS3_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS3_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS3_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS3_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS3_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS3_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS3_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS3_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS3_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS3_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS3_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4800C00+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS3_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS3_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS3_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4800C00+0x08))&0x20)==0x00) if (((per.l(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS3_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS3_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS3_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS3_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4800C00+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS3_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS3_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS3_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS3_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS3_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS3_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS3_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS3_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS3_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS3_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS3_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS3_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS3_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS3_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS3_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS3_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS3_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS3_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS3_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS3_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS3_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS3_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS3_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 4" base ad:0xB4801000 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4801000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS4_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS4_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS4_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS4_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS4_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS4_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS4_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS4_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS4_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS4_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801000+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS4_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS4_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS4_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS4_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS4_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS4_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS4_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS4_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS4_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS4_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS4_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS4_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS4_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS4_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS4_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS4_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS4_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS4_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS4_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS4_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS4_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS4_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS4_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS4_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS4_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS4_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS4_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS4_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS4_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS4_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS4_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS4_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS4_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS4_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS4_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS4_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS4_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS4_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS4_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS4_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS4_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS4_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS4_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4801000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS4_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4801000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS4_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS4_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS4_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS4_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS4_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS4_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS4_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS4_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS4_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4801000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801000+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS4_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS4_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS4_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS4_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS4_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS4_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4801000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4801000+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS4_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) if (((per.w(ad:0xB4801000+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS4_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4801000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x20) if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4801000+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4801000+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS4_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4801000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS4_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4801000+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4801000+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS4_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS4_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS4_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS4_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS4_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS4_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS4_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS4_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS4_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS4_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS4_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS4_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS4_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS4_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS4_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS4_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS4_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS4_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS4_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS4_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS4_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS4_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS4_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS4_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4801000+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS4_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS4_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS4_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4801000+0x08))&0x20)==0x00) if (((per.l(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS4_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS4_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS4_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS4_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4801000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS4_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS4_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS4_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS4_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS4_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS4_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS4_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS4_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS4_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS4_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS4_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS4_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS4_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS4_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS4_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS4_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS4_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS4_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS4_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS4_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS4_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS4_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS4_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "Channel 5" base ad:0xB4801400 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4801400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS5_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS5_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS5_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS5_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS5_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS5_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS5_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS5_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS5_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS5_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS5_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS5_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS5_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS5_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS5_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS5_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801400+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS5_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS5_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS5_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS5_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS5_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS5_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS5_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS5_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS5_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS5_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS5_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS5_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS5_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS5_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS5_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS5_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS5_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS5_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS5_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS5_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS5_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS5_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS5_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS5_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS5_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS5_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS5_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS5_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS5_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS5_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS5_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS5_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS5_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS5_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS5_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS5_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS5_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS5_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS5_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS5_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS5_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS5_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS5_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS5_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS5_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS5_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS5_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS5_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS5_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS5_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS5_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS5_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS5_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS5_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS5_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS5_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS5_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4801400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS5_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4801400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS5_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS5_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS5_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS5_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS5_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS5_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS5_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS5_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS5_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS5_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS5_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS5_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS5_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS5_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS5_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS5_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4801400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801400+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS5_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS5_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS5_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4801400+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS5_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS5_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801400+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS5_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS5_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS5_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS5_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS5_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS5_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS5_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS5_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4801400+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4801400+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS5_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS5_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS5_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) if (((per.w(ad:0xB4801400+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS5_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4801400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801400+0x08))&0x20)==0x20) if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801400+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801400+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4801400+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS5_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS5_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4801400+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS5_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS5_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS5_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS5_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS5_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4801400+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4801400+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS5_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS5_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS5_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS5_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS5_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS5_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS5_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4801400+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS5_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS5_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801400+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4801400+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4801400+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS5_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS5_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS5_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS5_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS5_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS5_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS5_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS5_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS5_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS5_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS5_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS5_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS5_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS5_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS5_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS5_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS5_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS5_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS5_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS5_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS5_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS5_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS5_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS5_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS5_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS5_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS5_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS5_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4801400+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS5_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS5_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS5_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4801400+0x08))&0x20)==0x00) if (((per.l(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS5_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS5_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS5_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS5_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4801400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS5_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS5_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS5_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS5_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS5_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS5_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS5_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS5_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS5_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS5_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS5_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS5_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS5_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS5_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS5_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS5_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS5_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS5_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS5_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS5_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS5_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS5_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS5_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 6" base ad:0xB4801800 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4801800))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS6_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS6_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS6_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS6_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS6_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS6_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS6_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS6_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS6_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS6_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS6_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS6_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS6_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS6_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801800+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS6_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS6_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS6_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS6_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801800+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS6_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS6_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801800+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801800+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS6_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS6_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS6_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS6_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS6_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS6_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS6_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS6_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS6_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS6_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS6_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS6_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS6_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS6_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS6_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS6_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS6_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS6_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS6_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS6_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS6_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS6_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS6_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS6_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS6_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS6_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS6_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS6_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS6_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS6_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS6_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS6_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS6_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS6_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS6_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS6_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS6_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS6_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS6_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS6_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS6_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS6_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS6_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS6_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS6_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS6_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS6_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS6_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS6_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS6_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS6_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS6_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS6_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS6_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS6_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS6_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4801800))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS6_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4801800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS6_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS6_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS6_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS6_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS6_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS6_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS6_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS6_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS6_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS6_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS6_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS6_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS6_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS6_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS6_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS6_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS6_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS6_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS6_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4801800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801800+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS6_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS6_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS6_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4801800+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS6_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS6_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801800+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS6_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS6_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS6_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS6_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS6_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS6_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS6_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS6_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4801800+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4801800+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS6_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS6_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS6_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) if (((per.w(ad:0xB4801800+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS6_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4801800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801800+0x08))&0x20)==0x20) if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801800+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801800+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4801800+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS6_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS6_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4801800+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS6_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS6_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS6_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS6_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS6_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4801800+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4801800+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS6_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS6_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS6_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS6_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS6_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS6_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS6_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4801800+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS6_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS6_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801800+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4801800+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4801800+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS6_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS6_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS6_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS6_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS6_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS6_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS6_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS6_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS6_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS6_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS6_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS6_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS6_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS6_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS6_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS6_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS6_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS6_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS6_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS6_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS6_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS6_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS6_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS6_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS6_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS6_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS6_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS6_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4801800+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS6_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS6_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS6_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4801800+0x08))&0x20)==0x00) if (((per.l(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS6_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS6_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS6_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS6_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4801800+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS6_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS6_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS6_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS6_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS6_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS6_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS6_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS6_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS6_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS6_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS6_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS6_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS6_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS6_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS6_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS6_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS6_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS6_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS6_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS6_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS6_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS6_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS6_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS6_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 7" base ad:0xB4801C00 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4801C00))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS7_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS7_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS7_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS7_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS7_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS7_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS7_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS7_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS7_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS7_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS7_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS7_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS7_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS7_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801C00+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS7_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS7_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS7_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS7_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801C00+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS7_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS7_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801C00+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801C00+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS7_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS7_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS7_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS7_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS7_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS7_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS7_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS7_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS7_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS7_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS7_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS7_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS7_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS7_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS7_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS7_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS7_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS7_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS7_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS7_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS7_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS7_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS7_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS7_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS7_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS7_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS7_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS7_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS7_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS7_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS7_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS7_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS7_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS7_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS7_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS7_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS7_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS7_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS7_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS7_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS7_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS7_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS7_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS7_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS7_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS7_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS7_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS7_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS7_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS7_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS7_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS7_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS7_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS7_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS7_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS7_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4801C00))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS7_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4801C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS7_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS7_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS7_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS7_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS7_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS7_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS7_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS7_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS7_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS7_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS7_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS7_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS7_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS7_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS7_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS7_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS7_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS7_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS7_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4801C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801C00+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS7_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS7_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS7_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS7_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS7_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801C00+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS7_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS7_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS7_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS7_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS7_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS7_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS7_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS7_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4801C00+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS7_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS7_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS7_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) if (((per.w(ad:0xB4801C00+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS7_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4801C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801C00+0x08))&0x20)==0x20) if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801C00+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4801C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801C00+0x08))&0x20)==0x00) if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4801C00+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS7_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS7_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4801C00+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS7_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS7_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS7_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS7_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS7_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x00) if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS7_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS7_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS7_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS7_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS7_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS7_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS7_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4801C00+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS7_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS7_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4801C00+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS7_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS7_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS7_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS7_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS7_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS7_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS7_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS7_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS7_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS7_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS7_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS7_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS7_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS7_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS7_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS7_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS7_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS7_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS7_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS7_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS7_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS7_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS7_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS7_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS7_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS7_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS7_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS7_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4801C00+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS7_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS7_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS7_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4801C00+0x08))&0x20)==0x00) if (((per.l(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS7_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS7_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS7_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS7_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4801C00+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS7_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS7_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS7_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS7_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS7_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS7_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS7_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS7_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS7_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS7_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS7_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS7_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS7_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS7_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS7_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS7_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS7_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS7_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS7_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS7_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS7_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS7_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS7_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS7_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end endif tree "Channel 8" base ad:0xB4880000 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4880000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS8_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS8_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS8_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS8_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS8_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS8_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS8_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS8_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS8_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS8_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS8_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880000+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS8_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS8_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS8_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS8_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS8_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS8_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS8_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS8_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS8_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS8_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS8_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS8_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS8_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS8_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS8_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS8_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS8_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS8_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS8_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS8_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS8_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS8_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS8_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS8_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS8_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS8_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS8_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS8_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS8_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS8_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS8_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS8_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS8_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS8_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS8_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS8_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS8_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS8_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS8_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS8_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS8_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS8_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS8_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4880000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS8_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4880000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS8_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS8_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS8_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS8_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS8_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS8_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS8_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS8_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS8_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS8_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS8_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4880000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880000+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS8_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS8_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS8_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS8_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS8_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS8_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4880000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4880000+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS8_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) if (((per.w(ad:0xB4880000+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS8_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4880000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x20) if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4880000+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4880000+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS8_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4880000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS8_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4880000+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4880000+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS8_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS8_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS8_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS8_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS8_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS8_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS8_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS8_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS8_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS8_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS8_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS8_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS8_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS8_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS8_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS8_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS8_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS8_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS8_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS8_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS8_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS8_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS8_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS8_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4880000+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS8_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS8_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS8_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4880000+0x08))&0x20)==0x00) if (((per.l(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS8_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS8_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS8_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS8_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4880000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS8_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS8_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS8_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS8_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS8_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS8_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS8_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS8_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS8_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS8_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS8_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS8_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS8_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS8_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS8_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS8_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS8_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS8_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS8_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS8_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS8_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS8_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS8_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 9" base ad:0xB4880400 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4880400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS9_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS9_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS9_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS9_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880400+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS9_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS9_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS9_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS9_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS9_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS9_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS9_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS9_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS9_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS9_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS9_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS9_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS9_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS9_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS9_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS9_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS9_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS9_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS9_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS9_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS9_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS9_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS9_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS9_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS9_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS9_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS9_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS9_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS9_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS9_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS9_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS9_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS9_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS9_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS9_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS9_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS9_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS9_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS9_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS9_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS9_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS9_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4880400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS9_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4880400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS9_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS9_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS9_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4880400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880400+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS9_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS9_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS9_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS9_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS9_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS9_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4880400+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4880400+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS9_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) if (((per.w(ad:0xB4880400+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS9_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4880400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x20) if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4880400+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4880400+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS9_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4880400+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS9_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4880400+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4880400+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS9_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS9_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS9_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS9_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS9_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS9_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS9_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS9_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS9_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS9_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS9_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS9_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS9_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS9_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS9_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS9_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS9_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS9_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS9_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS9_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS9_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS9_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS9_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS9_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4880400+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS9_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS9_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS9_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4880400+0x08))&0x20)==0x00) if (((per.l(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS9_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS9_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS9_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS9_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4880400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS9_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS9_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS9_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS9_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS9_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS9_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS9_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS9_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS9_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS9_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS9_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS9_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS9_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS9_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS9_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS9_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS9_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS9_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS9_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS9_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS9_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS9_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 10" base ad:0xB4880800 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4880800))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS10_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS10_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS10_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS10_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS10_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS10_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS10_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS10_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS10_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS10_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS10_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS10_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS10_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS10_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880800+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880800+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880800+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880800+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS10_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS10_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS10_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS10_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS10_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS10_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS10_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS10_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS10_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS10_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS10_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS10_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS10_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS10_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS10_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS10_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS10_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS10_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS10_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS10_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS10_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS10_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS10_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS10_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS10_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS10_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS10_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS10_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS10_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS10_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS10_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS10_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS10_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS10_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS10_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS10_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS10_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS10_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS10_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS10_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS10_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS10_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS10_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS10_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS10_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4880800))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS10_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4880800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS10_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS10_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS10_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS10_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS10_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS10_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS10_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS10_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS10_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS10_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS10_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS10_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS10_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS10_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS10_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4880800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880800+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS10_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS10_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS10_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS10_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS10_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS10_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS10_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4880800+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4880800+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS10_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) if (((per.w(ad:0xB4880800+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS10_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4880800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x20) if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4880800+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4880800+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS10_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4880800+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS10_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4880800+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4880800+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS10_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS10_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS10_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS10_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS10_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS10_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS10_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS10_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS10_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS10_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS10_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS10_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS10_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS10_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS10_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS10_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS10_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS10_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS10_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS10_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS10_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS10_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS10_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS10_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4880800+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS10_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS10_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS10_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4880800+0x08))&0x20)==0x00) if (((per.l(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS10_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS10_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS10_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS10_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4880800+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS10_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS10_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS10_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS10_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS10_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS10_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS10_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS10_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS10_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS10_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS10_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS10_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS10_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS10_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS10_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS10_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS10_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS10_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS10_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS10_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS10_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS10_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS10_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS10_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 11" base ad:0xB4880C00 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4880C00))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS11_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS11_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS11_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS11_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS11_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS11_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS11_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS11_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS11_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS11_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS11_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS11_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS11_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS11_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880C00+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880C00+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880C00+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880C00+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS11_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS11_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS11_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS11_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS11_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS11_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS11_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS11_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS11_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS11_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS11_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS11_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS11_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS11_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS11_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS11_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS11_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS11_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS11_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS11_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS11_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS11_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS11_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS11_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS11_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS11_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS11_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS11_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS11_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS11_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS11_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS11_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS11_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS11_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS11_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS11_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS11_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS11_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS11_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS11_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS11_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS11_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS11_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS11_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS11_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4880C00))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS11_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS11_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS11_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS11_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS11_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS11_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS11_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS11_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS11_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS11_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS11_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS11_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS11_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS11_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS11_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS11_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4880C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880C00+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS11_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS11_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS11_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS11_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS11_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS11_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS11_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS11_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) if (((per.w(ad:0xB4880C00+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS11_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x20) if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x00) if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00) if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4880C00+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4880C00+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS11_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x00) if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS11_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4880C00+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4880C00+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS11_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS11_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS11_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS11_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS11_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS11_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS11_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS11_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS11_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS11_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS11_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS11_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS11_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS11_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS11_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS11_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS11_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS11_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS11_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS11_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS11_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS11_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS11_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS11_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4880C00+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS11_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS11_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS11_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4880C00+0x08))&0x20)==0x00) if (((per.l(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS11_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS11_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS11_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS11_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4880C00+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS11_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS11_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS11_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS11_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS11_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS11_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS11_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS11_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS11_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS11_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS11_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS11_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS11_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS11_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS11_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS11_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS11_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS11_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS11_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS11_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS11_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS11_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS11_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS11_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 12" base ad:0xB4881000 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB4881000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS12_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4881000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS12_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS12_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS12_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS12_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4881000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4881000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS12_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS12_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS12_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS12_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS12_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS12_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS12_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS12_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS12_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4881000+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4881000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS12_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4881000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS12_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS12_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS12_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS12_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS12_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS12_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS12_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS12_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS12_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS12_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS12_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS12_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS12_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS12_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS12_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS12_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS12_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS12_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS12_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS12_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS12_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS12_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS12_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS12_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS12_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS12_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS12_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4881000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS12_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS12_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS12_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS12_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS12_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS12_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS12_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS12_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS12_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS12_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS12_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS12_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS12_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS12_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS12_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS12_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS12_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB4881000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS12_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB4881000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS12_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS12_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS12_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS12_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4881000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4881000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS12_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS12_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS12_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS12_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS12_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS12_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS12_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS12_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS12_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS12_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS12_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB4881000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4881000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4881000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4881000+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS12_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB4881000+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4881000+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4881000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS12_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS12_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS12_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS12_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS12_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS12_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x60) width 19. if (((per.b(ad:0xB4881000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB4881000+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS12_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) if (((per.w(ad:0xB4881000+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS12_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB4881000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4881000+0x08))&0x20)==0x20) if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4881000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4881000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB4881000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4881000+0x08))&0x20)==0x00) if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00) if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_LIN_STMR,Serial timer register" if (((per.w(ad:0xB4881000+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB4881000+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS12_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB4881000+0x12))&0x01)==0x00) if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB4881000+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS12_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB4881000+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB4881000+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB4881000+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB4881000+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS12_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS12_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS12_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS12_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS12_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS12_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS12_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS12_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS12_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS12_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS12_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS12_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS12_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS12_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS12_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS12_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS12_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS12_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS12_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS12_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS12_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS12_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS12_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS12_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB4881000+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS12_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS12_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS12_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB4881000+0x08))&0x20)==0x00) if (((per.l(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS12_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS12_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS12_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS12_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB4881000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS12_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS12_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS12_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4881000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS12_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS12_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS12_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS12_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS12_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS12_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS12_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS12_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS12_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS12_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS12_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS12_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS12_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS12_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS12_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS12_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS12_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS12_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS12_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS12_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS12_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 16" base ad:0xB06A8000 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB06A8000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS16_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB06A8000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS16_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS16_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS16_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS16_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB06A8000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB06A8000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS16_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS16_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS16_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS16_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS16_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS16_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS16_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS16_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS16_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x40)||(((per.w(ad:0xB06A8000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB06A8000+0x02))&0x20)==0x00)||((((per.b(ad:0xB06A8000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB06A8000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS16_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS16_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS16_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS16_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB06A8000+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS16_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS16_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x40)||(((per.w(ad:0xB06A8000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB06A8000+0x02))&0x20)==0x00)||((((per.b(ad:0xB06A8000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB06A8000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB06A8000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS16_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS16_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB06A8000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB06A8000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB06A8000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS16_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS16_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS16_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS16_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS16_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS16_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8000))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS16_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS16_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS16_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS16_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS16_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS16_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS16_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS16_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS16_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS16_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS16_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS16_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS16_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS16_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS16_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS16_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS16_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS16_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS16_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS16_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS16_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS16_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS16_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS16_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS16_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS16_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS16_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS16_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS16_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS16_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS16_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB06A8000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS16_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS16_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS16_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS16_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS16_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS16_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS16_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS16_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS16_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS16_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS16_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS16_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS16_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS16_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS16_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS16_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS16_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB06A8000))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS16_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB06A8000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS16_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS16_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS16_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS16_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB06A8000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB06A8000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS16_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS16_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB06A8000+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB06A8000+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS16_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS16_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS16_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS16_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS16_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS16_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS16_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS16_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS16_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8000))&0xE0)==0x40) width 21. if (((per.b(ad:0xB06A8000+0x01))&0x43)==0x40)||(((per.w(ad:0xB06A8000+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS16_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS16_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x40)||(((per.w(ad:0xB06A8000+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS16_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS16_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB06A8000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB06A8000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB06A8000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB06A8000+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS16_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS16_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8000+0x01))&0x43)==0x40)||(((per.w(ad:0xB06A8000+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS16_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB06A8000+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS16_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS16_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB06A8000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB06A8000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB06A8000+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB06A8000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB06A8000+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB06A8000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB06A8000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS16_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS16_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS16_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS16_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS16_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS16_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS16_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS16_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8000))&0xE0)==0x60) width 19. if (((per.b(ad:0xB06A8000+0x12))&0x01)==0x00) if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB06A8000+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS16_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS16_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS16_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x00) if (((per.w(ad:0xB06A8000+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS16_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB06A8000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB06A8000+0x08))&0x20)==0x20) if (((per.b(ad:0xB06A8000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8000+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB06A8000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB06A8000+0x08))&0x20)==0x00) if (((per.b(ad:0xB06A8000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8000+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB06A8000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB06A8000+0x08))&0x20)==0x00) if (((per.b(ad:0xB06A8000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8000+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB06A8000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8000+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_LIN_STMR,Serial timer register" if (((per.w(ad:0xB06A8000+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS16_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS16_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB06A8000+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS16_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS16_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS16_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS16_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS16_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB06A8000+0x12))&0x01)==0x00) if (((per.b(ad:0xB06A8000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8000+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB06A8000+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS16_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS16_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS16_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS16_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS16_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS16_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS16_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB06A8000+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS16_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS16_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB06A8000+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB06A8000+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB06A8000+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS16_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS16_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS16_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS16_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS16_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS16_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS16_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS16_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS16_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS16_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS16_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS16_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS16_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS16_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS16_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB06A8000+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS16_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS16_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS16_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS16_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS16_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS16_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS16_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS16_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS16_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS16_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8000))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS16_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS16_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS16_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB06A8000+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS16_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS16_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS16_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB06A8000+0x08))&0x20)==0x00) if (((per.l(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS16_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS16_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS16_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS16_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB06A8000+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS16_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS16_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS16_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB06A8000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS16_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS16_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS16_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS16_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS16_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS16_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS16_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS16_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS16_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS16_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS16_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS16_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS16_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS16_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS16_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS16_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS16_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS16_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS16_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS16_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS16_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end tree "Channel 17" base ad:0xB06A8400 sif (cpuis("S6J336*")||cpuis("S6J337*")) if (((per.b(ad:0xB06A8400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS17_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB06A8400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS17_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS17_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS17_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS17_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB06A8400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB06A8400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS17_UART_RDR/TDR,Reception/Transmission Data Register" in group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_UART_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS17_UART_STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "MFS17_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS17_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" newline hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS17_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS17_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS17_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS17_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS17_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x40)||(((per.w(ad:0xB06A8400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB06A8400+0x02))&0x20)==0x00)||((((per.b(ad:0xB06A8400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB06A8400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "MFS17_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS17_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" newline bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS17_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS17_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB06A8400+0x03))&0x06)==0x02) group.byte 0x03++0x00 line.byte 0x00 "MFS17_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS17_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x40)||(((per.w(ad:0xB06A8400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB06A8400+0x02))&0x20)==0x00)||((((per.b(ad:0xB06A8400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB06A8400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB06A8400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L3_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "MFS17_UART_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_CSIO_STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "MFS17_CSIO_STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB06A8400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" newline bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" newline bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else group.byte 0x10++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB06A8400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB06A8400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Inactive-time level of serial chip select pin 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Serial clock format assumed when serial chip select pin 1 is active" "'H' format,'L' format" bitfld.byte 0x00 5. " CS1SPI ,SPI support mode when serial chip select pin 1 is active" "Not supported,Supported" newline bitfld.byte 0x00 4. " CS1BDS ,Transfer direction type when serial chip select pin 1 is active" "LSB first,MSB first" bitfld.byte 0x00 0.--3. " CS1L ,Data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Inactive-time level of serial chip select pin 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Serial clock format assumed when serial chip select pin 2 is active" "'H' format,'L' format" bitfld.byte 0x01 5. " CS1SPI ,SPI support mode when serial chip select pin 2 is active" "Not supported,Supported" newline bitfld.byte 0x01 4. " CS2BDS ,Transfer direction type when serial chip select pin 2 is active" "LSB first,MSB first" bitfld.byte 0x01 0.--3. " CS2L ,Data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Inactive-time level of serial chip select pin 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Serial clock format assumed when serial chip select pin 3 is active" "'H' format,'L' format" bitfld.byte 0x02 5. " CS3SPI ,SPI support mode when serial chip select pin 3 is active" "Not supported,Supported" newline bitfld.byte 0x02 4. " CS3BDS ,Transfer direction type when serial chip select pin 3 is active" "LSB first,MSB first" bitfld.byte 0x02 0.--3. " CS3L ,Data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE0,Transfer Byte Register 0" rgroup.byte 0x19++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE1,Transfer Byte Register 1" rgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE2,Transfer Byte Register 2" rgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS17_CSIO_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS17_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS17_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS17_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS17_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS17_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8400))&0xE0)==0x60) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_setclr ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "MFS17_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "Odd,Even" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "MFS17_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1||2,3||4" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS17_LIN_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_LIN_STMR,Serial timer register" group.word 0x0C++0x01 line.word 0x00 "MFS17_LIN_STMCR,Serial timer comparison register" group.word 0x0E++0x03 line.word 0x00 "MFS17_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS17_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" group.word 0x1C++0x01 line.word 0x00 "MFS17_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x12++0x00 line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "MFS17_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS17_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS17_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "MFS17_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE_SET/CLR ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE_SET/CLR ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE_SET/CLR ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE_SET/CLR ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE_SET/CLR ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE_SET/CLR ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS17_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "MFS17_LIN_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS17_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS17_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS17_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_LIN_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS17_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS17_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS17_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS17_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS17_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS17_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS17_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS17_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgement enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS17_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS17_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "MFS17_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS17_I2C_RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "MFS17_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio|8MHz/10MHz|16MHz|20MHz|24MHz|32MHz)" "/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,/4|500ns|400ns|250ns|200ns|166.667ns|125ns,/8|1us|800ns|500ns|400ns|333.33ns|250ns,/16|2us|1.6us|1us|800ns|666.67ns|500ns,/32|4us|3.2us|2us|1.6us|1.33us|1us,/64|8us|6.4us|4us|3.2us|2.67us|2us,/128|16us|12.8us|8us|6.4us|5.33us|4us,/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" newline rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" group.word 0x0C++0x01 line.word 0x00 "MFS17_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" group.byte 0x10++0x00 line.byte 0x00 "MFS17_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB06A8400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS17_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS17_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS17_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS17_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS17_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS17_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS17_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS17_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS17_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_I2C_TBSIZE,Transmission Block Size Register" group.byte 0x2E++0x00 line.byte 0x00 "MFS17_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" group.word 0x30++0x01 line.word 0x00 "MFS17_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" group.byte 0x3D++0x00 line.byte 0x00 "MFS17_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" group.byte 0x43++0x00 line.byte 0x00 "MFS17_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" group.byte 0x45++0x00 line.byte 0x00 "MFS17_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS17_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" group.byte 0x54++0x00 line.byte 0x00 "MFS17_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS17_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif else if (((per.b(ad:0xB06A8400))&0xE0)<0x40) width 20. group.byte 0x01++0x00 line.byte 0x00 "MFS17_UART_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" textline " " if (((per.b(ad:0xB06A8400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "MFS17_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS17_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "MFS17_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS17_UART_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB06A8400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB06A8400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS17_UART_ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" textline " " bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x04++0x01 hide.word 0x00 "MFS17_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB06A8400+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif else if (((per.w(ad:0xB06A8400+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_UART_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_UART_STMR,Serial Timer Register" if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS17_UART_STMCR,Serial Timer Comparison Register" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS17_UART_STMCR,Serial Timer Comparison Register" endif group.byte 0x18++0x00 line.byte 0x00 "MFS17_UART_TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "MFS17_UART_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS17_UART_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_UART_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS17_UART_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "MFS17_UART_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "MFS17_UART_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_UART_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_UART_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_UART_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_UART_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS17_UART_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8400))&0xE0)==0x40) width 21. if (((per.b(ad:0xB06A8400+0x01))&0x43)==0x40)||(((per.w(ad:0xB06A8400+0x0E))&0x1E)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS17_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" textline " " bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS17_CSIO_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x40)||(((per.w(ad:0xB06A8400+0x0E))&0x1E)==0x0) group.byte 0x00++0x00 line.byte 0x00 "MFS17_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS17_CSIO_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if ((((per.b(ad:0xB06A8400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB06A8400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB06A8400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB06A8400+0x03))&0x4)==0x0)) group.byte 0x03++0x00 line.byte 0x00 "MFS17_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS17_CSIO_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB06A8400+0x01))&0x43)==0x40)||(((per.w(ad:0xB06A8400+0x0E))&0x1E)==0x00) group.byte 0x02++0x00 line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*") bitfld.byte 0x00 6. " L3 ,L3" "0,1" textline " " endif bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif hgroup.long 0x04++0x03 hide.long 0x00 "MFS17_UART_RDR/TDR,Reception/Transmission Data Register" in sif (cpuis("S6J33*")) if (((per.w(ad:0xB06A8400+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x20)==0x20) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x01) group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." textline " " setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_CSIO_STMR,Serial Timer Register" if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x01) rgroup.word 0x0C++0x01 line.word 0x00 "MFS17_CSIO_STMCR,Serial Timer Comparison Register" else group.word 0x0C++0x01 line.word 0x00 "MFS17_CSIO_STMCR,Serial Timer Comparison Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB06A8400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB06A8400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" textline " " bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6," bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x40) group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" textline " " rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif endif if (((per.b(ad:0xB06A8400+0x01))&0x43)==(0x01||0x02||0x03)) rgroup.byte 0x10++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0" rgroup.byte 0x11++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1" rgroup.word 0x12++0x01 line.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x00) group.byte 0x10++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0" group.byte 0x11++0x00 line.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1" group.word 0x12++0x01 line.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" else hgroup.byte 0x10++0x00 hide.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0" hgroup.byte 0x11++0x00 hide.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1" hgroup.word 0x12++0x01 hide.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3" endif if (((per.b(ad:0xB06A8400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB06A8400+0x02))&0x20)==0x20) rgroup.byte 0x14++0x02 line.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," elif (((per.b(ad:0xB06A8400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB06A8400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" textline " " bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x01 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" textline " " bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," line.byte 0x02 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" textline " " bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit," else hgroup.byte 0x14++0x00 hide.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0" hgroup.byte 0x15++0x00 hide.byte 0x00 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1" hgroup.byte 0x16++0x00 hide.byte 0x00 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2" endif if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x00) group.byte 0x18++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE0,Transfer Byte Register 0" group.byte 0x19++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE1,Transfer Byte Register 1" group.byte 0x1A++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE2,Transfer Byte Register 2" group.byte 0x1B++0x00 line.byte 0x00 "MFS17_CSIO_TBYTE3,Transfer Byte Register 3" else hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE0,Transfer Byte Register 0" hgroup.byte 0x19++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE1,Transfer Byte Register 1" hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE2,Transfer Byte Register 2" hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS17_CSIO_TBYTE3,Transfer Byte Register 3" endif group.word 0x1C++0x01 line.word 0x00 "MFS17_CSIO_BGR,Baud Rate Generator Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" else textline " " hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif group.byte 0x21++0x00 line.byte 0x00 "MFS17_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_CSIO_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS17_CSIO_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS17_CSIO_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS17_CSIO_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_CSIO_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_CSIO_TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_CSIO_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_CSIO_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS17_CSIO_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8400))&0xE0)==0x60) width 19. if (((per.b(ad:0xB06A8400+0x12))&0x01)==0x00) if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif else if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x00) group.byte 0x01++0x00 line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif endif textline " " if (((per.b(ad:0xB06A8400+0x02))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "MFS17_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "MFS17_LIN_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." textline " " bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x03++0x00 line.byte 0x00 "MFS17_LIN_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x00) if (((per.w(ad:0xB06A8400+0x12))&0x01)==0x01) group.byte 0x02++0x00 line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" else group.byte 0x02++0x00 line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..." bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" endif else group.byte 0x02++0x00 line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit" bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS17_LIN_RDR/TDR,Reception/Transmission Data Register" in textline " " if (((per.w(ad:0xB06A8400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB06A8400+0x08))&0x20)==0x20) if (((per.b(ad:0xB06A8400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8400+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," textline " " rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB06A8400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB06A8400+0x08))&0x20)==0x00) if (((per.b(ad:0xB06A8400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8400+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" textline " " bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif elif (((per.w(ad:0xB06A8400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB06A8400+0x08))&0x20)==0x00) if (((per.b(ad:0xB06A8400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8400+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif else if (((per.b(ad:0xB06A8400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8400+0x01))&0x01)==0x00) if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif else if (((per.w(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register" rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled" textline " " rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..." textline " " bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled" endif endif endif textline " " rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_LIN_STMR,Serial timer register" if (((per.w(ad:0xB06A8400+0x08))&0x1)==0x1) rgroup.word 0x0C++0x01 line.word 0x00 "MFS17_LIN_STMCR,Serial timer comparison register" else group.word 0x0C++0x01 line.word 0x00 "MFS17_LIN_STMCR,Serial timer comparison register" endif if (((per.w(ad:0xB06A8400+0x08))&0x800)==0x800) rgroup.word 0x0E++0x03 line.word 0x00 "MFS17_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS17_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" else group.word 0x0E++0x03 line.word 0x00 "MFS17_LIN_SFUR,Sync Field Upper Limit Register" hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits" line.word 0x02 "MFS17_LIN_SFLR,Sync Field Lower Limit Register" hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits" endif group.word 0x1C++0x01 line.word 0x00 "MFS17_LIN_BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" textline " " sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA") hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register" textline " " else hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" endif if (((per.b(ad:0xB06A8400+0x12))&0x01)==0x00) if (((per.b(ad:0xB06A8400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB06A8400+0x01))&0x01)==0x00) group.byte 0x12++0x00 line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif else if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x40) group.byte 0x12++0x00 line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" else group.byte 0x12++0x00 line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended" textline " " bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID" bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist" endif endif if (((per.b(ad:0xB06A8400+0x12))&0x01)==0x01) rgroup.byte 0x13++0x00 line.byte 0x00 "MFS17_LIN_LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" textline " " bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "MFS17_LIN_LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "MFS17_LIN_LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.byte 0x13++0x00 hide.byte 0x00 "MFS17_LIN_LAMSR,LIN Assist Mode Status Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS17_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register" hgroup.byte 0x18++0x00 hide.byte 0x00 "MFS17_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register" endif group.byte 0x19++0x00 line.byte 0x00 "MFS17_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register" bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" if (((per.w(ad:0xB06A8400+0x12))&0x01)==0x01) rgroup.byte 0x1B++0x00 line.byte 0x00 "MFS17_LIN_LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" else hgroup.byte 0x1B++0x00 hide.byte 0x00 "MFS17_LIN_LAMESR,LIN Assist Mode Error Status Register" endif sif (cpuis("S6J33*")) if (((per.b(ad:0xB06A8400+0x12))&0x01)==0x01) group.byte 0x1A++0x00 line.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register" endif else if (((per.b(ad:0xB06A8400+0x12))&0x01)==0x01) rgroup.byte 0x1A++0x00 line.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register" sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA") bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" textline " " else bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" endif textline " " bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" else hgroup.byte 0x1A++0x00 hide.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register" endif endif if (((per.b(ad:0xB06A8400+0x21))&0x04)==0x00) group.byte 0x21++0x00 line.byte 0x00 "MFS17_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" else group.byte 0x21++0x00 line.byte 0x00 "MFS17_LIN_FCR1,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" textline " " bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1" endif group.byte 0x20++0x00 line.byte 0x00 "MFS17_LIN_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "MFS17_LIN_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "MFS17_LIN_FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "MFS17_LIN_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_LIN_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_LIN_TBSIZE,Transmission Block Size Register" textline " " wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS17_LIN_SCRC,Serial Control Clear Register" bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear" bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear" bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear" bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear" bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear" wgroup.byte 0x2C++0x00 line.byte 0x00 "MFS17_LIN_SMRC,Serial Mode Clear Register" bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear" bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear" bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear" wgroup.byte 0x2F++0x00 line.byte 0x00 "MFS17_LIN_SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS17_LIN_ESCRC,Extended Communication Control Clear Register" bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear" bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_LIN_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear" bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear" bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear" bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear" textline " " bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear" bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear" bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "MFS17_LIN_LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x36++0x00 line.byte 0x00 "MFS17_LIN_LAMCRC,LIN Assist Mode Control Clear Register" bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear" bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear" bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear" wgroup.byte 0x39++0x00 line.byte 0x00 "MFS17_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register" bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear" bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear" bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear" textline " " bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear" bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "MFS17_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_LIN_FCR1C,FIFO Control Register 1" bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear" bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" textline " " bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear" bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear" wgroup.byte 0x3C++0x00 line.byte 0x00 "MFS17_LIN_FCR0C,FIFO Control CLear Register 0" bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear" bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_LIN_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" if (((per.b(ad:0xB06A8400+0x01))&0x40)==0x00) wgroup.byte 0x45++0x00 line.byte 0x00 "MFS17_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set" textline " " bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" else wgroup.byte 0x45++0x00 line.byte 0x00 "MFS17_LIN_SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set" bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set" bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set" bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set" textline " " bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set" endif wgroup.byte 0x44++0x00 line.byte 0x00 "MFS17_LIN_SMRS,Serial Mode Set Register" bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set" bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set" bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "MFS17_LIN_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x46++0x00 line.byte 0x00 "MFS17_LIN_ESCRS,Extended Communication Control Set Register" bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set" bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set" wgroup.word 0x48++0x01 line.word 0x00 "MFS17_LIN_SACSRS,Serial Auxiliary Control Status Set Register" bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set" bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set" bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set" textline " " bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set" bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set" bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "MFS17_LIN_LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set" bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set" bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set" wgroup.byte 0x51++0x00 line.byte 0x00 "MFS17_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register" bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set" bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set" bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set" textline " " bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set" bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set" bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set" wgroup.byte 0x55++0x00 line.byte 0x00 "MFS17_LIN_FCR1S,FIFO Control Set Register 1" bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set" bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set" bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set" bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "MFS17_LIN_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set" bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set" width 0x0B elif (((per.b(ad:0xB06A8400))&0xE0)==0x80) width 19. group.byte 0x01++0x00 line.byte 0x00 "MFS17_I2C_IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_set/clr ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC_set/clr ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_set/clr ,Data byte acknowledgement enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_set/clr ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_set/clr ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_set/clr ,Interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "MFS17_I2C_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_set/clr ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_set/clr ,Reception interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_set/clr ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "MFS17_I2C_IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgement flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration Lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not Detected,Detected" textline " " bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not Detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" if (((per.l(ad:0xB06A8400+0x03))&0x20)==0x20) group.byte 0x03++0x00 line.byte 0x00 "MFS17_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" textline " " rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "MFS17_I2C_SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_set/clr ,DMA mode enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "MFS17_I2C_RDR/TDR,Reception/Transmission Data Register" in if (((per.l(ad:0xB06A8400+0x08))&0x20)==0x00) if (((per.l(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x08++0x01 line.word 0x00 "MFS17_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" else group.word 0x08++0x01 line.word 0x00 "MFS17_I2C_SACSR,Serial Auxiliary Control Status Register" rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both," bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" textline " " setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif else group.word 0x08++0x01 line.word 0x00 "MFS17_I2C_SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled" endif rgroup.word 0x0A++0x01 line.word 0x00 "MFS17_I2C_STMR,Serial Timer Register" hexmask.word 0x00 0.--15. 1. " TM ,Timer data bits" if (((per.l(ad:0xB06A8400+0x08))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "MFS17_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" else rgroup.word 0x0C++0x01 line.word 0x00 "MFS17_I2C_STMCR,Serial Timer Comparison Register" hexmask.word 0x00 0.--15. 1. " TC ,Compare bits" endif group.byte 0x10++0x00 line.byte 0x00 "MFS17_I2C_NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB06A8400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "MFS17_I2C_EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "MFS17_I2C_EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "MFS17_I2C_ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SM ,Slave address mask bits" group.byte 0x1E++0x00 line.byte 0x00 "MFS17_I2C_ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.word 0x1C++0x01 line.word 0x00 "MFS17_I2C_BGR,Baud Rate Generator Register" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "MFS17_CSIO_FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" textline " " setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "MFS17_I2C_FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer reload bit" "Not saved,Saved" textline " " bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,FIFO2" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,FIFO1" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" textline " " setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "MFS17_I2C_FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" group.word 0x24++0x01 line.word 0x00 "MFS17_I2C_FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "MFS17_I2C_ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "MFS17_I2C_ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "MFS17_I2C_TBSIZE,Transmission Block Size Register" wgroup.byte 0x2D++0x00 line.byte 0x00 "MFS17_I2C_IBCRC,Bus Control Clear Register" bitfld.byte 0x00 0. " INTC ,Clearing the interrupt flag" ",Clear" wgroup.byte 0x2E++0x00 line.byte 0x00 "MFS17_I2C_IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "MFS17_UART_SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "MFS17_I2C_FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "MFS17_I2C_ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" textline " " bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "MFS17_I2C_IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" group.byte 0x47++0x00 line.byte 0x00 "MFS17_I2C_SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" "No effect,Setting" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" "No effect,Setting" group.byte 0x54++0x00 line.byte 0x00 "MFS17_I2C_FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" "No effect,Setting" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" "No effect,Setting" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" "No effect,Setting" textline " " bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" "No effect,Setting" width 0x0B else width 16. group.byte 0x00++0x00 line.byte 0x00 "MFS17_UART_SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif endif width 0xB tree.end endif tree.end tree "BT (Base Timer)" tree "Channel 0" base ad:0xB4808000 width 14. if (((per.w(ad:0xB4808000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4808000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL01,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else group.long 0x30++0x03 line.long 0x00 "BTSEL01,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.l(ad:0xB4808000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" elif cpuis("S6J33*") if (((per.l(ad:0xB4808000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" else if (((per.l(ad:0xB4808000+0x30))&0x0F)==(0x05||0x06)) group.long 0x04++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x04++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif group.long 0x08++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" endif width 0x0B tree.end tree "Channel 1" base ad:0xB4808400 width 14. if (((per.w(ad:0xB4808400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4808400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 2" base ad:0xB4808800 width 14. if (((per.w(ad:0xB4808800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4808800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL23,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL23 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else group.long 0x30++0x03 line.long 0x00 "BTSEL23,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL23 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 3" base ad:0xB4808C00 width 14. if (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4808C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4808C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4808C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 4" base ad:0xB4809000 width 14. if (((per.w(ad:0xB4809000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4809000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL45,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL45 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else group.long 0x30++0x03 line.long 0x00 "BTSEL45,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL45 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 5" base ad:0xB4809400 width 14. if (((per.w(ad:0xB4809400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4809400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 6" base ad:0xB4809800 width 14. if (((per.w(ad:0xB4809800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4809800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL67,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL67 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else group.long 0x30++0x03 line.long 0x00 "BTSEL67,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL67 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 7" base ad:0xB4809C00 width 14. if (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4809C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4809C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4809C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 8" base ad:0xB480A000 width 14. if (((per.w(ad:0xB480A000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB480A000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480A000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480A000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480A000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480A000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480A000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480A000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL89,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL89 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else group.long 0x30++0x03 line.long 0x00 "BTSEL89,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL89 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 9" base ad:0xB480A400 width 14. if (((per.w(ad:0xB480A400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB480A400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480A400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480A400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480A400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480A400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480A400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480A400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 10" base ad:0xB480A800 width 14. if (((per.w(ad:0xB480A800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB480A800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480A800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480A800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480A800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480A800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480A800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480A800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480A800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1011,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1011 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else group.long 0x30++0x03 line.long 0x00 "BTSEL1011,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1011 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 11" base ad:0xB480AC00 width 14. if (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480AC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480AC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480AC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB480AC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB480AC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB480AC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 12" base ad:0xB4888000 width 14. if (((per.w(ad:0xB4888000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1213,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1213 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.l(ad:0xB4888000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" elif cpuis("S6J33*") if (((per.l(ad:0xB4888000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" else if (((per.l(ad:0xB4888000+0x30))&0x0F)==(0x05||0x06)) group.long 0x04++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x04++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif group.long 0x08++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" endif width 0x0B tree.end tree "Channel 13" base ad:0xB4888400 width 14. if (((per.w(ad:0xB4888400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4888400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 14" base ad:0xB4888000 width 14. if (((per.w(ad:0xB4888000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1415,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1415 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 15" base ad:0xB488C000 width 14. if (((per.w(ad:0xB488C000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB488C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB488C000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB488C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488C000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB488C000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488C000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488C000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488C000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488C000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488C000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488C000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488C000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488C000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB488C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end else tree "Channel 14" base ad:0xB4888800 width 14. if (((per.w(ad:0xB4888800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4888800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1415,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1415 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 15" base ad:0xB4888C00 width 14. if (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4888C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4888C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4888C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end endif tree "Channel 16" base ad:0xB4889000 width 14. if (((per.w(ad:0xB4889000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4889000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1617,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1617 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 17" base ad:0xB4889400 width 14. if (((per.w(ad:0xB4889400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4889400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 18" base ad:0xB4898000 width 14. if (((per.w(ad:0xB4898000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4898000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4898000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4898000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4898000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4898000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4898000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4898000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4898000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4898000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4898000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4898000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4898000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4898000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4898000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1819,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1819 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 19" base ad:0xB489C000 width 14. if (((per.w(ad:0xB489C000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB489C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB489C000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB489C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB489C000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB489C000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB489C000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB489C000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB489C000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB489C000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB489C000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB489C000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB489C000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB489C000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB489C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end else tree "Channel 18" base ad:0xB4889800 width 14. if (((per.w(ad:0xB4889800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4889800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL1819,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1819 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 19" base ad:0xB4889C00 width 14. if (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4889C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4889C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4889C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end endif tree "Channel 20" base ad:0xB488A000 width 14. if (((per.w(ad:0xB488A000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB488A000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488A000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488A000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488A000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488A000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488A000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488A000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL2021,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2021 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 21" base ad:0xB488A400 width 14. if (((per.w(ad:0xB488A400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB488A400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488A400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488A400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488A400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488A400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488A400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488A400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 22" base ad:0xB488A800 width 14. if (((per.w(ad:0xB488A800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB488A800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488A800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488A800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488A800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488A800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488A800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488A800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488A800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL2223,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2223 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 23" base ad:0xB488AC00 width 14. if (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488AC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488AC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488AC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB488AC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB488AC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB488AC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 24" base ad:0xB4780000 width 14. if (((per.w(ad:0xB4780000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4780000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4780000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4780000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4780000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4780000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4780000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4780000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4780000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4780000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4780000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4780000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4780000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4780000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4780000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL2425,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2425 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.l(ad:0xB4780000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" newline bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" newline bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" newline bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" newline bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" elif cpuis("S6J33*") if (((per.l(ad:0xB4780000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" else endif width 0x0B tree.end else tree "Channel 24" base ad:0xB4846000 width 14. if (((per.w(ad:0xB4846000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL2425,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2425 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.l(ad:0xB4846000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" newline bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" newline bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" newline bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" newline bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" elif cpuis("S6J33*") if (((per.l(ad:0xB4846000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " SSSR[10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " SSSR[9] ,Simultaneous soft start bit 9" "No effect,Started" newline bitfld.long 0x00 8. " SSSR[8] ,Simultaneous soft start bit 8" "No effect,Started" bitfld.long 0x00 7. " SSSR[7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " SSSR[6] ,Simultaneous soft start bit 6" "No effect,Started" newline bitfld.long 0x00 5. " SSSR[5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " SSSR[4] ,Simultaneous soft start bit 4" "No effect,Started" bitfld.long 0x00 3. " SSSR[3] ,Simultaneous soft start bit 3" "No effect,Started" newline bitfld.long 0x00 2. " SSSR[2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " SSSR[1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " SSSR[0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " TRR[10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " TRR[9] ,Simultaneous TOUT read bit 9" "0,1" newline bitfld.long 0x00 8. " TRR[8] ,Simultaneous TOUT read bit 8" "0,1" bitfld.long 0x00 7. " TRR[7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " TRR[6] ,Simultaneous TOUT read bit 6" "0,1" newline bitfld.long 0x00 5. " TRR[5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " TRR[4] ,Simultaneous TOUT read bit 4" "0,1" bitfld.long 0x00 3. " TRR[3] ,Simultaneous TOUT read bit 3" "0,1" newline bitfld.long 0x00 2. " TRR[2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " TRR[1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " TRR[0] ,Simultaneous TOUT read bit 0" "0,1" else endif width 0x0B tree.end endif tree "Channel 25" base ad:0xB4846400 width 14. if (((per.w(ad:0xB4846400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 26" base ad:0xB4846800 width 14. if (((per.w(ad:0xB4846800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL2627,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2627 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 27" base ad:0xB4846C00 width 14. if (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4846C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4846C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4846C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 28" base ad:0xB4847000 width 14. if (((per.w(ad:0xB4847000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL2829,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2829 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 29" base ad:0xB4847400 width 14. if (((per.w(ad:0xB4847400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 30" base ad:0xB4847800 width 14. if (((per.w(ad:0xB4847800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x30++0x03 line.long 0x00 "BTSEL3031,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3031 ,I/O mode selection bits" "16-bit timer standard,32-bit timer full-function,PPG trigger 2-channel sharing,,Timer start/stop,Simultaneous soft start,Start/stop and simultaneous soft start,Timer start,?..." else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 31" base ad:0xB4847C00 width 14. if (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4847C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4847C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4847C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end sif (cpuis("S6J335*")) tree "Channel 32" base ad:0xB4848000 width 14. if (((per.w(ad:0xB4848000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 33" base ad:0xB4848400 width 14. if (((per.w(ad:0xB4848400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 34" base ad:0xB4848800 width 14. if (((per.w(ad:0xB4848800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 35" base ad:0xB4848C00 width 14. if (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4848C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4848C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4848C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 36" base ad:0xB4849000 width 14. if (((per.w(ad:0xB4849000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 37" base ad:0xB4849400 width 14. if (((per.w(ad:0xB4849400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 38" base ad:0xB4849800 width 14. if (((per.w(ad:0xB4849800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 39" base ad:0xB4849C00 width 14. if (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849C00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB4849C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB4849C00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB4849C00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 40" base ad:0xB484A000 width 14. if (((per.w(ad:0xB484A000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484A000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484A000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484A000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484A000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 41" base ad:0xB484A400 width 14. if (((per.w(ad:0xB484A400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484A400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484A400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484A400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484A400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 42" base ad:0xB484A800 width 14. if (((per.w(ad:0xB484A800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484A800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484A800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484A800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484A800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484A800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 43" base ad:0xB484AC00 width 14. if (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484AC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484AC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484AC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484AC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484AC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484AC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 44" base ad:0xB484B000 width 14. if (((per.w(ad:0xB484B000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484B000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484B000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484B000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484B000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 45" base ad:0xB484B400 width 14. if (((per.w(ad:0xB484B400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484B400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484B400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484B400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484B400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 46" base ad:0xB484B800 width 14. if (((per.w(ad:0xB484B800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484B800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484B800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484B800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484B800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484B800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 47" base ad:0xB484BC00 width 14. if (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484BC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484BC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484BC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484BC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484BC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484BC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 48" base ad:0xB484C000 width 14. if (((per.w(ad:0xB484C000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484C000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484C000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484C000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484C000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 49" base ad:0xB484C400 width 14. if (((per.w(ad:0xB484C400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484C400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484C400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484C400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484C400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 50" base ad:0xB484C800 width 14. if (((per.w(ad:0xB484C800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484C800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484C800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484C800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484C800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484C800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 51" base ad:0xB484CC00 width 14. if (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484CC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484CC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484CC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484CC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484CC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484CC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 52" base ad:0xB484D000 width 14. if (((per.w(ad:0xB484D000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484D000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484D000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484D000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484D000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 53" base ad:0xB484D400 width 14. if (((per.w(ad:0xB484D400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484D400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484D400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484D400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484D400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 54" base ad:0xB484D800 width 14. if (((per.w(ad:0xB484D800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484D800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484D800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484D800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484D800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484D800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 55" base ad:0xB484DC00 width 14. if (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484DC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484DC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484DC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484DC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484DC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484DC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 56" base ad:0xB484E000 width 14. if (((per.w(ad:0xB484E000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484E000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484E000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484E000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484E000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 57" base ad:0xB484E400 width 14. if (((per.w(ad:0xB484E400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484E400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484E400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484E400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484E400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 58" base ad:0xB484E800 width 14. if (((per.w(ad:0xB484E800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484E800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484E800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484E800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484E800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484E800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 59" base ad:0xB484EC00 width 14. if (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484EC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484EC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484EC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484EC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484EC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484EC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 60" base ad:0xB484F000 width 14. if (((per.w(ad:0xB484F000+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484F000+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484F000+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484F000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484F000+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F000+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484F000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F000+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484F000+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484F000+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 61" base ad:0xB484F400 width 14. if (((per.w(ad:0xB484F400+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484F400+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484F400+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484F400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484F400+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F400+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484F400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F400+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484F400+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484F400+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 62" base ad:0xB484F800 width 14. if (((per.w(ad:0xB484F800+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") endif elif (((per.w(ad:0xB484F800+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484F800+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484F800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484F800+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F800+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484F800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484F800+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484F800+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484F800+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end tree "Channel 63" base ad:0xB484FC00 width 14. if (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request" "No interrupt,Interrupt" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request" "No interrupt,Interrupt" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "BDEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif cpuis("S6J33*") group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" endif elif (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" newline bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" newline bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,Cycle Setting Register" group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" newline newline if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484FC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484FC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484FC00+0x11))&0x80)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00)&&(((per.b(ad:0xB484FC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif elif (((per.b(ad:0xB484FC00+0x11))&0x01)==0x01)&&(((per.b(ad:0xB484FC00+0x11))&0x80)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" sif cpuis("s6j336*")||cpuis("s6j337*") bitfld.word 0x00 0. " STRG ,Software trigger" ",Enabled" else bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif endif group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt" newline rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" else group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear" endif sif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" endif elif (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x40) sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in else rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" endif newline newline newline if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "Cleared,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt" line.byte 0x01 "TMCR2,Timer Control Register 2" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "0,1" sif cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear" endif else newline newline newline newline newline group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..." endif newline sif cpuis("s6j336*")||cpuis("s6j337*") else endif newline sif cpuis("s6j336*")||cpuis("s6j337*") elif cpuis("S6J33*") else endif width 0x0B tree.end endif tree.end tree "GT (Global Timer)" base ad:0xB488B000 width 8. group.long 0x00++0x0B line.long 0x00 "CPCLR,Compare Clear Register" hexmask.long.word 0x00 0.--15. 1. " CL ,Compare clear value bits" line.long 0x04 "TCDT,Timer Data Register" hexmask.long.word 0x04 0.--15. 1. " T ,Global timer data value bits" line.long 0x08 "TCCS,Timer State Control Register" bitfld.long 0x08 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" rbitfld.long 0x08 9. " ICLR ,Compare clear interrupt flag bit" "No interrupt,Interrupt" setclrfld.long 0x08 8. 0x0C 8. 0x08 8. " ICRE_SET/CLR ,Compare clear interrupt request enable bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x0C 6. 0x08 6. " STOP_SET/CLR ,Timer enable bit" "No,Yes" newline bitfld.long 0x08 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,?..." group.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 9. " ICLRC ,CLR clear bit" "No effect,Clear" group.long 0x18++0x03 line.long 0x00 "DEBUG,Timer State Control Clear Register" bitfld.long 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "MSCTR,Global Timer Match Starting Control Register" bitfld.long 0x00 2. " TREN ,Transfer request enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " MODE ,Mode select bit" "Disabled,Enabled" bitfld.long 0x00 0. " GTMOE ,Global timer match output enable bit" "Disabled,Enabled" hgroup.long 0x24++0x03 hide.long 0x00 "MSCHB0,Global Timer Match Starting Channel 0 Buffer Register" in hgroup.long 0x28++0x03 hide.long 0x00 "MSCHB1,Global Timer Match Starting Channel 1 Buffer Register" in sif cpuis("S6J342*") rgroup.long 0x2C++0x07 line.long 0x00 "MSCH0,Global Timer Match Starting Channel 0 Register" line.long 0x04 "MSCH1,Global Timer Match Starting Channel 1 Register" else group.long 0x2C++0x07 line.long 0x00 "MSCH0,Global Timer Match Starting Channel 0 Register" line.long 0x04 "MSCH1,Global Timer Match Starting Channel 1 Register" endif width 0x0B tree.end tree "FRT (Free-Run Timer)" sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "FRT00" base ad:0xB4820000 width 8. if (((per.l(ad:0xB4820000+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820000+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820000+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820000+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820000+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT01" base ad:0xB4820400 width 8. if (((per.l(ad:0xB4820400+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820400+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820400+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820400+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820400+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT02" base ad:0xB4820800 width 8. if (((per.l(ad:0xB4820800+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820800+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820800+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820800+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820800+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT03" base ad:0xB4820C00 width 8. if (((per.l(ad:0xB4820C00+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820C00+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820C00+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820C00+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820C00+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT04" base ad:0xB4821000 width 8. if (((per.l(ad:0xB4821000+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4821000+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4821000+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4821000+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4821000+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT08" base ad:0xB48A0000 width 8. if (((per.l(ad:0xB48A0000+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB48A0000+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB48A0000+0x08))&0x20)==0x20)&&(((per.l(ad:0xB48A0000+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB48A0000+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT09" base ad:0xB48A0400 width 8. if (((per.l(ad:0xB48A0400+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB48A0400+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB48A0400+0x08))&0x20)==0x20)&&(((per.l(ad:0xB48A0400+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB48A0400+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT10" base ad:0xB48A0800 width 8. if (((per.l(ad:0xB48A0800+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB48A0800+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB48A0800+0x08))&0x20)==0x20)&&(((per.l(ad:0xB48A0800+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB48A0800+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end else tree "FRT00" base ad:0xB4820000 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB4820000+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB4820000+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT01" base ad:0xB4820400 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB4820400+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB4820400+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT02" base ad:0xB4820800 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB4820800+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB4820800+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT03" base ad:0xB4820C00 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB4820C00+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB4820C00+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT04" base ad:0xB4821000 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB4821000+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB4821000+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT08" base ad:0xB48A0000 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB48A0000+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB48A0000+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT09" base ad:0xB48A0400 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB48A0400+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB48A0400+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end tree "FRT10" base ad:0xB48A0800 width 10. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") hgroup.word 0x00++0x01 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x02++0x01 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else if (((per.l(ad:0xB48A0800+0x08))&0x80)==0x80) wgroup.word 0x0++0x1 line.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" wgroup.word 0x2++0x1 line.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" else hgroup.word 0x0++0x1 hide.word 0x00 "CPCLRB_0,Compare Clear Buffer Register" hgroup.word 0x2++0x1 hide.word 0x00 "CPCLRB_1,Compare Clear Buffer Register" endif rgroup.word 0x0++0x1 line.word 0x00 "CPCLR_0,Compare Clear Register" rgroup.word 0x2++0x1 line.word 0x00 "CPCLR_1,Compare Clear Register" endif group.word 0x4++0x1 line.word 0x00 "TCDT_0,Timer Data Register" group.word 0x6++0x1 line.word 0x00 "TCDT_1,Timer Data Register" group.long 0x8++0x3 line.long 0x00 "TCCS,Timer State Control Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " ECKE_set/clr ,Clock selection bit" "Peripheral,External" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 14. 0x00 14. 0x08 14. " IRQZF_set/clr ,0 detection interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" else setclrfld.long 0x00 9. 0x00 9. 0x08 9. " ICLR_set/clr ,Compare clear interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count" textline " " sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100ns|200ns|400ns,clock/2|50ns|100ns|200ns|400ns|800ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|200ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." else setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,?..." endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") textline " " if (((per.l(ad:0xB48A0800+0x08))&0x20)==0x20) group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif else group.long 0xC++0x3 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid," bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") wgroup.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 14. " IRQZFC ,IRQZF Clear Bit" "No effect,Clear" bitfld.long 0x00 9. " ICLRC ,ICLR Clear Bit" "No effect,Clear" wgroup.long 0x14++0x3 line.long 0x00 "TCCSS,Timer State Control Set Register" bitfld.long 0x00 4. " SCLRS ,SCLR Set Bit" "No effect,Set" endif width 0x0B tree.end endif tree.end tree "ICU (32-BIT INPUT CAPTURE)" tree "ICU00" base ad:0xB4828000 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU01" base ad:0xB4828400 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU02" base ad:0xB4828800 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "ICU03" base ad:0xB4828C00 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU04" base ad:0xB4829000 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU05" base ad:0xB4829400 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU06" base ad:0xB4829800 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU07" base ad:0xB4829C00 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end endif tree "ICU08" base ad:0xB48A8000 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU09" base ad:0xB48A8400 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU10" base ad:0xB48A8800 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "ICU11" base ad:0xB48A8C00 width 9. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x07 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" else group.long 0x0++0x7 line.long 0x00 "IPCP0,Input Capture Data Register 0" line.long 0x04 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end endif tree.end tree "OCU (32-BIT OUTPUT COMPARE)" tree "OCU00" base ad:0xB4830000 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU01" base ad:0xB4830400 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU02" base ad:0xB4830800 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "OCU03" base ad:0xB4830C00 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU04" base ad:0xB4831000 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU05" base ad:0xB4831400 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU06" base ad:0xB4831800 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU07" base ad:0xB4831C00 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end endif tree "OCU08" base ad:0xB48B0000 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU09" base ad:0xB48B0400 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "OCU10" base ad:0xB48B0800 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "OCU11" base ad:0xB48B0C00 width 10. sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" in else hgroup.long 0x00++0x03 hide.long 0x00 "OCCPB0,Output Compare Buffer Register 0" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x00++0x03 line.long 0x00 "OCCP0,Output Compare Register 0" endif sif cpuis("s6j336*")||cpuis("s6j337*") hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" in else hgroup.long 0x04++0x03 hide.long 0x00 "OCCPB1,Output Compare Buffer Register 1" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("s6j336*")||cpuis("s6j337*") rgroup.long 0x04++0x03 line.long 0x00 "OCCP1,Output Compare Register 1" endif group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" newline bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" width 0x0B tree.end endif tree.end tree "32-bit Reload Timer" tree "Channel 0" base ad:0xB4810000 width 15. group.long 0x00++0x03 line.long 0x00 "RLT0_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4810000+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4810000+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT0_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT0_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT0_TMR,32-Bit Timer Register" width 0x0B tree.end tree "Channel 1" base ad:0xB4810400 width 15. group.long 0x00++0x03 line.long 0x00 "RLT1_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4810400+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4810400+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT1_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT1_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT1_TMR,32-Bit Timer Register" width 0x0B tree.end sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "Channel 2" base ad:0xB4810800 width 15. group.long 0x00++0x03 line.long 0x00 "RLT2_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4810800+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4810800+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT2_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT2_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT2_TMR,32-Bit Timer Register" width 0x0B tree.end tree "Channel 3" base ad:0xB4810C00 width 15. group.long 0x00++0x03 line.long 0x00 "RLT3_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4810C00+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4810C00+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT3_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT3_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT3_TMR,32-Bit Timer Register" width 0x0B tree.end endif tree "Channel 16" base ad:0xB4890000 width 15. group.long 0x00++0x03 line.long 0x00 "RLT16_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4890000+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4890000+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT16_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT16_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT16_TMR,32-Bit Timer Register" width 0x0B tree.end tree "Channel 17" base ad:0xB4890400 width 15. group.long 0x00++0x03 line.long 0x00 "RLT17_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB4890400+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB4890400+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT17_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT17_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT17_TMR,32-Bit Timer Register" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "Channel 48" base ad:0xB0690000 width 15. group.long 0x00++0x03 line.long 0x00 "RLT48_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB0690000+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690000+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690000+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690000+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690000+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690000+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690000+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB0690000+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT48_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT48_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT48_TMR,32-Bit Timer Register" width 0x0B tree.end tree "Channel 49" base ad:0xB0690400 width 15. group.long 0x00++0x03 line.long 0x00 "RLT49_DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" sif (cpuis("S6J33*")) if (((per.l(ad:0xB0690400+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690400+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690400+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690400+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690400+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690400+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB0690400+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" newline bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" newline bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif else if (((per.l(ad:0xB0690400+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "RLT49_TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" newline sif !cpuis("S6J312?HAA") bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" newline endif bitfld.long 0x00 5. " OUTL ,Output level" "0,1" bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "RLT49_TMRLR,32-Bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "RLT49_TMR,32-Bit Timer Register" width 0x0B tree.end endif tree.end tree "RTSSS (Reload Timer Simultaneous Soft Start)" tree "RLT0" base ad:0xB483FC00 width 6. sif cpuis("S6J336*")||cpuis("S6J337*") group.long 0x00++0x03 line.long 0x00 "TSEL,Reload Timer Trigger Selection Register" bitfld.long 0x00 3. " TSEL_[3] ,Trigger selection bit 3 (Channel 3)" "External,Software" bitfld.long 0x00 2. " [2] ,Trigger selection bit 2 (Channel 2)" "External,Software" bitfld.long 0x00 1. " [1] ,Trigger selection bit 1 (Channel 1)" "External,Software" bitfld.long 0x00 0. " [0] ,Trigger selection bit 0 (Channel 0)" "External,Software" else group.long 0x00++0x03 line.long 0x00 "TSEL,Reload Timer Trigger Selection Register" bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software" bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software" bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software" bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software" newline bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software" bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software" bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software" bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software" newline bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software" bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software" bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software" bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software" newline bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software" bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software" bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software" bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software" endif sif cpuis("S6J336*")||cpuis("S6J337*") group.long 0x04++0x03 line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register" bitfld.long 0x00 3. " SSSR_[3] ,Simultaneous soft start bit 3 (Channel 3)" "Not active,Active" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2 (Channel 2)" "Not active,Active" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1 (Channel 1)" "Not active,Active" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0 (Channel 0)" "Not active,Active" else group.long 0x04++0x03 line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register" bitfld.long 0x00 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active" bitfld.long 0x00 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active" bitfld.long 0x00 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active" bitfld.long 0x00 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active" newline bitfld.long 0x00 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active" endif width 0x0B tree.end tree "RLT1" base ad:0xB48BFC00 width 6. sif cpuis("S6J336*")||cpuis("S6J337*") group.long 0x00++0x03 line.long 0x00 "TSEL,Reload Timer Trigger Selection Register" bitfld.long 0x00 1. " TSEL_[1] ,Trigger selection bit 1 (Channel 17)" "External,Software" bitfld.long 0x00 0. " [0] ,Trigger selection bit 0 (Channel 16)" "External,Software" else group.long 0x00++0x03 line.long 0x00 "TSEL,Reload Timer Trigger Selection Register" bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software" bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software" bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software" bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software" newline bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software" bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software" bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software" bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software" newline bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software" bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software" bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software" bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software" newline bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software" bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software" bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software" bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software" endif sif cpuis("S6J336*")||cpuis("S6J337*") group.long 0x04++0x03 line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register" bitfld.long 0x00 1. " SSSR_[1] ,Simultaneous soft start bit 1 (Channel 17)" "Not active,Active" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0 (Channel 16)" "Not active,Active" else group.long 0x04++0x03 line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register" bitfld.long 0x00 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active" bitfld.long 0x00 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active" bitfld.long 0x00 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active" bitfld.long 0x00 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active" newline bitfld.long 0x00 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active" endif width 0x0B tree.end tree.end tree "QPRC (Quad Position & Revolution Counter)" tree "Channel 8" base ad:0xB4898000 width 12. group.word 0x00++0x07 line.word 0x00 "QC08_QPCR,QPRC Position Count Register" line.word 0x02 "QC08_QRCR,QPRC Revolution Count Register" line.word 0x04 "QC08_QPCCR,QPRC Position Counter Compare Register" line.word 0x06 "QC08_QPRCR,QPRC Position And Revolution Counter Compare Register" sif cpuis("S6J336*")||cpuis("S6J337*") if ((per.w(ad:0xB4898000+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898000+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QC08_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898000+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898000+0x0C)&0x0C)==(0x04||0x08)) group.word 0x0C++0x01 line.word 0x00 "QC08_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898000+0x0C)&0x20)==0x00)&&((per.w(ad:0xB4898000+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QC08_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" else group.word 0x0C++0x01 line.word 0x00 "QC08_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" endif else if ((per.w(ad:0xB4898000+0x0C)&0x20)==0x20) group.word 0x0C++0x01 line.word 0x00 "QC08_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3" else group.word 0x0C++0x01 line.word 0x00 "QC08_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3" endif endif group.word 0x0E++0x01 line.word 0x00 "QC08_QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" group.byte 0x0A++0x01 line.byte 0x00 "QC08_QICRL,Low-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected" bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected" bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " OUZIE ,Overflow/Underflow/Zero index interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched" bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not compared,Compared" bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" line.byte 0x01 "QC08_QICRH,High-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x01 5. " QPCNRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched" bitfld.byte 0x01 4. " QPCNRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.byte 0x01 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" newline rbitfld.byte 0x01 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" else bitfld.byte 0x01 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" newline bitfld.byte 0x01 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" endif bitfld.byte 0x01 1. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted" bitfld.byte 0x01 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" group.word 0x08++0x01 line.word 0x00 "QC08_QMPR,QPRC Maximum Position Register" width 0x0B tree.end tree "Channel 9" base ad:0xB4898400 width 12. group.word 0x00++0x07 line.word 0x00 "QC09_QPCR,QPRC Position Count Register" line.word 0x02 "QC09_QRCR,QPRC Revolution Count Register" line.word 0x04 "QC09_QPCCR,QPRC Position Counter Compare Register" line.word 0x06 "QC09_QPRCR,QPRC Position And Revolution Counter Compare Register" sif cpuis("S6J336*")||cpuis("S6J337*") if ((per.w(ad:0xB4898400+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898400+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QC09_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898400+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898400+0x0C)&0x0C)==(0x04||0x08)) group.word 0x0C++0x01 line.word 0x00 "QC09_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898400+0x0C)&0x20)==0x00)&&((per.w(ad:0xB4898400+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QC09_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" else group.word 0x0C++0x01 line.word 0x00 "QC09_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" endif else if ((per.w(ad:0xB4898400+0x0C)&0x20)==0x20) group.word 0x0C++0x01 line.word 0x00 "QC09_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3" else group.word 0x0C++0x01 line.word 0x00 "QC09_QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3" endif endif group.word 0x0E++0x01 line.word 0x00 "QC09_QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" group.byte 0x0A++0x01 line.byte 0x00 "QC09_QICRL,Low-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected" bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected" bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " OUZIE ,Overflow/Underflow/Zero index interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched" bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not compared,Compared" bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" line.byte 0x01 "QC09_QICRH,High-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x01 5. " QPCNRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched" bitfld.byte 0x01 4. " QPCNRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") rbitfld.byte 0x01 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" newline rbitfld.byte 0x01 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" else bitfld.byte 0x01 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" newline bitfld.byte 0x01 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" endif bitfld.byte 0x01 1. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted" bitfld.byte 0x01 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" group.word 0x08++0x01 line.word 0x00 "QC09_QMPR,QPRC Maximum Position Register" width 0x0B tree.end tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "EICU (External Interrupt Capture)" base ad:0xB0688000 width 13. group.long 0x00++0x27 line.long 0x00 "EICU0_CNFGR,Configuration Register" bitfld.long 0x00 26. " IRQEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " OBSEN ,Observation enable" "Disabled,Enabled" bitfld.long 0x00 24. " DATARESET ,Data Reset" "No effect,Reset" rbitfld.long 0x00 23. " DATAVALID ,Data valid" "Not valid,Valid" newline rbitfld.long 0x00 22. " BUSY ,Sampling status" "Not ongoing,Ongoing" rbitfld.long 0x00 16.--20. " OBSCH ,Observed channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--7. " PRESCALE ,Prescale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. " CLKSEL ,Clock select" "Slow RC,Fast RC,Main,Sub" line.long 0x04 "EICU0_IRENR,External Interrupt Pin Enable Register" sif (!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("S6J335*")) bitfld.long 0x04 31. " IREN_[31] ,External interrupt pin observe enable 31" "Disabled,Enabled" bitfld.long 0x04 30. " [30] ,External interrupt pin observe enable 30" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,External interrupt pin observe enable 29" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,External interrupt pin observe enable 28" "Disabled,Enabled" newline bitfld.long 0x04 27. " [27] ,External interrupt pin observe enable 27" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,External interrupt pin observe enable 26" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,External interrupt pin observe enable 25" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,External interrupt pin observe enable 24" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,External interrupt pin observe enable 23" "Disabled,Enabled" else bitfld.long 0x04 23. " IREN_[23] ,External interrupt pin observe enable 23" "Disabled,Enabled" endif bitfld.long 0x04 22. " [22] ,External interrupt pin observe enable 22" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,External interrupt pin observe enable 21" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,External interrupt pin observe enable 20" "Disabled,Enabled" newline bitfld.long 0x04 19. " [19] ,External interrupt pin observe enable 19" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,External interrupt pin observe enable 18" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,External interrupt pin observe enable 17" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,External interrupt pin observe enable 16" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,External interrupt pin observe enable 15" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,External interrupt pin observe enable 14" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,External interrupt pin observe enable 13" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,External interrupt pin observe enable 12" "Disabled,Enabled" newline bitfld.long 0x04 11. " [11] ,External interrupt pin observe enable 11" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,External interrupt pin observe enable 10" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,External interrupt pin observe enable 9" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,External interrupt pin observe enable 8" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,External interrupt pin observe enable 7" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,External interrupt pin observe enable 6" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,External interrupt pin observe enable 5" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,External interrupt pin observe enable 4" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,External interrupt pin observe enable 3" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,External interrupt pin observe enable 2" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,External interrupt pin observe enable 1" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,External interrupt pin observe enable 0" "Disabled,Enabled" line.long 0x08 "EICU0_SPLR0,Sample Register" bitfld.long 0x08 31. " SPL_[31] ,Sample bit 31" "Not occurred,Occurred" bitfld.long 0x08 30. " [30] ,Sample bit 30" "Not occurred,Occurred" bitfld.long 0x08 29. " [29] ,Sample bit 29" "Not occurred,Occurred" bitfld.long 0x08 28. " [28] ,Sample bit 28" "Not occurred,Occurred" newline bitfld.long 0x08 27. " [27] ,Sample bit 27" "Not occurred,Occurred" bitfld.long 0x08 26. " [26] ,Sample bit 26" "Not occurred,Occurred" bitfld.long 0x08 25. " [25] ,Sample bit 25" "Not occurred,Occurred" bitfld.long 0x08 24. " [24] ,Sample bit 24" "Not occurred,Occurred" newline bitfld.long 0x08 23. " [23] ,Sample bit 23" "Not occurred,Occurred" bitfld.long 0x08 22. " [22] ,Sample bit 22" "Not occurred,Occurred" bitfld.long 0x08 21. " [21] ,Sample bit 21" "Not occurred,Occurred" bitfld.long 0x08 20. " [20] ,Sample bit 20" "Not occurred,Occurred" newline bitfld.long 0x08 19. " [19] ,Sample bit 19" "Not occurred,Occurred" bitfld.long 0x08 18. " [18] ,Sample bit 18" "Not occurred,Occurred" bitfld.long 0x08 17. " [17] ,Sample bit 17" "Not occurred,Occurred" bitfld.long 0x08 16. " [16] ,Sample bit 16" "Not occurred,Occurred" newline bitfld.long 0x08 15. " [15] ,Sample bit 15" "Not occurred,Occurred" bitfld.long 0x08 14. " [14] ,Sample bit 14" "Not occurred,Occurred" bitfld.long 0x08 13. " [13] ,Sample bit 13" "Not occurred,Occurred" bitfld.long 0x08 12. " [12] ,Sample bit 12" "Not occurred,Occurred" newline bitfld.long 0x08 11. " [11] ,Sample bit 11" "Not occurred,Occurred" bitfld.long 0x08 10. " [10] ,Sample bit 10" "Not occurred,Occurred" bitfld.long 0x08 9. " [9] ,Sample bit 9" "Not occurred,Occurred" bitfld.long 0x08 8. " [8] ,Sample bit 8" "Not occurred,Occurred" newline bitfld.long 0x08 7. " [7] ,Sample bit 7" "Not occurred,Occurred" bitfld.long 0x08 6. " [6] ,Sample bit 6" "Not occurred,Occurred" bitfld.long 0x08 5. " [5] ,Sample bit 5" "Not occurred,Occurred" bitfld.long 0x08 4. " [4] ,Sample bit 4" "Not occurred,Occurred" newline bitfld.long 0x08 3. " [3] ,Sample bit 3" "Not occurred,Occurred" bitfld.long 0x08 2. " [2] ,Sample bit 2" "Not occurred,Occurred" bitfld.long 0x08 1. " [1] ,Sample bit 1" "Not occurred,Occurred" bitfld.long 0x08 0. " [0] ,Sample bit 0" "Not occurred,Occurred" line.long 0x0C "EICU0_SPLR1,Sample Register" bitfld.long 0x0C 31. " SPL_[63] ,Sample bit 63" "Not occurred,Occurred" bitfld.long 0x0C 30. " [62] ,Sample bit 62" "Not occurred,Occurred" bitfld.long 0x0C 29. " [61] ,Sample bit 61" "Not occurred,Occurred" bitfld.long 0x0C 28. " [60] ,Sample bit 60" "Not occurred,Occurred" newline bitfld.long 0x0C 27. " [59] ,Sample bit 59" "Not occurred,Occurred" bitfld.long 0x0C 26. " [58] ,Sample bit 58" "Not occurred,Occurred" bitfld.long 0x0C 25. " [57] ,Sample bit 57" "Not occurred,Occurred" bitfld.long 0x0C 24. " [56] ,Sample bit 56" "Not occurred,Occurred" newline bitfld.long 0x0C 23. " [55] ,Sample bit 55" "Not occurred,Occurred" bitfld.long 0x0C 22. " [54] ,Sample bit 54" "Not occurred,Occurred" bitfld.long 0x0C 21. " [53] ,Sample bit 53" "Not occurred,Occurred" bitfld.long 0x0C 20. " [52] ,Sample bit 52" "Not occurred,Occurred" newline bitfld.long 0x0C 19. " [51] ,Sample bit 51" "Not occurred,Occurred" bitfld.long 0x0C 18. " [50] ,Sample bit 50" "Not occurred,Occurred" bitfld.long 0x0C 17. " [49] ,Sample bit 49" "Not occurred,Occurred" bitfld.long 0x0C 16. " [48] ,Sample bit 48" "Not occurred,Occurred" newline bitfld.long 0x0C 15. " [47] ,Sample bit 47" "Not occurred,Occurred" bitfld.long 0x0C 14. " [46] ,Sample bit 46" "Not occurred,Occurred" bitfld.long 0x0C 13. " [45] ,Sample bit 45" "Not occurred,Occurred" bitfld.long 0x0C 12. " [44] ,Sample bit 44" "Not occurred,Occurred" newline bitfld.long 0x0C 11. " [43] ,Sample bit 43" "Not occurred,Occurred" bitfld.long 0x0C 10. " [42] ,Sample bit 42" "Not occurred,Occurred" bitfld.long 0x0C 9. " [41] ,Sample bit 41" "Not occurred,Occurred" bitfld.long 0x0C 8. " [40] ,Sample bit 40" "Not occurred,Occurred" newline bitfld.long 0x0C 7. " [39] ,Sample bit 39" "Not occurred,Occurred" bitfld.long 0x0C 6. " [38] ,Sample bit 38" "Not occurred,Occurred" bitfld.long 0x0C 5. " [37] ,Sample bit 37" "Not occurred,Occurred" bitfld.long 0x0C 4. " [36] ,Sample bit 36" "Not occurred,Occurred" newline bitfld.long 0x0C 3. " [35] ,Sample bit 35" "Not occurred,Occurred" bitfld.long 0x0C 2. " [34] ,Sample bit 34" "Not occurred,Occurred" bitfld.long 0x0C 1. " [33] ,Sample bit 33" "Not occurred,Occurred" bitfld.long 0x0C 0. " [32] ,Sample bit 32" "Not occurred,Occurred" line.long 0x10 "EICU0_SPLR2,Sample Register" bitfld.long 0x10 31. " SPL_[95] ,Sample bit 95" "Not occurred,Occurred" bitfld.long 0x10 30. " [94] ,Sample bit 94" "Not occurred,Occurred" bitfld.long 0x10 29. " [93] ,Sample bit 93" "Not occurred,Occurred" bitfld.long 0x10 28. " [92] ,Sample bit 92" "Not occurred,Occurred" newline bitfld.long 0x10 27. " [91] ,Sample bit 91" "Not occurred,Occurred" bitfld.long 0x10 26. " [90] ,Sample bit 90" "Not occurred,Occurred" bitfld.long 0x10 25. " [89] ,Sample bit 89" "Not occurred,Occurred" bitfld.long 0x10 24. " [88] ,Sample bit 88" "Not occurred,Occurred" newline bitfld.long 0x10 23. " [87] ,Sample bit 87" "Not occurred,Occurred" bitfld.long 0x10 22. " [86] ,Sample bit 86" "Not occurred,Occurred" bitfld.long 0x10 21. " [85] ,Sample bit 85" "Not occurred,Occurred" bitfld.long 0x10 20. " [84] ,Sample bit 84" "Not occurred,Occurred" newline bitfld.long 0x10 19. " [83] ,Sample bit 83" "Not occurred,Occurred" bitfld.long 0x10 18. " [82] ,Sample bit 82" "Not occurred,Occurred" bitfld.long 0x10 17. " [81] ,Sample bit 81" "Not occurred,Occurred" bitfld.long 0x10 16. " [80] ,Sample bit 80" "Not occurred,Occurred" newline bitfld.long 0x10 15. " [79] ,Sample bit 79" "Not occurred,Occurred" bitfld.long 0x10 14. " [78] ,Sample bit 78" "Not occurred,Occurred" bitfld.long 0x10 13. " [77] ,Sample bit 77" "Not occurred,Occurred" bitfld.long 0x10 12. " [76] ,Sample bit 76" "Not occurred,Occurred" newline bitfld.long 0x10 11. " [75] ,Sample bit 75" "Not occurred,Occurred" bitfld.long 0x10 10. " [74] ,Sample bit 74" "Not occurred,Occurred" bitfld.long 0x10 9. " [73] ,Sample bit 73" "Not occurred,Occurred" bitfld.long 0x10 8. " [72] ,Sample bit 72" "Not occurred,Occurred" newline bitfld.long 0x10 7. " [71] ,Sample bit 71" "Not occurred,Occurred" bitfld.long 0x10 6. " [70] ,Sample bit 70" "Not occurred,Occurred" bitfld.long 0x10 5. " [69] ,Sample bit 69" "Not occurred,Occurred" bitfld.long 0x10 4. " [68] ,Sample bit 68" "Not occurred,Occurred" newline bitfld.long 0x10 3. " [67] ,Sample bit 67" "Not occurred,Occurred" bitfld.long 0x10 2. " [66] ,Sample bit 66" "Not occurred,Occurred" bitfld.long 0x10 1. " [65] ,Sample bit 65" "Not occurred,Occurred" bitfld.long 0x10 0. " [64] ,Sample bit 64" "Not occurred,Occurred" line.long 0x14 "EICU0_SPLR3,Sample Register" bitfld.long 0x14 31. " SPL_[127] ,Sample bit 127" "Not occurred,Occurred" bitfld.long 0x14 30. " [126] ,Sample bit 126" "Not occurred,Occurred" bitfld.long 0x14 29. " [125] ,Sample bit 125" "Not occurred,Occurred" bitfld.long 0x14 28. " [124] ,Sample bit 124" "Not occurred,Occurred" newline bitfld.long 0x14 27. " [123] ,Sample bit 123" "Not occurred,Occurred" bitfld.long 0x14 26. " [122] ,Sample bit 122" "Not occurred,Occurred" bitfld.long 0x14 25. " [121] ,Sample bit 121" "Not occurred,Occurred" bitfld.long 0x14 24. " [120] ,Sample bit 120" "Not occurred,Occurred" newline bitfld.long 0x14 23. " [119] ,Sample bit 119" "Not occurred,Occurred" bitfld.long 0x14 22. " [118] ,Sample bit 118" "Not occurred,Occurred" bitfld.long 0x14 21. " [117] ,Sample bit 117" "Not occurred,Occurred" bitfld.long 0x14 20. " [116] ,Sample bit 116" "Not occurred,Occurred" newline bitfld.long 0x14 19. " [115] ,Sample bit 115" "Not occurred,Occurred" bitfld.long 0x14 18. " [114] ,Sample bit 114" "Not occurred,Occurred" bitfld.long 0x14 17. " [113] ,Sample bit 113" "Not occurred,Occurred" bitfld.long 0x14 16. " [112] ,Sample bit 112" "Not occurred,Occurred" newline bitfld.long 0x14 15. " [111] ,Sample bit 111" "Not occurred,Occurred" bitfld.long 0x14 14. " [110] ,Sample bit 110" "Not occurred,Occurred" bitfld.long 0x14 13. " [109] ,Sample bit 109" "Not occurred,Occurred" bitfld.long 0x14 12. " [108] ,Sample bit 108" "Not occurred,Occurred" newline bitfld.long 0x14 11. " [107] ,Sample bit 107" "Not occurred,Occurred" bitfld.long 0x14 10. " [106] ,Sample bit 106" "Not occurred,Occurred" bitfld.long 0x14 9. " [105] ,Sample bit 105" "Not occurred,Occurred" bitfld.long 0x14 8. " [104] ,Sample bit 104" "Not occurred,Occurred" newline bitfld.long 0x14 7. " [103] ,Sample bit 103" "Not occurred,Occurred" bitfld.long 0x14 6. " [102] ,Sample bit 102" "Not occurred,Occurred" bitfld.long 0x14 5. " [101] ,Sample bit 101" "Not occurred,Occurred" bitfld.long 0x14 4. " [100] ,Sample bit 100" "Not occurred,Occurred" newline bitfld.long 0x14 3. " [99] ,Sample bit 99" "Not occurred,Occurred" bitfld.long 0x14 2. " [98] ,Sample bit 98" "Not occurred,Occurred" bitfld.long 0x14 1. " [97] ,Sample bit 97" "Not occurred,Occurred" bitfld.long 0x14 0. " [96] ,Sample bit 96" "Not occurred,Occurred" line.long 0x18 "EICU0_SPLR4,Sample Register" bitfld.long 0x18 31. " SPL_[159] ,Sample bit 159" "Not occurred,Occurred" bitfld.long 0x18 30. " [158] ,Sample bit 158" "Not occurred,Occurred" bitfld.long 0x18 29. " [157] ,Sample bit 157" "Not occurred,Occurred" bitfld.long 0x18 28. " [156] ,Sample bit 156" "Not occurred,Occurred" newline bitfld.long 0x18 27. " [155] ,Sample bit 155" "Not occurred,Occurred" bitfld.long 0x18 26. " [154] ,Sample bit 154" "Not occurred,Occurred" bitfld.long 0x18 25. " [153] ,Sample bit 153" "Not occurred,Occurred" bitfld.long 0x18 24. " [152] ,Sample bit 152" "Not occurred,Occurred" newline bitfld.long 0x18 23. " [151] ,Sample bit 151" "Not occurred,Occurred" bitfld.long 0x18 22. " [150] ,Sample bit 150" "Not occurred,Occurred" bitfld.long 0x18 21. " [149] ,Sample bit 149" "Not occurred,Occurred" bitfld.long 0x18 20. " [148] ,Sample bit 148" "Not occurred,Occurred" newline bitfld.long 0x18 19. " [147] ,Sample bit 147" "Not occurred,Occurred" bitfld.long 0x18 18. " [146] ,Sample bit 146" "Not occurred,Occurred" bitfld.long 0x18 17. " [145] ,Sample bit 145" "Not occurred,Occurred" bitfld.long 0x18 16. " [144] ,Sample bit 144" "Not occurred,Occurred" newline bitfld.long 0x18 15. " [143] ,Sample bit 143" "Not occurred,Occurred" bitfld.long 0x18 14. " [142] ,Sample bit 142" "Not occurred,Occurred" bitfld.long 0x18 13. " [141] ,Sample bit 141" "Not occurred,Occurred" bitfld.long 0x18 12. " [140] ,Sample bit 140" "Not occurred,Occurred" newline bitfld.long 0x18 11. " [139] ,Sample bit 139" "Not occurred,Occurred" bitfld.long 0x18 10. " [138] ,Sample bit 138" "Not occurred,Occurred" bitfld.long 0x18 9. " [137] ,Sample bit 137" "Not occurred,Occurred" bitfld.long 0x18 8. " [136] ,Sample bit 136" "Not occurred,Occurred" newline bitfld.long 0x18 7. " [135] ,Sample bit 135" "Not occurred,Occurred" bitfld.long 0x18 6. " [134] ,Sample bit 134" "Not occurred,Occurred" bitfld.long 0x18 5. " [133] ,Sample bit 133" "Not occurred,Occurred" bitfld.long 0x18 4. " [132] ,Sample bit 132" "Not occurred,Occurred" newline bitfld.long 0x18 3. " [131] ,Sample bit 131" "Not occurred,Occurred" bitfld.long 0x18 2. " [130] ,Sample bit 130" "Not occurred,Occurred" bitfld.long 0x18 1. " [129] ,Sample bit 129" "Not occurred,Occurred" bitfld.long 0x18 0. " [128] ,Sample bit 128" "Not occurred,Occurred" line.long 0x1C "EICU0_SPLR5,Sample Register" bitfld.long 0x1C 31. " SPL_[191] ,Sample bit 191" "Not occurred,Occurred" bitfld.long 0x1C 30. " [190] ,Sample bit 190" "Not occurred,Occurred" bitfld.long 0x1C 29. " [189] ,Sample bit 189" "Not occurred,Occurred" bitfld.long 0x1C 28. " [188] ,Sample bit 188" "Not occurred,Occurred" newline bitfld.long 0x1C 27. " [187] ,Sample bit 187" "Not occurred,Occurred" bitfld.long 0x1C 26. " [186] ,Sample bit 186" "Not occurred,Occurred" bitfld.long 0x1C 25. " [185] ,Sample bit 185" "Not occurred,Occurred" bitfld.long 0x1C 24. " [184] ,Sample bit 184" "Not occurred,Occurred" newline bitfld.long 0x1C 23. " [183] ,Sample bit 183" "Not occurred,Occurred" bitfld.long 0x1C 22. " [182] ,Sample bit 182" "Not occurred,Occurred" bitfld.long 0x1C 21. " [181] ,Sample bit 181" "Not occurred,Occurred" bitfld.long 0x1C 20. " [180] ,Sample bit 180" "Not occurred,Occurred" newline bitfld.long 0x1C 19. " [179] ,Sample bit 179" "Not occurred,Occurred" bitfld.long 0x1C 18. " [178] ,Sample bit 178" "Not occurred,Occurred" bitfld.long 0x1C 17. " [177] ,Sample bit 177" "Not occurred,Occurred" bitfld.long 0x1C 16. " [176] ,Sample bit 176" "Not occurred,Occurred" newline bitfld.long 0x1C 15. " [175] ,Sample bit 175" "Not occurred,Occurred" bitfld.long 0x1C 14. " [174] ,Sample bit 174" "Not occurred,Occurred" bitfld.long 0x1C 13. " [173] ,Sample bit 173" "Not occurred,Occurred" bitfld.long 0x1C 12. " [172] ,Sample bit 172" "Not occurred,Occurred" newline bitfld.long 0x1C 11. " [171] ,Sample bit 171" "Not occurred,Occurred" bitfld.long 0x1C 10. " [170] ,Sample bit 170" "Not occurred,Occurred" bitfld.long 0x1C 9. " [169] ,Sample bit 169" "Not occurred,Occurred" bitfld.long 0x1C 8. " [168] ,Sample bit 168" "Not occurred,Occurred" newline bitfld.long 0x1C 7. " [167] ,Sample bit 167" "Not occurred,Occurred" bitfld.long 0x1C 6. " [166] ,Sample bit 166" "Not occurred,Occurred" bitfld.long 0x1C 5. " [165] ,Sample bit 165" "Not occurred,Occurred" bitfld.long 0x1C 4. " [164] ,Sample bit 164" "Not occurred,Occurred" newline bitfld.long 0x1C 3. " [163] ,Sample bit 163" "Not occurred,Occurred" bitfld.long 0x1C 2. " [162] ,Sample bit 162" "Not occurred,Occurred" bitfld.long 0x1C 1. " [161] ,Sample bit 161" "Not occurred,Occurred" bitfld.long 0x1C 0. " [160] ,Sample bit 160" "Not occurred,Occurred" line.long 0x20 "EICU0_SPLR6,Sample Register" bitfld.long 0x20 31. " SPL_[223] ,Sample bit 223" "Not occurred,Occurred" bitfld.long 0x20 30. " [222] ,Sample bit 222" "Not occurred,Occurred" bitfld.long 0x20 29. " [221] ,Sample bit 221" "Not occurred,Occurred" bitfld.long 0x20 28. " [220] ,Sample bit 220" "Not occurred,Occurred" newline bitfld.long 0x20 27. " [219] ,Sample bit 219" "Not occurred,Occurred" bitfld.long 0x20 26. " [218] ,Sample bit 218" "Not occurred,Occurred" bitfld.long 0x20 25. " [217] ,Sample bit 217" "Not occurred,Occurred" bitfld.long 0x20 24. " [216] ,Sample bit 216" "Not occurred,Occurred" newline bitfld.long 0x20 23. " [215] ,Sample bit 215" "Not occurred,Occurred" bitfld.long 0x20 22. " [214] ,Sample bit 214" "Not occurred,Occurred" bitfld.long 0x20 21. " [213] ,Sample bit 213" "Not occurred,Occurred" bitfld.long 0x20 20. " [212] ,Sample bit 212" "Not occurred,Occurred" newline bitfld.long 0x20 19. " [211] ,Sample bit 211" "Not occurred,Occurred" bitfld.long 0x20 18. " [210] ,Sample bit 210" "Not occurred,Occurred" bitfld.long 0x20 17. " [209] ,Sample bit 209" "Not occurred,Occurred" bitfld.long 0x20 16. " [208] ,Sample bit 208" "Not occurred,Occurred" newline bitfld.long 0x20 15. " [207] ,Sample bit 207" "Not occurred,Occurred" bitfld.long 0x20 14. " [206] ,Sample bit 206" "Not occurred,Occurred" bitfld.long 0x20 13. " [205] ,Sample bit 205" "Not occurred,Occurred" bitfld.long 0x20 12. " [204] ,Sample bit 204" "Not occurred,Occurred" newline bitfld.long 0x20 11. " [203] ,Sample bit 203" "Not occurred,Occurred" bitfld.long 0x20 10. " [202] ,Sample bit 202" "Not occurred,Occurred" bitfld.long 0x20 9. " [201] ,Sample bit 201" "Not occurred,Occurred" bitfld.long 0x20 8. " [200] ,Sample bit 200" "Not occurred,Occurred" newline bitfld.long 0x20 7. " [199] ,Sample bit 199" "Not occurred,Occurred" bitfld.long 0x20 6. " [198] ,Sample bit 198" "Not occurred,Occurred" bitfld.long 0x20 5. " [197] ,Sample bit 197" "Not occurred,Occurred" bitfld.long 0x20 4. " [196] ,Sample bit 196" "Not occurred,Occurred" newline bitfld.long 0x20 3. " [195] ,Sample bit 195" "Not occurred,Occurred" bitfld.long 0x20 2. " [194] ,Sample bit 194" "Not occurred,Occurred" bitfld.long 0x20 1. " [193] ,Sample bit 193" "Not occurred,Occurred" bitfld.long 0x20 0. " [192] ,Sample bit 192" "Not occurred,Occurred" line.long 0x24 "EICU0_SPLR7,Sample Register" bitfld.long 0x24 31. " SPL_[255] ,Sample bit 255" "Not occurred,Occurred" bitfld.long 0x24 30. " [254] ,Sample bit 254" "Not occurred,Occurred" bitfld.long 0x24 29. " [253] ,Sample bit 253" "Not occurred,Occurred" bitfld.long 0x24 28. " [252] ,Sample bit 252" "Not occurred,Occurred" newline bitfld.long 0x24 27. " [251] ,Sample bit 251" "Not occurred,Occurred" bitfld.long 0x24 26. " [250] ,Sample bit 250" "Not occurred,Occurred" bitfld.long 0x24 25. " [249] ,Sample bit 249" "Not occurred,Occurred" bitfld.long 0x24 24. " [248] ,Sample bit 248" "Not occurred,Occurred" newline bitfld.long 0x24 23. " [247] ,Sample bit 247" "Not occurred,Occurred" bitfld.long 0x24 22. " [246] ,Sample bit 246" "Not occurred,Occurred" bitfld.long 0x24 21. " [245] ,Sample bit 245" "Not occurred,Occurred" bitfld.long 0x24 20. " [244] ,Sample bit 244" "Not occurred,Occurred" newline bitfld.long 0x24 19. " [243] ,Sample bit 243" "Not occurred,Occurred" bitfld.long 0x24 18. " [242] ,Sample bit 242" "Not occurred,Occurred" bitfld.long 0x24 17. " [241] ,Sample bit 241" "Not occurred,Occurred" bitfld.long 0x24 16. " [240] ,Sample bit 240" "Not occurred,Occurred" newline bitfld.long 0x24 15. " [239] ,Sample bit 239" "Not occurred,Occurred" bitfld.long 0x24 14. " [238] ,Sample bit 238" "Not occurred,Occurred" bitfld.long 0x24 13. " [237] ,Sample bit 237" "Not occurred,Occurred" bitfld.long 0x24 12. " [236] ,Sample bit 236" "Not occurred,Occurred" newline bitfld.long 0x24 11. " [235] ,Sample bit 235" "Not occurred,Occurred" bitfld.long 0x24 10. " [234] ,Sample bit 234" "Not occurred,Occurred" bitfld.long 0x24 9. " [233] ,Sample bit 233" "Not occurred,Occurred" bitfld.long 0x24 8. " [232] ,Sample bit 232" "Not occurred,Occurred" newline bitfld.long 0x24 7. " [231] ,Sample bit 231" "Not occurred,Occurred" bitfld.long 0x24 6. " [230] ,Sample bit 230" "Not occurred,Occurred" bitfld.long 0x24 5. " [229] ,Sample bit 229" "Not occurred,Occurred" bitfld.long 0x24 4. " [228] ,Sample bit 228" "Not occurred,Occurred" newline bitfld.long 0x24 3. " [227] ,Sample bit 227" "Not occurred,Occurred" bitfld.long 0x24 2. " [226] ,Sample bit 226" "Not occurred,Occurred" bitfld.long 0x24 1. " [225] ,Sample bit 225" "Not occurred,Occurred" bitfld.long 0x24 0. " [224] ,Sample bit 224" "Not occurred,Occurred" width 0x0B tree.end endif tree "CRC (Cyclic Redundancy Check)" tree "CRC 0" base ad:0xB4718000 width 15. group.byte 0x00++0x00 line.byte 0x00 "CRC00_CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0xB4718000))&0x2)==0x00) group.long 0x04++0x03 line.long 0x00 "CRC00_CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRC00_CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRC00_CRCIN,Input Data Register" if (((per.b(ad:0xB4718000))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRC00_CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0xB4718000))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRC00_CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRC00_CRCR,CRC Register" endif width 0x0B tree.end tree "CRC 1" base ad:0xB4718400 width 15. group.byte 0x00++0x00 line.byte 0x00 "CRC01_CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0XB4718400))&0x2)==0x00) group.long 0x04++0x03 line.long 0x00 "CRC01_CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRC01_CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRC01_CRCIN,Input Data Register" if (((per.b(ad:0XB4718400))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRC01_CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0XB4718400))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRC01_CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRC01_CRCR,CRC Register" endif width 0x0B tree.end tree "CRC 2" base ad:0xB4718800 width 15. group.byte 0x00++0x00 line.byte 0x00 "CRC02_CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0XB4718800))&0x2)==0x00) group.long 0x04++0x03 line.long 0x00 "CRC02_CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRC02_CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRC02_CRCIN,Input Data Register" if (((per.b(ad:0XB4718800))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRC02_CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0XB4718800))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRC02_CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRC02_CRCR,CRC Register" endif width 0x0B tree.end tree "CRC 3" base ad:0xB4718C00 width 15. group.byte 0x00++0x00 line.byte 0x00 "CRC03_CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0XB4718C00))&0x2)==0x00) group.long 0x04++0x03 line.long 0x00 "CRC03_CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRC03_CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRC03_CRCIN,Input Data Register" if (((per.b(ad:0XB4718C00))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRC03_CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0XB4718C00))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRC03_CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRC03_CRCR,CRC Register" endif width 0x0B tree.end tree.end tree.open "I/O PORT" tree "GPIO" base ad:0xB4738000 width 20. group.long 0x200++0x3 line.long 0x00 "GPIO_POR0_SET/CLR,Port Output Set/Clear Register 0" setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 09. -0x200 09. -0x1FC 09. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 08. -0x200 08. -0x1FC 08. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 07. -0x200 07. -0x1FC 07. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 06. -0x200 06. -0x1FC 06. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 05. -0x200 05. -0x1FC 05. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 04. -0x200 04. -0x1FC 04. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 03. -0x200 03. -0x1FC 03. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 02. -0x200 02. -0x1FC 02. " [2] ,Port output bit 2" "Low,High" newline setclrfld.long 0x00 01. -0x200 01. -0x1FC 01. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 00. -0x200 00. -0x1FC 00. " [0] ,Port output bit 0" "Low,High" group.long 0x208++0x3 line.long 0x00 "GPIO_POR1_SET/CLR,Port Output Set/Clear Register 1" setclrfld.long 0x00 31. -0x1F8 31. -0x1F4 31. " P1[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1F8 30. -0x1F4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1F8 29. -0x1F4 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F8 28. -0x1F4 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x1F8 27. -0x1F4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x1F8 25. -0x1F4 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F8 24. -0x1F4 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1F8 23. -0x1F4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F8 22. -0x1F4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1F8 21. -0x1F4 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1F8 20. -0x1F4 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1F8 19. -0x1F4 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1F8 18. -0x1F4 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1F8 17. -0x1F4 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1F8 16. -0x1F4 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x1F8 15. -0x1F4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F8 14. -0x1F4 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1F8 13. -0x1F4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1F8 12. -0x1F4 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1F8 11. -0x1F4 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1F8 10. -0x1F4 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 09. -0x1F8 09. -0x1F4 09. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 08. -0x1F8 08. -0x1F4 08. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 07. -0x1F8 07. -0x1F4 07. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 06. -0x1F8 06. -0x1F4 06. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 05. -0x1F8 05. -0x1F4 05. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 04. -0x1F8 04. -0x1F4 04. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 03. -0x1F8 03. -0x1F4 03. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 02. -0x1F8 02. -0x1F4 02. " [2] ,Port output bit 2" "Low,High" newline setclrfld.long 0x00 01. -0x1F8 01. -0x1F4 01. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 00. -0x1F8 00. -0x1F4 00. " [0] ,Port output bit 0" "Low,High" group.long 0x210++0x3 line.long 0x00 "GPIO_POR2_SET/CLR,Port Output Set/Clear Register 2" sif cpuis("S6J336?H?")||cpuis("S6J337?H?")||cpuis("S6J336?J?")||cpuis("S6J337?J?") setclrfld.long 0x00 29. -0x1F0 29. -0x1EC 29. " P2[29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F0 28. -0x1EC 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x1F0 27. -0x1EC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F0 26. -0x1EC 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x1F0 25. -0x1EC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F0 24. -0x1EC 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1F0 23. -0x1EC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F0 22. -0x1EC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1F0 21. -0x1EC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1F0 20. -0x1EC 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1F0 19. -0x1EC 19. " [19] ,Port output bit 19" "Low,High" else setclrfld.long 0x00 19. -0x1F0 19. -0x1EC 19. " P2[19] ,Port output bit 19" "Low,High" endif setclrfld.long 0x00 18. -0x1F0 18. -0x1EC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1F0 17. -0x1EC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1F0 16. -0x1EC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x1F0 15. -0x1EC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F0 14. -0x1EC 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1F0 13. -0x1EC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1F0 12. -0x1EC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1F0 11. -0x1EC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1F0 10. -0x1EC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 09. -0x1F0 09. -0x1EC 09. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 08. -0x1F0 08. -0x1EC 08. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 07. -0x1F0 07. -0x1EC 07. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 06. -0x1F0 06. -0x1EC 06. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 05. -0x1F0 05. -0x1EC 05. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 04. -0x1F0 04. -0x1EC 04. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 03. -0x1F0 03. -0x1EC 03. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 02. -0x1F0 02. -0x1EC 02. " [2] ,Port output bit 2" "Low,High" newline setclrfld.long 0x00 01. -0x1F0 01. -0x1EC 01. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 00. -0x1F0 00. -0x1EC 00. " [0] ,Port output bit 0" "Low,High" sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J336?H?")&&!cpuis("S6J337?H?")) group.long 0x218++0x3 line.long 0x00 "GPIO_POR3_SET/CLR,Port Output Set/Clear Register 3" setclrfld.long 0x00 31. -0x1E8 31. -0x1E4 31. " P3[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1E8 30. -0x1E4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1E8 29. -0x1E4 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1E8 28. -0x1E4 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x1E8 27. -0x1E4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1E8 26. -0x1E4 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x1E8 25. -0x1E4 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1E8 24. -0x1E4 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1E8 23. -0x1E4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1E8 22. -0x1E4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E8 21. -0x1E4 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1E8 20. -0x1E4 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1E8 19. -0x1E4 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1E8 18. -0x1E4 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1E8 17. -0x1E4 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1E8 16. -0x1E4 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x1E8 15. -0x1E4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1E8 14. -0x1E4 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1E8 13. -0x1E4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1E8 12. -0x1E4 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1E8 11. -0x1E4 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1E8 10. -0x1E4 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 09. -0x1E8 09. -0x1E4 09. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 08. -0x1E8 08. -0x1E4 08. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 07. -0x1E8 07. -0x1E4 07. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 06. -0x1E8 06. -0x1E4 06. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 05. -0x1E8 05. -0x1E4 05. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 04. -0x1E8 04. -0x1E4 04. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 03. -0x1E8 03. -0x1E4 03. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 02. -0x1E8 02. -0x1E4 02. " [2] ,Port output bit 2" "Low,High" newline setclrfld.long 0x00 01. -0x1E8 01. -0x1E4 01. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 00. -0x1E8 00. -0x1E4 00. " [0] ,Port output bit 0" "Low,High" sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")&&!cpuis("S6J336?J?")&&!cpuis("S6J337?J?")) group.long 0x220++0x3 line.long 0x00 "GPIO_POR4_SET/CLR,Port Output Set/Clear Register 4" setclrfld.long 0x00 31. -0x1E0 31. -0x1DC 31. " P4[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1E0 30. -0x1DC 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1E0 29. -0x1DC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1E0 28. -0x1DC 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x1E0 27. -0x1DC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1E0 26. -0x1DC 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x1E0 25. -0x1DC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1E0 24. -0x1DC 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1E0 23. -0x1DC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1E0 22. -0x1DC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E0 21. -0x1DC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1E0 20. -0x1DC 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1E0 19. -0x1DC 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1E0 18. -0x1DC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1E0 17. -0x1DC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1E0 16. -0x1DC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x1E0 15. -0x1DC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1E0 14. -0x1DC 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1E0 13. -0x1DC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1E0 12. -0x1DC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1E0 11. -0x1DC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1E0 10. -0x1DC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 09. -0x1E0 09. -0x1DC 09. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 08. -0x1E0 08. -0x1DC 08. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 07. -0x1E0 07. -0x1DC 07. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 06. -0x1E0 06. -0x1DC 06. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 05. -0x1E0 05. -0x1DC 05. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 04. -0x1E0 04. -0x1DC 04. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 03. -0x1E0 03. -0x1DC 03. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 02. -0x1E0 02. -0x1DC 02. " [2] ,Port output bit 2" "Low,High" newline setclrfld.long 0x00 01. -0x1E0 01. -0x1DC 01. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 00. -0x1E0 00. -0x1DC 00. " [0] ,Port output bit 0" "Low,High" endif endif newline group.long 0x204++0x3 line.long 0x00 "GPIO_DDR0_SET/CLR,Data Direction Set/Clear Register 0" setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 09. -0x1FC 09. -0x1F8 09. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 08. -0x1FC 08. -0x1F8 08. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 07. -0x1FC 07. -0x1F8 07. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 06. -0x1FC 06. -0x1F8 06. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 05. -0x1FC 05. -0x1F8 05. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 04. -0x1FC 04. -0x1F8 04. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 03. -0x1FC 03. -0x1F8 03. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 02. -0x1FC 02. -0x1F8 02. " [2] ,Data direction bit 2" "Input,Output" newline setclrfld.long 0x00 01. -0x1FC 01. -0x1F8 01. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 00. -0x1FC 00. -0x1F8 00. " [0] ,Data direction bit 0" "Input,Output" group.long 0x20C++0x3 line.long 0x00 "GPIO_DDR1_SET/CLR,Data Direction Set/Clear Register 1" setclrfld.long 0x00 31. -0x1F4 31. -0x1F0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1F4 30. -0x1F0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1F4 29. -0x1F0 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1F4 28. -0x1F0 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1F4 27. -0x1F0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1F4 25. -0x1F0 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1F4 24. -0x1F0 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1F4 23. -0x1F0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1F4 22. -0x1F0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1F4 21. -0x1F0 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1F4 20. -0x1F0 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1F4 19. -0x1F0 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1F4 18. -0x1F0 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1F4 17. -0x1F0 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1F4 16. -0x1F0 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1F4 15. -0x1F0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1F4 14. -0x1F0 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1F4 13. -0x1F0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1F4 12. -0x1F0 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1F4 11. -0x1F0 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1F4 10. -0x1F0 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 09. -0x1F4 09. -0x1F0 09. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 08. -0x1F4 08. -0x1F0 08. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 07. -0x1F4 07. -0x1F0 07. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 06. -0x1F4 06. -0x1F0 06. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 05. -0x1F4 05. -0x1F0 05. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 04. -0x1F4 04. -0x1F0 04. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 03. -0x1F4 03. -0x1F0 03. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 02. -0x1F4 02. -0x1F0 02. " [2] ,Data direction bit 2" "Input,Output" newline setclrfld.long 0x00 01. -0x1F4 01. -0x1F0 01. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 00. -0x1F4 00. -0x1F0 00. " [0] ,Data direction bit 0" "Input,Output" group.long 0x214++0x3 line.long 0x00 "GPIO_DDR2_SET/CLR,Data Direction Set/Clear Register 2" sif cpuis("S6J336?H?")||cpuis("S6J337?H?")||cpuis("S6J336?J?")||cpuis("S6J337?J?") setclrfld.long 0x00 29. -0x1EC 29. -0x1E8 29. " DD[29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1EC 28. -0x1E8 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1EC 27. -0x1E8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1EC 26. -0x1E8 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1EC 25. -0x1E8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1EC 24. -0x1E8 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1EC 23. -0x1E8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1EC 22. -0x1E8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1EC 21. -0x1E8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1EC 20. -0x1E8 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1EC 19. -0x1E8 19. " [19] ,Data direction bit 19" "Input,Output" else setclrfld.long 0x00 19. -0x1EC 19. -0x1E8 19. " DD[19] ,Data direction bit 19" "Input,Output" endif setclrfld.long 0x00 18. -0x1EC 18. -0x1E8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1EC 17. -0x1E8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1EC 16. -0x1E8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1EC 15. -0x1E8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1EC 14. -0x1E8 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1EC 13. -0x1E8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1EC 12. -0x1E8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1EC 11. -0x1E8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1EC 10. -0x1E8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 09. -0x1EC 09. -0x1E8 09. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 08. -0x1EC 08. -0x1E8 08. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 07. -0x1EC 07. -0x1E8 07. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 06. -0x1EC 06. -0x1E8 06. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 05. -0x1EC 05. -0x1E8 05. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 04. -0x1EC 04. -0x1E8 04. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 03. -0x1EC 03. -0x1E8 03. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 02. -0x1EC 02. -0x1E8 02. " [2] ,Data direction bit 2" "Input,Output" newline setclrfld.long 0x00 01. -0x1EC 01. -0x1E8 01. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 00. -0x1EC 00. -0x1E8 00. " [0] ,Data direction bit 0" "Input,Output" sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J336?H?")&&!cpuis("S6J337?H?")) group.long 0x21C++0x3 line.long 0x00 "GPIO_DDR3_SET/CLR,Data Direction Set/Clear Register 3" setclrfld.long 0x00 31. -0x1E4 31. -0x1E0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1E4 30. -0x1E0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1E4 29. -0x1E0 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1E4 28. -0x1E0 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1E4 27. -0x1E0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1E4 26. -0x1E0 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1E4 25. -0x1E0 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1E4 24. -0x1E0 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1E4 23. -0x1E0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1E4 22. -0x1E0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1E4 21. -0x1E0 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1E4 20. -0x1E0 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1E4 19. -0x1E0 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1E4 18. -0x1E0 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1E4 17. -0x1E0 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1E4 16. -0x1E0 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1E4 15. -0x1E0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1E4 14. -0x1E0 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1E4 13. -0x1E0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1E4 12. -0x1E0 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1E4 11. -0x1E0 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1E4 10. -0x1E0 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 09. -0x1E4 09. -0x1E0 09. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 08. -0x1E4 08. -0x1E0 08. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 07. -0x1E4 07. -0x1E0 07. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 06. -0x1E4 06. -0x1E0 06. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 05. -0x1E4 05. -0x1E0 05. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 04. -0x1E4 04. -0x1E0 04. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 03. -0x1E4 03. -0x1E0 03. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 02. -0x1E4 02. -0x1E0 02. " [2] ,Data direction bit 2" "Input,Output" newline setclrfld.long 0x00 01. -0x1E4 01. -0x1E0 01. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 00. -0x1E4 00. -0x1E0 00. " [0] ,Data direction bit 0" "Input,Output" sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")&&!cpuis("S6J336?J?")&&!cpuis("S6J337?J?")) group.long 0x224++0x3 line.long 0x00 "GPIO_DDR4_SET/CLR,Data Direction Set/Clear Register 4" setclrfld.long 0x00 31. -0x1DC 31. -0x1D8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1DC 30. -0x1D8 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1DC 29. -0x1D8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1DC 28. -0x1D8 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1DC 27. -0x1D8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1DC 26. -0x1D8 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1DC 25. -0x1D8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1DC 24. -0x1D8 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1DC 23. -0x1D8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1DC 22. -0x1D8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1DC 21. -0x1D8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1DC 20. -0x1D8 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1DC 19. -0x1D8 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1DC 18. -0x1D8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1DC 17. -0x1D8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1DC 16. -0x1D8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1DC 15. -0x1D8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1DC 14. -0x1D8 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1DC 13. -0x1D8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1DC 12. -0x1D8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1DC 11. -0x1D8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1DC 10. -0x1D8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 09. -0x1DC 09. -0x1D8 09. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 08. -0x1DC 08. -0x1D8 08. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 07. -0x1DC 07. -0x1D8 07. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 06. -0x1DC 06. -0x1D8 06. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 05. -0x1DC 05. -0x1D8 05. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 04. -0x1DC 04. -0x1D8 04. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 03. -0x1DC 03. -0x1D8 03. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 02. -0x1DC 02. -0x1D8 02. " [2] ,Data direction bit 2" "Input,Output" newline setclrfld.long 0x00 01. -0x1DC 01. -0x1D8 01. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 00. -0x1DC 00. -0x1D8 00. " [0] ,Data direction bit 0" "Input,Output" endif endif newline rgroup.long 0x300++0x0B line.long 0x00 "GPIO_PIDR0,Port Input Data Register 0" bitfld.long 0x00 31. " PID_[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x00 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" line.long 0x04 "GPIO_PIDR1,Port Input Data Register 1" bitfld.long 0x04 31. " PID_[31] ,Port input data bit 31" "Low,High" bitfld.long 0x04 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x04 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x04 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x04 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x04 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x04 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x04 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x04 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x04 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x04 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x04 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x04 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x04 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x04 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x04 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x04 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x04 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x04 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x04 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x04 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x04 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x04 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x04 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x04 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x04 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x04 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x04 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x04 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x04 2. " [2] ,Port input data bit 2" "Low,High" newline bitfld.long 0x04 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x04 0. " [0] ,Port input data bit 0" "Low,High" line.long 0x08 "GPIO_PIDR2,Port Input Data Register 2" sif cpuis("S6J336?H?")||cpuis("S6J337?H?")||cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x08 29. " PID_[29] ,Port input data bit 29" "Low,High" bitfld.long 0x08 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x08 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x08 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x08 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x08 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x08 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x08 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x08 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x08 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x08 19. " [19] ,Port input data bit 19" "Low,High" else bitfld.long 0x08 19. " PID_[19] ,Port input data bit 19" "Low,High" endif bitfld.long 0x08 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x08 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x08 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x08 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x08 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x08 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x08 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x08 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x08 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x08 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x08 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x08 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x08 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x08 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x08 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x08 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x08 2. " [2] ,Port input data bit 2" "Low,High" newline bitfld.long 0x08 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x08 0. " [0] ,Port input data bit 0" "Low,High" sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J336?H?")&&!cpuis("S6J337?H?")) rgroup.long 0x30C++0x03 line.long 0x00 "GPIO_PIDR3,Port Input Data Register 3" bitfld.long 0x00 31. " PID_[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x00 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")&&!cpuis("S6J336?J?")&&!cpuis("S6J337?J?")) rgroup.long 0x310++0x03 line.long 0x00 "GPIO_PIDR4,Port Input Data Register 4" bitfld.long 0x00 31. " PID_[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x00 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" endif endif newline group.long 0x400++0x07 line.long 0x00 "GPIO_PORTEN,Port Input Enable Register" bitfld.long 0x00 0. " GPORTEN ,GPIO port enable bit" "Disabled,Enabled" line.long 0x04 "GPIO_KEYCDR,GPIO Key Code Register" bitfld.long 0x04 30.--31. " KEY ,Key code bits" "1,2,3,4" bitfld.long 0x04 28.--29. " SIZE ,Access size bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x04 0.--14. 0x01 " RADR ,Port address bits" width 0x0B tree.end tree "PPC" base ad:0xB4740000 width 14. group.word 0x00++0x1 line.word 0x00 "PPC_PCFGR000,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,LCDD12,MFS7_SOT_1,I2S1_SD_0,,BT0_TIOA1_1,MAD8" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,LCDD5,,,DSP0_R7_0,,MAD1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,,,,,MAD1" endif group.word 0x02++0x1 line.word 0x00 "PPC_PCFGR001,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,LCDD13,MFS7_SCK_1,I2S1_WS_0,,BT1_TIOA2_1,MAD9" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,LCDD6,ARH1_AIC1_DNCLK,,DSP0_G0_0,,MAD2" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,,,,,,MAD2" endif group.word 0x04++0x1 line.word 0x00 "PPC_PCFGR002,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,LCDD14,,I2S1_SCK_0,,BT1_TIOA3_1,MAD10" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SCK1_0,LCDD7,ARH1_AIC1_TDA1,ARH0_AIC1_DNDATA1,DSP0_G1_0,SCL1,MAD3" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SCK1_0,,,,,SCL1,MAD3" endif group.word 0x06++0x1 line.word 0x00 "PPC_PCFGR003,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,MFS1_SOT_1,LCDD15,,,PCMP0_BL_1,BT2_TIOA4_1,MAD11" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,SOT1_0,LCDD8,ARH1_AIC1_dbg_out_1,,DSP0_G2_0,SDA1,MAD4" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,SOT1_0,,,,,SDA1,MAD4" endif group.word 0x08++0x1 line.word 0x00 "PPC_PCFGR004,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,MFS1_SCK_1,LCDD16,,I2S0_SD_0,PCMP0_BH_1,BT2_TIOA5_1,MAD12" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCSO10_0,LCDD9,ARH1_AIC1_dbg_out_0,,DSP0_G3_0,,MAD5" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCSO10_0,,,,,,MAD5" endif group.word 0x0A++0x1 line.word 0x00 "PPC_PCFGR005,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,LCDD17,,I2S0_WS_0,PCMP0_AL_1,BT3_TIOA6_1,MAD13" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,SCSO11_0,LCDD10,ARH0_AIC1_TDA0,ARH0_AIC1_DNDATA0,DSP0_G4_0,SOT0_1,MAD6" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,SCSO11_0,,,,,SOT0_1,MAD6" endif group.word 0x0C++0x1 line.word 0x00 "PPC_PCFGR006,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,MFS1_CS0_1,CS#,,I2S0_SCK_0,PCMP0_AH_1,BT3_TIOA7_1,MAD14" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCSO12_0,LCDD11,SCK0_1,,DSP0_G5_0,PPG0_TOUT0_1,MAD7" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCSO12_0,,SCK0_1,,,PPG0_TOUT0_1,MAD7" endif group.word 0x0E++0x1 line.word 0x00 "PPC_PCFGR007,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,WR#,,,,MFS4_SOT_1,MOEX" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,SCSO13_0,LCDD12,SCSO00_1,I2S1_SD_0,DSP0_G6_0,PPG0_TOUT2_1,MAD8" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,SCSO13_0,,SCSO00_1,,,PPG0_TOUT2_1,MAD8" endif group.word 0x10++0x1 line.word 0x00 "PPC_PCFGR008,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,RD#,,,,MFS4_SCK_1,MWEX" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,LCDD13,,I2S1_WS_0,DSP0_G7,PPG1_TOUT0_1,MAD9" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,,,,,PPG1_TOUT0_1,MAD9" endif group.word 0x12++0x1 line.word 0x00 "PPC_PCFGR009,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,,,,,PCMP1_BL_1,,MCLK" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,,LCDD14,ARH0_AIC0_DNCLK,I2S1_SCK_0,DSP0_B0_0,PPG1_TOUT2_1,MAD10" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,,,,,,PPG1_TOUT2_1,MAD10" endif group.word 0x14++0x1 line.word 0x00 "PPC_PCFGR010,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,RS,,,PCMP1_BH_1,MFS4_CS0_1,MDQM0" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SCSO171_1,LCDD15,ARH0_AIC0_TDA1,ARH0_AIC0_DNDATA1,DSP0_B1,PPG2_TOUT0_1,MAD11" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SCSO171_1,,,,,PPG2_TOUT0_1,MAD11" endif group.word 0x16++0x1 line.word 0x00 "PPC_PCFGR011,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,RES#,,,PCMP1_AL_1,MFS4_CS1_1,MCSX2" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,LCDD16,ARH0_AIC0_dbg_out_1,I2S0_SD_0,DSP0_B2_0,PPG2_TOUT2_1,MAD12" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,,,,,PPG2_TOUT2_1,MAD12" endif group.word 0x18++0x1 line.word 0x00 "PPC_PCFGR012,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,,,,PCMP1_AH_1,MFS4_CS2_1,MCSX3" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,LCDD17,ARH0_AIC0_dbg_out_0,I2S0_WS_0,DSP0_B3_0,PPG3_TOUT0_1,MAD13" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,,,,,PPG3_TOUT0_1,MAD13" endif group.word 0x1A++0x1 line.word 0x00 "PPC_PCFGR013,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,MFS2_SOT_0,DDRHSSPI1_SDATA0,,,MFS9_SOT_2,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,CS#,,I2S0_SCK_0,DSP0_B4_0,PPG3_TOUT2_1,MAD14" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,,,,,PPG3_TOUT2_1,MAD14" endif group.word 0x1C++0x1 line.word 0x00 "PPC_PCFGR014,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,MFS2_SCK_0,DDRHSSPI1_SDATA2,,,MFS9_SCK_2,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,WR#,,,DSP0_B5_0,SCK4_1,MOEX" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,,,,,SCK4_1,MOEX" endif group.word 0x1E++0x1 line.word 0x00 "PPC_PCFGR015,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,DDRHSSPI1_SDATA1,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,RD#,,,DSP0_B6_0,SCSO40_1,MWEX" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,,,,,SCSO40_1,MWEX" endif group.word 0x20++0x1 line.word 0x00 "PPC_PCFGR016,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,MFS2_CS0_0,DDRHSSPI1_SSEL,,,MFS9_CS0_2,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,DSP0_B7_1,,ARH0_AIC0_TDA0,ARH0_AIC0_DNDATA0,,SCSO41_1,MCLK" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,,,,,,SCSO41_1,MCLK" endif group.word 0x22++0x1 line.word 0x00 "PPC_PCFGR017,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,MFS2_CS1_0,DDRHSSPI1_SDATA3,,,MFS9_CS1_2,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,,,,DSP0_B7_0,SCSO43_1,MDQM0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,,,,,SCSO43_1,MDQM0" endif group.word 0x24++0x1 line.word 0x00 "PPC_PCFGR018,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,MFS2_CS2_0,DDRHSSPI0_SCLK,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,RS,,MDC_1,,,MCSX2" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,,MDC_1,,,MCSX2" endif group.word 0x26++0x1 line.word 0x00 "PPC_PCFGR019,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,MFS2_CS3_0,DDRHSSPI0_SDATA0,,,MFS8_SOT_2,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,RES#,,,,,MCSX3" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,,,,,,MCSX3" endif group.word 0x28++0x1 line.word 0x00 "PPC_PCFGR020,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,MFS3_SOT_0,DDRHSSPI0_SDATA2,,,MFS8_SCK_2,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,?..." endif group.word 0x2A++0x1 line.word 0x00 "PPC_PCFGR021,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,MFS3_SCK_0,DDRHSSPI0_SDATA1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,M_SDATA0_0,TXEN_0,M_DQ3,?..." endif group.word 0x2C++0x1 line.word 0x00 "PPC_PCFGR022,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,,DDRHSSPI0_SSEL,,,MFS8_CS0_2,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,SCK2_0,M_SDATA0_2,TXD0_0,M_DQ2,SOT9_2,?..." endif group.word 0x2E++0x1 line.word 0x00 "PPC_PCFGR023,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,MFS3_CS0_0,DDRHSSPI0_SDATA3,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,SOT2_0,M_SDATA0_1,TXD1_0,M_DQ1,SCK9_2,?..." endif group.word 0x30++0x1 line.word 0x00 "PPC_PCFGR024,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/-,2mA/-,-/5mA,-/15mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,MFS3_CS1_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,SCSO20_0,M_SSEL0,TXD2_0,M_DQ0,SCSO90_2,?..." endif group.word 0x32++0x1 line.word 0x00 "PPC_PCFGR025,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,MFS8_SOT_0,,MFS0_SDA,OCU0_OUT0_0,,BT0_TIOA0_0,PCMP0_BL_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,SCSO21_0,M_SDATA0_3,TXD3_0,M_CS#_1,SCSO91_2,?..." endif group.word 0x34++0x1 line.word 0x00 "PPC_PCFGR026,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,MFS8_SCK_0,CAN0_TX_0,MFS0_SCL,OCU0_OUT1_0,RLT0_TOT_0,BT0_TIOA1_0,PCMP0_BH_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,SCSO22_0,M_SCLKO,TXER_0,M_CK,?..." endif group.word 0x36++0x1 line.word 0x00 "PPC_PCFGR027,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,,SG0_SGA_0,,,,BT1_TIOA2_0,PCMP0_AL_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,SCSO23_0,M_SDATA1_0,,M_RWDS,?..." endif group.word 0x38++0x1 line.word 0x00 "PPC_PCFGR028,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,MFS8_CS0_0,SG0_SGO_0,CAN1_TX_0,PWUTRG_0,RLT1_TOT_0,BT1_TIOA3_0,PCMP0_AH_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,M_SDATA1_2,,M_DQ4,SCK8_2,?..." endif group.word 0x3A++0x1 line.word 0x00 "PPC_PCFGR029,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,MFS10_CS0_1,,BT9_TIOA18_1,OCU8_OUT0_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,SCK3_0,M_SDATA1_1,,M_DQ5,SOT8_2,?..." endif group.word 0x3C++0x1 line.word 0x00 "PPC_PCFGR030,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,MFS6_CS0_0,,,OCU8_OUT0_0,,BT4_TIOA8_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,SOT3_0,M_SSEL1,,M_DQ6,SCSO80_2,?..." endif group.word 0x3E++0x1 line.word 0x00 "PPC_PCFGR031,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,MFS6_CS1_0,,,OCU8_OUT1_0,RLT17_TOT_0,BT4_TIOA9_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,SCSO30_0,M_SDATA1_3,MDIO_0,M_DQ7,?..." endif group.word 0x40++0x1 line.word 0x00 "PPC_PCFGR100,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,,Media LB" endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,SG1_SGA_0,IND0_OUT_0,OCU1_OUT0_0,TRACE0_0,BT2_TIOA4_0,PCMP1_BL_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,SCSO31_0,,MDC_0,M_CS#_2,?..." endif group.word 0x42++0x1 line.word 0x00 "PPC_PCFGR101,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,,Media LB" endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,TRACE1_0,SG1_SGO_0,CAN2_TX_0,OCU1_OUT1_0,RLT16_TOT_0,BT2_TIOA5_0,PCMP1_BH_0" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,SCSO32_0,,,,,,MLBSIG" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,SCSO32_0,?..." endif group.word 0x44++0x1 line.word 0x00 "PPC_PCFGR102,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,,Media LB" endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "2mA,5mA,6mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,MFS6_SOT_0,SG2_SGA_0,MFS6_SDA,OCU2_OUT0_0,TRACE2_0,BT3_TIOA6_0,PCMP1_AL_0" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SCSO33_0,,,,,,MLBDAT" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SCSO33_0,?..." endif group.word 0x46++0x1 line.word 0x00 "PPC_PCFGR103,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,MFS6_SCK_0,SG2_SGO_0,MFS6_SCL,OCU2_OUT1_0,TRACE3_0,BT3_TIOA7_0,PCMP1_AH_0" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,OCU0_OTD0_0,,PPG0_TOUT0_0,BN0-BL0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,OCU0_OTD0_0,,PPG0_TOUT0_0,?..." endif group.word 0x48++0x1 line.word 0x00 "PPC_PCFGR104,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,SG3_SGA_0,BT9_TIOA19_1,OCU8_OUT1_1,RLT17_TOT_1,TRACE_CLK_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCK0_0,,SCL0,OCU0_OTD1_0,TOT0_0,PPG0_TOUT2_0,BP0-BL0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCK0_0,,SCL0,OCU0_OTD1_0,TOT0_0,PPG0_TOUT2_0,?..." endif group.word 0x4A++0x1 line.word 0x00 "PPC_PCFGR105,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,MFS7_SOT_0,SG3_SGO_0,,OCU9_OUT0_1,TRACE_CTL_0,MFS7_SDA,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,SOT0_0,SGA0_0,SDA0,TRACE0_0,,PPG1_TOUT0_0,AN0-AL0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,SOT0_0,,SDA0,TRACE0_0,,PPG1_TOUT0_0,?..." endif group.word 0x4C++0x1 line.word 0x00 "PPC_PCFGR106,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,MFS7_SCK_0,SG4_SGA_0,CAN3_TX_0,OCU9_OUT1_1,RLT2_TOT_1,MFS7_SCL,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCSO00_0,SGO0_0,TX0_0,TRACE1_0,TOT1_0,PPG1_TOUT2_0,AP0-AH0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCSO00_0,,TX0_0,TRACE1_0,TOT1_0,PPG1_TOUT2_0,?..." endif group.word 0x4E++0x1 line.word 0x00 "PPC_PCFGR107,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,SYSC0_CLK_1,SG4_SGO_0,,OCU9_OUT0_0,RLT2_TOT_0,BT5_TIOA10_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,SGA1_0,TRACE2_0,OCU1_OTD0_0,,PPG2_TOUT0_0,BN1-BL1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,,TRACE2_0,OCU1_OTD0_0,,PPG2_TOUT0_0,?..." endif group.word 0x50++0x1 line.word 0x00 "PPC_PCFGR108,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,MFS7_CS0_0,,,OCU10_OUT0_0,MFS5_SCK_1,BT5_TIOA11_0,IND0_OUT_1" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TRACE3_0,SGO1_0,TX1_0,OCU1_OTD1_0,TOT16_0,PPG2_TOUT2_0,BP1-BH1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TRACE3_0,,TX1_0,OCU1_OTD1_0,TOT16_0,PPG2_TOUT2_0,?..." endif group.word 0x52++0x1 line.word 0x00 "PPC_PCFGR109,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,MFS7_CS1_0,,,OCU10_OUT1_0,RLT3_TOT_0,SYSC0_CLK_0,RTC0_WOT" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,SCK16_0,SGA2_0,SCL16,OCU2_OTD0_0,TRACECTL_0,PPG3_TOUT0_0,AN1-AL1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,SCK16_0,,SCL16,OCU2_OTD0_0,TRACECTL_0,PPG3_TOUT0_0,?..." endif group.word 0x54++0x1 line.word 0x00 "PPC_PCFGR110,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,,,,SMC0_PWM1P,BT6_TIOA12_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SOT16_0,SGO2_0,SDA16,OCU2_OTD1_0,TRACECLK_0,PPG3_TOUT2_0,AP1-AH1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SOT16_0,,SDA16,OCU2_OTD1_0,TRACECLK_0,PPG3_TOUT2_0,?..." endif group.word 0x56++0x1 line.word 0x00 "PPC_PCFGR111,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,,,,SMC0_PWM1M,BT6_TIOA13_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,SCSO160_0,INDICATOR0,,OCU8_OTD0_0,,PPG4_TOUT0_0,?..." endif group.word 0x58++0x1 line.word 0x00 "PPC_PCFGR112,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,MFS0_SOT_0,,MFS8_SDA,,SMC0_PWM2P,BT7_TIOA14_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,SCSO161_0,,,OCU8_OTD1_0,TOT17_0,PPG16_TOUT2_0,TX2_0" endif group.word 0x5A++0x1 line.word 0x00 "PPC_PCFGR113,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,MFS0_SCK_0,,MFS8_SCL,,SMC0_PWM2M,BT7_TIOA15_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,SGA3_0,,OCU9_OTD0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,,,OCU9_OTD0_0,?..." endif group.word 0x5C++0x1 line.word 0x00 "PPC_PCFGR114,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,,,,SMC1_PWM1P,BT8_TIOA16_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,SYSC0_CLK_1,SGO3_0,,OCU9_OTD1_0,TOT48_0,PPG5_TOUT0_0,TX3_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,SYSC0_CLK_1,,,OCU9_OTD1_0,TOT48_0,PPG5_TOUT0_0,TX3_0" endif group.word 0x5E++0x1 line.word 0x00 "PPC_PCFGR115,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,MFS0_CS0_0,,,,SMC1_PWM1M,BT8_TIOA17_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,SCK17_0,SGA4_0,SCL17,OCU10_OTD0_0,SCK12_1,PPG5_TOUT2_0,INDICATOR0_1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,SCK17_0,,SCL17,OCU10_OTD0_0,SCK12_1,PPG5_TOUT2_0,INDICATOR0_1" endif group.word 0x60++0x1 line.word 0x00 "PPC_PCFGR116,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,MFS9_CS0_0,,,,SMC1_PWM2P,BT9_TIOA18_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,SOT17_0,SGO4_0,SDA17,OCU10_OTD1_0,TOT49_0,SYSC0_CLK_0,WOT" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,SOT17_0,,SDA17,OCU10_OTD1_0,TOT49_0,SYSC0_CLK_0,WOT" endif group.word 0x62++0x1 line.word 0x00 "PPC_PCFGR117,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,MFS9_CS1_0,,,,SMC1_PWM2M,BT9_TIOA19_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,SCSO170_0,,,,PWM1P0,PPG6_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,SCSO170_0,,,,,PPG6_TOUT0_0,?..." endif group.word 0x64++0x1 line.word 0x00 "PPC_PCFGR118,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,MFS9_SOT_0,,MFS9_SDA,,SMC2_PWM1P,BT10_TIOA20_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,SCSO171_0,,,,PWM1M0,PPG6_TOUT2_0,TX5_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,SCSO171_0,,,,,PPG6_TOUT2_0,TX5_0" endif group.word 0x66++0x1 line.word 0x00 "PPC_PCFGR119,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,MFS9_SCK_0,,MFS9_SCL,,SMC2_PWM1M,BT10_TIOA21_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,,,,PWM2P0,PPG7_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,,,,,PPG7_TOUT0_0,?..." endif group.word 0x68++0x1 line.word 0x00 "PPC_PCFGR120,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,,,,SMC2_PWM2P,BT11_TIOA22_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,SCK8_0,,SCL8,,PWM2M0,PPG7_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,SCK8_0,,SCL8,,,PPG7_TOUT2_0,?..." endif group.word 0x6A++0x1 line.word 0x00 "PPC_PCFGR121,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,MFS10_SOT_0,,MFS10_SDA,,SMC2_PWM2M,BT11_TIOA23_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,SOT8_0,,SDA8,,PWM1P1,PPG8_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,SOT8_0,,SDA8,,,PPG8_TOUT0_0,?..." endif group.word 0x6C++0x1 line.word 0x00 "PPC_PCFGR122,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,MFS10_SCK_0,,MFS10_SCL,,SMC3_PWM1P,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,SCSO80_0,,,,PWM1M1,PPG8_TOUT2_0,TX6_0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,SCSO80_0,,,,,PPG8_TOUT2_0,TX6_0" endif group.word 0x6E++0x1 line.word 0x00 "PPC_PCFGR123,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,,,,SMC3_PWM1M,BT12_TIOA24_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,,,,PWM2P1,PPG9_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,,,,,PPG9_TOUT0_0,?..." endif group.word 0x70++0x1 line.word 0x00 "PPC_PCFGR124,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,MFS10_CS0_0,,,,SMC3_PWM2P,BT12_TIOA25_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,SCK9_0,,SCL9,,PWM2M1,PPG9_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,SCK9_0,,SCL9,,,PPG9_TOUT2_0,?..." endif group.word 0x72++0x1 line.word 0x00 "PPC_PCFGR125,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,MFS11_CS0_0,,,,SMC3_PWM2M,BT13_TIOA26_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,SOT9_0,,SDA9,,PWM1P2,PPG10_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,SOT9_0,,SDA9,,,PPG10_TOUT0_0,?..." endif group.word 0x74++0x1 line.word 0x00 "PPC_PCFGR126,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,MFS11_CS1_0,,,,SMC4_PWM1P,BT13_TIOA27_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,SCSO90_0,,,,PWM1M2,PPG10_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,SCSO90_0,,,,,PPG10_TOUT2_0,?..." endif group.word 0x76++0x1 line.word 0x00 "PPC_PCFGR127,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,MFS11_SOT_0,,MFS11_SDA,,SMC4_PWM1M,BT14_TIOA28_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,SCSO91_0,,,,PWM2P2,PPG11_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,SCSO91_0,,,,,PPG11_TOUT0_0,?..." endif group.word 0x78++0x1 line.word 0x00 "PPC_PCFGR128,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,MFS11_SCK_0,,MFS11_SCL,,SMC4_PWM2P,BT14_TIOA29_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,,,PWM2M2,PPG11_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,,,,PPG11_TOUT2_0,?..." endif group.word 0x7A++0x1 line.word 0x00 "PPC_PCFGR129,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,,,,,SMC4_PWM2M,BT15_TIOA30_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,SCK10_0,,SCL10,,PWM1P3,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,SCK10_0,,SCL10,,,?..." endif group.word 0x7C++0x1 line.word 0x00 "PPC_PCFGR130,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,MFS5_SOT_0,,MFS5_SDA,,SMC5_PWM1P,BT15_TIOA31_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,SOT10_0,,SDA10,,PWM1M3,PPG12_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,SOT10_0,,SDA10,,,PPG12_TOUT0_0,?..." endif group.word 0x7E++0x1 line.word 0x00 "PPC_PCFGR131,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,MFS5_SCK_0,,MFS5_SCL,,SMC5_PWM1M,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,SCSO100_0,,,,PWM2P3,PPG12_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,SCSO100_0,,,,,PPG12_TOUT2_0,?..." endif group.word 0x80++0x1 line.word 0x00 "PPC_PCFGR200,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,,,SMC5_PWM2P,,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,,,PWM2M3,PPG13_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,,,,PPG13_TOUT0_0,?..." endif group.word 0x82++0x1 line.word 0x00 "PPC_PCFGR201,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,5mA/2mA,30mA/-" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,MFS5_CS0_0,,,,SMC5_PWM2M,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,SCK11_0,,SCL11,,PWM1P4,PPG13_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,SCK11_0,,SCL11,,,PPG13_TOUT2_0,?..." endif group.word 0x84++0x1 line.word 0x00 "PPC_PCFGR202,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SOT11_0,,SDA11,,PWM1M4,PPG14_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SOT11_0,,SDA11,,,PPG14_TOUT0_0,?..." endif group.word 0x86++0x1 line.word 0x00 "PPC_PCFGR203,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,SCSO110_0,,,,PWM2P4,PPG14_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,SCSO110_0,,,,,PPG14_TOUT2_0,?..." endif group.word 0x88++0x1 line.word 0x00 "PPC_PCFGR204,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,MFS2_SOT_1,,,,,BT12_TIOA24_1,MDATA8" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCSO111_0,,,,PWM2M4,PPG15_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCSO111_0,,,,,PPG15_TOUT0_0,?..." endif group.word 0x8A++0x1 line.word 0x00 "PPC_PCFGR205,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,MFS2_SCK_1,,,,I2S0_SD_1,BT12_TIOA25_1,MDATA9" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,,,,PWM1P5,PPG15_TOUT2_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,,,,,PPG15_TOUT2_0,?..." endif group.word 0x8C++0x1 line.word 0x00 "PPC_PCFGR206,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,,,,I2S0_WS_1,BT13_TIOA26_1,MDATA10" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCK12_0,,SCL12,,PWM1M5,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCK12_0,,SCL12,?..." endif group.word 0x8E++0x1 line.word 0x00 "PPC_PCFGR207,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,MFS2_CS0_1,,,,I2S0_SCK_1,BT13_TIOA27_1,MDATA11" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,SOT12_0,,SDA12,,PWM2P5,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,SOT12_0,,SDA12,?..." endif group.word 0x90++0x1 line.word 0x00 "PPC_PCFGR208,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,MFS2_CS1_1,,,,,BT14_TIOA28_1,MCSX0" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,SCSO120_2,,,,PWM2M5,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,SCSO120_2,?..." endif group.word 0x92++0x1 line.word 0x00 "PPC_PCFGR209,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,MFS3_SOT_1,,,,,BT14_TIOA29_1,MDATA12" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,SCSO23_1,,,,DSP0_EN_0,PPG14_TOUT0_1,MCSX0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,SCSO23_1,,,,,PPG14_TOUT0_1,MCSX0" endif group.word 0x94++0x1 line.word 0x00 "PPC_PCFGR210,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,MFS3_SCK_1,,,,SG0_SGA_2,BT15_TIOA30_1,MDATA13" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SCSO31_1,,,,DSP0_HSYNC_0,,MCSX1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SCSO31_1,,,,,,MCSX1" endif group.word 0x96++0x1 line.word 0x00 "PPC_PCFGR211,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,,,,SG0_SGO_2,BT15_TIOA31_1,MDATA14" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,SCSO32_1,,,,DSP0_VSYNC_0,,MDATA0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,SCSO32_1,,,,,,MDATA0" endif group.word 0x98++0x1 line.word 0x00 "PPC_PCFGR212,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,15mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,MFS3_CS0_1,,,,SG1_SGA_2,,MDATA15" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,SCSO33_1,,,,DSP0_CLK_0,,MDATA1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,SCSO33_1,,,,,,MDATA1" endif group.word 0x9A++0x1 line.word 0x00 "PPC_PCFGR213,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,MFS3_CS1_1,,,,SG1_SGO_2,,MCSX1" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,,,,DSP0_R0_0,,MDATA2" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,,,,,,MDATA2" endif group.word 0x9C++0x1 line.word 0x00 "PPC_PCFGR214,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,MFS3_CS2_1,,,,,,MDATA0" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,SCK4_0,,SCL4,,DSP0_R1_0,,MDATA3" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,SCK4_0,,SCL4,,,,MDATA3" endif group.word 0x9E++0x1 line.word 0x00 "PPC_PCFGR215,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,MFS3_CS3_1,LCDD0,,,,,MDATA1" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,SOT4_0,LCDD0,SDA4,,DSP0_R2_0,,MDATA4" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,SOT4_0,,SDA4,,,,MDATA4" endif group.word 0xA0++0x1 line.word 0x00 "PPC_PCFGR216,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,MFS4_SOT_0,LCDD1,MFS4_SDA,,,,MDATA2" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,SCSO40_0,LCDD1,,,DSP0_R3_0,,MDATA5" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,SCSO40_0,,,,,,MDATA5" endif group.word 0xA2++0x1 line.word 0x00 "PPC_PCFGR217,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,MFS4_SCK_0,LCDD2,MFS4_SCL,,,,MDATA3" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,SCSO41_0,LCDD2,,,DSP0_R4_0,,MDATA6" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,SCSO41_0,,,,,,MDATA6" endif group.word 0xA4++0x1 line.word 0x00 "PPC_PCFGR218,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,LCDD3,,,,,MDATA4" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,SCSO42_0,LCDD3,,,DSP0_R5_0,,MDATA7" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,SCSO42_0,,,,,,MDATA7" endif group.word 0xA6++0x1 line.word 0x00 "PPC_PCFGR219,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,MFS4_CS0_0,,,,,,MDATA5" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,SCSO43_0,,,,,TX7_1,MAD0" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,SCSO43_0,LCDD4,,,DSP0_R6_0,,MAD0" endif sif cpuis("S6J336*")||cpuis("S6J337*") group.word 0xA8++0x1 line.word 0x00 "PPC_PCFGR220,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,MFS4_CS1_0,,,,,,MDATA6" group.word 0xAA++0x1 line.word 0x00 "PPC_PCFGR221,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,MFS4_CS2_0,,,,,,MDATA7" group.word 0xAC++0x1 line.word 0x00 "PPC_PCFGR222,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,MFS4_CS3_0,LCDD4,,,,,MAD0" group.word 0xAE++0x1 line.word 0x00 "PPC_PCFGR223,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,MFS1_SOT_0,LCDD5,,,,MFS1_SDA,MAD1" group.word 0xB0++0x1 line.word 0x00 "PPC_PCFGR224,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,MFS1_SCK_0,LCDD6,,,,MFS1_SCL,MAD2" group.word 0xB2++0x1 line.word 0x00 "PPC_PCFGR225,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,LCDD7,,,,,MAD3" group.word 0xB4++0x1 line.word 0x00 "PPC_PCFGR226,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,MFS1_CS0_0,LCDD8,MFS0_CS0_1,,,,MAD4" group.word 0xB6++0x1 line.word 0x00 "PPC_PCFGR227,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,MFS1_CS1_0,LCDD9,,,,MFS0_SOT_1,MAD5" group.word 0xB8++0x1 line.word 0x00 "PPC_PCFGR228,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,MFS1_CS2_0,LCDD10,MFS0_SCK_1,,,,MAD6" group.word 0xBA++0x1 line.word 0x00 "PPC_PCFGR229,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,MFS1_CS3_0,LCDD11,,,,BT0_TIOA0_1,MAD7" endif sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J336?H?")&&!cpuis("S6J337?H?")) group.word 0xC0++0x1 line.word 0x00 "PPC_PCFGR300,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,MFS1_CS1_1,,,,,BT4_TIOA8_1,MAD15" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,TXD1_1,,,,PPG4_TOUT0_1,MAD15" endif group.word 0xC2++0x1 line.word 0x00 "PPC_PCFGR301,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,MFS1_CS2_1,,,,,BT4_TIOA9_1,MAD16" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,SCK1_1,TXD2_1,,,,PPG4_TOUT2_1,MAD16" endif group.word 0xC4++0x1 line.word 0x00 "PPC_PCFGR302,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,MFS1_CS3_1,,,,,BT5_TIOA10_1,MAD17" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,SOT1_1,TXD3_1,,,,PPG5_TOUT0_1,MAD17" endif group.word 0xC6++0x1 line.word 0x00 "PPC_PCFGR303,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,,,BT5_TIOA11_1,MAD18" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,SCSO10_1,TXER_1,,,,PPG5_TOUT2_1,MAD18" endif group.word 0xC8++0x1 line.word 0x00 "PPC_PCFGR304,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,,BT10_TIOA20_1,,,,MAD19" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,SCSO11_1,,,,,,MAD19" endif group.word 0xCA++0x1 line.word 0x00 "PPC_PCFGR305,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,,,,,,MAD20" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,SCSO12_1,,,,,,MAD20" endif group.word 0xCC++0x1 line.word 0x00 "PPC_PCFGR306,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,,,,,,MAD21" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,SCSO13_1,MDIO_1,,,,SOT4_1,MAD21" endif group.word 0xCE++0x1 line.word 0x00 "PPC_PCFGR307,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,,,,,MFS4_CS3_1,MDQMI" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,,,,,SCSO42_1,MDQMI" endif group.word 0xD0++0x1 line.word 0x00 "PPC_PCFGR308,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,MFS8_SOT_1,SG0_SGA_1,BT6_TIOA12_1,OCU0_OUT0_1,,TRACE0_1,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,SGA0_1,PPG6_TOUT0_1,OCU0_OTD0_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,,PPG6_TOUT0_1,OCU0_OTD0_1,?..." endif group.word 0xD2++0x1 line.word 0x00 "PPC_PCFGR309,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,MFS8_SCK_1,SG0_SGO_1,BT6_TIOA13_1,OCU0_OUT1_1,RLT0_TOT_1,TRACE1_1,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,SCK8_1,SGO0_1,PPG6_TOUT2_1,OCU0_OTD1_1,TOT0_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,SCK8_1,,PPG6_TOUT2_1,OCU0_OTD1_1,TOT0_1,PPG22_TOUT0_0,?..." endif group.word 0xD4++0x1 line.word 0x00 "PPC_PCFGR310,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,SG1_SGA_1,BT7_TIOA14_1,OCU1_OUT0_1,,TRACE2_1,CAN0_TX_1" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SOT8_1,SGA1_1,PPG7_TOUT0_1,OCU1_OTD0_1,TRACE0_1,,TX0_1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,SOT8_1,,PPG7_TOUT0_1,OCU1_OTD0_1,TRACE0_1,PPG22_TOUT2_1,TX0_1" endif group.word 0xD6++0x1 line.word 0x00 "PPC_PCFGR311,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,MFS10_SOT_1,SG1_SGO_1,BT7_TIOA15_1,OCU1_OUT1_1,RLT1_TOT_1,TRACE3_1,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,SCSO80_1,SGO1_1,PPG7_TOUT2_1,OCU1_OTD1_1,TOT1_1,TRACE1_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,SCSO80_1,,PPG7_TOUT2_1,OCU1_OTD1_1,TOT1_1,TRACE1_1,?..." endif group.word 0xD8++0x1 line.word 0x00 "PPC_PCFGR312,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,MFS10_SCK_1,SG2_SGA_1,BT8_TIOA16_1,OCU2_OUT0_1,,TRACE_CLK_1,CAN1_TX_1" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,SGA2_1,PPG8_TOUT0_1,OCU2_OTD0-1,,TRACE2_1,TX1_1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,,PPG8_TOUT0_1,OCU2_OTD0-1,,TRACE2_1,TX1_1" endif group.word 0xDA++0x1 line.word 0x00 "PPC_PCFGR313,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,SG2_SGO_1,BT8_TIOA17_1,OCU2_OUT1_1,RLT16_TOT_1,TRACE_CTL_1,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,SCK10_1,SGO2_1,PPG8_TOUT2_1,OCU2_OTD1_1,TOT16_1,TRACE3_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,SCK10_1,,PPG8_TOUT2_1,OCU2_OTD1_1,TOT16_1,TRACE3_1,?..." endif group.word 0xDC++0x1 line.word 0x00 "PPC_PCFGR314,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,SOT10_1,SGA3_1,PPG9_TOUT0_1,OCU8_OTD0_1,,TRACECTL_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,SOT10_1,,PPG9_TOUT0_1,OCU8_OTD0_1,,TRACECTL_1,?..." endif group.word 0xDE++0x1 line.word 0x00 "PPC_PCFGR315,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,,BT11_TIOA22_1,OCU10_OUT0_1,,,CAN2_TX_1" elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,SCSO100_1,SGO3_1,PPG9_TOUT2_1,OCU8_OTD1_1,TOT17_1,TRACECLK_1,TX2_1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,SCSO100_1,,PPG9_TOUT2_1,OCU8_OTD1_1,TOT17_1,TRACECLK_1,TX2_1" endif group.word 0xE0++0x1 line.word 0x00 "PPC_PCFGR316,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,MFS9_SOT_1,,,OCU9_OUT1_0,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,,SGA4_1,PPG10_TOUT0_1,OCU9_OTD0_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,,,PPG10_TOUT0_1,OCU9_OTD0_1,?..." endif group.word 0xE2++0x1 line.word 0x00 "PPC_PCFGR317,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,MFS9_SCK_1,,BT11_TIOA23_1,OCU10_OUT1_1,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,SGO4_1,PPG10_TOUT2_1,OCU9_OTD1_1,TOT48,,TX3_1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,,PPG10_TOUT2_1,OCU9_OTD1_1,TOT48,,TX3_1" endif group.word 0xE4++0x1 line.word 0x00 "PPC_PCFGR318,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,BT10_TIOA21_1,,,,CAN3_TX_1" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,PPG11_TOUT0_1,OCU10_OTD0_1,?..." endif group.word 0xE6++0x1 line.word 0x00 "PPC_PCFGR319,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,MFS9_CS0_1,SG3_SGA_1,,,RLT3_TOT_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,SCK9_1,,PPG11_TOUT2_1,OCU10_OTD1_1,?..." endif group.word 0xE8++0x1 line.word 0x00 "PPC_PCFGR320,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,MFS9_CS1_1,SG3_SGO_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,SOT9_1,,,,,,TX5_1" endif group.word 0xEA++0x1 line.word 0x00 "PPC_PCFGR321,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,,,PWUTRG_1,MFS5_SOT_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,SCSO90_1,,,,TOT49_1,?..." endif group.word 0xEC++0x1 line.word 0x00 "PPC_PCFGR322,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,,SG4_SGA_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,SCSO91_1,?..." endif group.word 0xEE++0x1 line.word 0x00 "PPC_PCFGR323,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,SG4_SGO_1,,,MFS5_CS0_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,,,,SCSO120_1,,TX6_1" endif group.word 0xF0++0x1 line.word 0x00 "PPC_PCFGR324,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,SOT2_1,,,,,PPG12_TOUT0_1,MDATA8" endif group.word 0xF2++0x1 line.word 0x00 "PPC_PCFGR325,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,SCSO20_1,,,,I2S0_SD_1,PPG12_TOUT2_1,MDATA9" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,SCSO20_1,,,,,PPG12_TOUT2_1,MDATA9" endif group.word 0xF4++0x1 line.word 0x00 "PPC_PCFGR326,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,SCSO21_1,,,,I2S0_WS_1,PPG13_TOUT0_1,MDATA10" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,SCSO21_1,,,,,PPG13_TOUT0_1,MDATA10" endif group.word 0xF6++0x1 line.word 0x00 "PPC_PCFGR327,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,?..." elif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,SCSO22_1,,,,I2S0_SCK_1,PPG13_TOUT2_1,MDATA11" else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,SCSO22_1,,,,,PPG13_TOUT2_1,MDATA11" endif group.word 0xF8++0x1 line.word 0x00 "PPC_PCFGR328,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,MFS2_CS2_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,,,,PPG14_TOUT2_1,MDATA12" endif group.word 0xFA++0x1 line.word 0x00 "PPC_PCFGR329,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,MFS2_CS3_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,SCK3_1,,,,,PPG15_TOUT0_1,MDATA13" endif group.word 0xFC++0x1 line.word 0x00 "PPC_PCFGR330,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,SOT3_1,,,,,PPG15_TOUT2_1,MDATA14" endif group.word 0xFE++0x1 line.word 0x00 "PPC_PCFGR331,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." else bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." endif bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit [5V/3.3V]" "1mA/0.5mA,2mA/1mA,,5mA/2mA" else bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." endif newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,,,,,CAN0_TX_2,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,SCSO30_1,,,,,,MDATA15" endif sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")&&!cpuis("S6J336?J?")&&!cpuis("S6J337?J?")) group.word 0x100++0x1 line.word 0x00 "PPC_PCFGR400,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,,,,PPG16_TOUT0_0,?..." endif group.word 0x102++0x1 line.word 0x00 "PPC_PCFGR401,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,,,,TX0_2,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,,,,TX0_2,PPG16_TOUT2_0,?..." endif group.word 0x104++0x1 line.word 0x00 "PPC_PCFGR402,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,,,,,PPG17_TOUT0_0,?..." endif group.word 0x106++0x1 line.word 0x00 "PPC_PCFGR403,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,SCSO170_1,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,SCSO170_1,,,PPG17_TOUT2_0,?..." endif group.word 0x108++0x1 line.word 0x00 "PPC_PCFGR404,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,TXEN_1,SCK17_1,,TX3_2,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,TXEN_1,SCK17_1,,TX3_2,PPG18_TOUT0_0,?..." endif group.word 0x10A++0x1 line.word 0x00 "PPC_PCFGR405,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,TXD0_1,SOT17_1,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,TXD0_1,SOT17_1,,,PPG18_TOUT2_0,?..." endif group.word 0x10C++0x1 line.word 0x00 "PPC_PCFGR406,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,,,,,PPG19_TOUT0_0,?..." endif group.word 0x10E++0x1 line.word 0x00 "PPC_PCFGR407,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,,,,,PPG19_TOUT2_0,?..." endif group.word 0x110++0x1 line.word 0x00 "PPC_PCFGR408,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,,,,,PPG20_TOUT0_0,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,,,,,PPG20_TOUT0_0,?..." endif group.word 0x112++0x1 line.word 0x00 "PPC_PCFGR409,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,,,,,,PPG20_TOUT2_0,?..." endif group.word 0x114++0x1 line.word 0x00 "PPC_PCFGR410,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,,,,,PPG21_TOUT0_0,?..." endif group.word 0x116++0x1 line.word 0x00 "PPC_PCFGR411,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,,,,,PPG21_TOUT2_0,?..." endif group.word 0x118++0x1 line.word 0x00 "PPC_PCFGR412,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,,,,,PPG23_TOUT0_0,?..." endif group.word 0x11A++0x1 line.word 0x00 "PPC_PCFGR413,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,,,,,PPG23_TOUT2_0,?..." endif group.word 0x11C++0x1 line.word 0x00 "PPC_PCFGR414,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,,,,,PPG24_TOUT0_0,?..." endif group.word 0x11E++0x1 line.word 0x00 "PPC_PCFGR415,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,,,,,PPG24_TOUT2_0,?..." endif group.word 0x120++0x1 line.word 0x00 "PPC_PCFGR416,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,,,,,,PPG25_TOUT0_0,?..." endif group.word 0x122++0x1 line.word 0x00 "PPC_PCFGR417,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,,,,SOT12_1,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,,,,SOT12_1,PPG25_TOUT2_0,?..." endif group.word 0x124++0x1 line.word 0x00 "PPC_PCFGR418,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,,,,PPG26_TOUT0_0,?..." endif group.word 0x126++0x1 line.word 0x00 "PPC_PCFGR419,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,,,,,PPG26_TOUT2_0,?..." endif group.word 0x128++0x1 line.word 0x00 "PPC_PCFGR420,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,,,,SOT16_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,,,,SOT16_1,PPG27_TOUT0_0,TX4_0" endif group.word 0x12A++0x1 line.word 0x00 "PPC_PCFGR421,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,,,,SCK16_1,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,,,,SCK16_1,PPG27_TOUT2_0,?..." endif group.word 0x12C++0x1 line.word 0x00 "PPC_PCFGR422,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,,,,,SCSO161_1,?..." group.word 0x12E++0x1 line.word 0x00 "PPC_PCFGR423,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,,,,SCSO160_1,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,,,,SCSO160_1,PPG28_TOUT0_0,TX7_0" endif group.word 0x130++0x1 line.word 0x00 "PPC_PCFGR424,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,,,,,,PPG28_TOUT2_0,?..." endif group.word 0x132++0x1 line.word 0x00 "PPC_PCFGR425,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,,,,,PPG29_TOUT0_0,?..." endif group.word 0x134++0x1 line.word 0x00 "PPC_PCFGR426,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,,,,,,PPG29_TOUT2_0,?..." endif group.word 0x136++0x1 line.word 0x00 "PPC_PCFGR427,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,,,,,,PPG30_TOUT0_0,?..." endif group.word 0x138++0x1 line.word 0x00 "PPC_PCFGR428,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,,,,PPG30_TOUT2_0,?..." endif group.word 0x13A++0x1 line.word 0x00 "PPC_PCFGR429,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,,,,,,PPG31_TOUT0_0,?..." endif group.word 0x13C++0x1 line.word 0x00 "PPC_PCFGR430,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" sif (!cpuis("S6J335*")) bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,,,,,,,?..." else bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,,,,,,PPG31_TOUT2_0,?..." endif group.word 0x13E++0x1 line.word 0x00 "PPC_PCFGR431,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,SCK2_1,?..." endif endif newline group.long 0x400++0x3 line.long 0x00 "PPC_KEYCDR,PPC Key Code Register" bitfld.long 0x00 30.--31. " KEY ,Key code bits" "1,2,3,4" bitfld.long 0x00 28.--29. " SIZE ,Access size bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x00 0.--14. 0x01 " RADR ,Port address bits" width 0x0B tree.end sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "RIC" base ad:0xB4748000 width 15. group.word 0x00++0x1 line.word 0x00 "RIC_RESIN0,SIN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P2_29,?..." group.word 0x02++0x1 line.word 0x00 "RIC_RESIN1,SCK0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,P2_28,?..." group.word 0x04++0x1 line.word 0x00 "RIC_RESIN2,SCL0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x06++0x1 line.word 0x00 "RIC_RESIN3,SDA0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x08++0x1 line.word 0x00 "RIC_RESIN4,MFS0_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x0A++0x1 line.word 0x00 "RIC_RESIN5,SCS0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,P2_26,?..." group.word 0x0E++0x1 line.word 0x00 "RIC_RESIN7,SIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_25,P0_05,?..." group.word 0x10++0x1 line.word 0x00 "RIC_RESIN8,SCK1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_24,P0_04,?..." group.word 0x12++0x1 line.word 0x00 "RIC_RESIN9,SCL1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x14++0x1 line.word 0x00 "RIC_RESIN10,SDA1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x16++0x1 line.word 0x00 "RIC_RESIN11,MFS1_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x18++0x1 line.word 0x00 "RIC_RESIN12,SCS1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_26,P0_06,?..." group.word 0x1C++0x1 line.word 0x00 "RIC_RESIN14,SIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_15,P2_06,?..." group.word 0x1E++0x1 line.word 0x00 "RIC_RESIN15,SCK2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_14,P2_05,?..." group.word 0x24++0x1 line.word 0x00 "RIC_RESIN18,MFS2_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x26++0x1 line.word 0x00 "RIC_RESIN19,SCS2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_16,P2_07,?..." group.word 0x2A++0x1 line.word 0x00 "RIC_RESIN21,SIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_22,P2_11,?..." group.word 0x2C++0x1 line.word 0x00 "RIC_RESIN22,SCK3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,P2_10,?..." group.word 0x32++0x1 line.word 0x00 "RIC_RESIN25,MFS3_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x34++0x1 line.word 0x00 "RIC_RESIN26,SCS3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_23,P2_12,?..." group.word 0x38++0x1 line.word 0x00 "RIC_RESIN28,SIN4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_18,P0_09,?..." group.word 0x3A++0x1 line.word 0x00 "RIC_RESIN29,SCK4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_17,P0_08,?..." group.word 0x3C++0x1 line.word 0x00 "RIC_RESIN30,SCL4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x3E++0x1 line.word 0x00 "RIC_RESIN31,SDA4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x40++0x1 line.word 0x00 "RIC_RESIN32,MFS4_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x42++0x1 line.word 0x00 "RIC_RESIN33,SCS4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_19,P0_10,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x46++0x1 line.word 0x00 "RIC_RESIN35,SIN5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_00,P3_22,?..." else group.word 0x46++0x1 line.word 0x00 "RIC_RESIN35,SIN5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_00,?..." endif group.word 0x48++0x1 line.word 0x00 "RIC_RESIN36,SCK5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,P1_08,?..." group.word 0x4A++0x1 line.word 0x00 "RIC_RESIN37,SCL5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x4C++0x1 line.word 0x00 "RIC_RESIN38,SDA5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x4E++0x1 line.word 0x00 "RIC_RESIN39,MFS5_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x50++0x1 line.word 0x00 "RIC_RESIN40,SCS5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_01,P3_23,?..." else group.word 0x50++0x1 line.word 0x00 "RIC_RESIN40,SCS5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_01,?..." endif group.word 0x54++0x1 line.word 0x00 "RIC_RESIN42,SIN6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,?..." group.word 0x56++0x1 line.word 0x00 "RIC_RESIN43,SCK6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,?..." group.word 0x58++0x1 line.word 0x00 "RIC_RESIN44,SCL6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x5A++0x1 line.word 0x00 "RIC_RESIN45,SDA6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x5C++0x1 line.word 0x00 "RIC_RESIN46,MFS6_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x5E++0x1 line.word 0x00 "RIC_RESIN47,SCS6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,?..." group.word 0x62++0x1 line.word 0x00 "RIC_RESIN49,SIN7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P0_02,?..." group.word 0x64++0x1 line.word 0x00 "RIC_RESIN50,SCK7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,P0_01,?..." group.word 0x66++0x1 line.word 0x00 "RIC_RESIN51,SCL7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x68++0x1 line.word 0x00 "RIC_RESIN52,SDA7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x6A++0x1 line.word 0x00 "RIC_RESIN53,MFS7_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x6C++0x1 line.word 0x00 "RIC_RESIN54,SCS7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x70++0x1 line.word 0x00 "RIC_RESIN56,SIN8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,P3_10,P0_21,?..." group.word 0x72++0x1 line.word 0x00 "RIC_RESIN57,SCK8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_26,P3_09,P0_20,?..." else group.word 0x70++0x1 line.word 0x00 "RIC_RESIN56,SIN8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,,P0_21,?..." group.word 0x72++0x1 line.word 0x00 "RIC_RESIN57,SCK8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_26,,P0_20,?..." endif group.word 0x74++0x1 line.word 0x00 "RIC_RESIN58,SCL8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x76++0x1 line.word 0x00 "RIC_RESIN59,SDA8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x78++0x1 line.word 0x00 "RIC_RESIN60,MFS8_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." group.word 0x7A++0x1 line.word 0x00 "RIC_RESIN61,SCS8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,,P0_22,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x7E++0x1 line.word 0x00 "RIC_RESIN63,SIN9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_20,P3_18,P0_15,?..." group.word 0x80++0x1 line.word 0x00 "RIC_RESIN64,SCK9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,P3_17,P0_14,?..." else group.word 0x7E++0x1 line.word 0x00 "RIC_RESIN63,SIN9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_20,,P0_15,?..." group.word 0x80++0x1 line.word 0x00 "RIC_RESIN64,SCK9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,,P0_14,?..." endif group.word 0x82++0x1 line.word 0x00 "RIC_RESIN65,SCL9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x84++0x1 line.word 0x00 "RIC_RESIN66,SDA9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x86++0x1 line.word 0x00 "RIC_RESIN67,MFS9_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x88++0x1 line.word 0x00 "RIC_RESIN68,SCS9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_19,P0_16,?..." else group.word 0x88++0x1 line.word 0x00 "RIC_RESIN68,SCS9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,P0_16,?..." endif sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x8C++0x1 line.word 0x00 "RIC_RESIN70,SIN10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,P3_13,?..." group.word 0x8E++0x1 line.word 0x00 "RIC_RESIN71,SCK10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P3_12,?..." else group.word 0x8C++0x1 line.word 0x00 "RIC_RESIN70,SIN10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,?..." group.word 0x8E++0x1 line.word 0x00 "RIC_RESIN71,SCK10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,?..." endif group.word 0x90++0x1 line.word 0x00 "RIC_RESIN72,SCL10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x92++0x1 line.word 0x00 "RIC_RESIN73,SDA10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x94++0x1 line.word 0x00 "RIC_RESIN74,MFS10_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." group.word 0x96++0x1 line.word 0x00 "RIC_RESIN75,SCS10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_24,P0_29,?..." group.word 0x9E++0x1 line.word 0x00 "RIC_RESIN79,SCL11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xA0++0x1 line.word 0x00 "RIC_RESIN80,SDA11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xA2++0x1 line.word 0x00 "RIC_RESIN81,MFS11_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x1A4++0x1 line.word 0x00 "RIC_RESIN210,RX0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,P3_09,P3_30,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN0_RX_AND_TX,?..." group.word 0x1A6++0x1 line.word 0x00 "RIC_RESIN211,RX1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,P3_11,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN1_RX_AND_TX,?..." group.word 0x1A8++0x1 line.word 0x00 "RIC_RESIN212,RX2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,P3_14,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN2_RX_AND_TX,?..." group.word 0x1AA++0x1 line.word 0x00 "RIC_RESIN213,RX3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_17,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN3_RX_AND_TX,?..." group.word 0x1B6++0x1 line.word 0x00 "RIC_RESIN219,TIN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,P3_08,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT3,RLT3_UFSET,TOT1,TIOA0,?..." group.word 0x1B8++0x1 line.word 0x00 "RIC_RESIN220,TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,P3_10,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,TIOA2,?..." group.word 0x1BA++0x1 line.word 0x00 "RIC_RESIN221,TIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P3_16,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,RLT1_UFSET,TOT3,TIOA4,?..." group.word 0x1BC++0x1 line.word 0x00 "RIC_RESIN222,TIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,P3_18,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,RLT2_UFSET,TOT0,TIOA6,?..." group.word 0x1D6++0x1 line.word 0x00 "RIC_RESIN235,TIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,P3_12,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT17,RLT17_UFSET,,TIOA8,?..." else group.word 0x1A4++0x1 line.word 0x00 "RIC_RESIN210,RX0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN0_RX_AND_TX,?..." group.word 0x1A6++0x1 line.word 0x00 "RIC_RESIN211,RX1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN1_RX_AND_TX,?..." group.word 0x1A8++0x1 line.word 0x00 "RIC_RESIN212,RX2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN2_RX_AND_TX,?..." group.word 0x1AA++0x1 line.word 0x00 "RIC_RESIN213,RX3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN3_RX_AND_TX,?..." group.word 0x1B6++0x1 line.word 0x00 "RIC_RESIN219,TIN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT3,RLT3_UFSET,TOT1,TIOA0,?..." group.word 0x1B8++0x1 line.word 0x00 "RIC_RESIN220,TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,TIOA2,?..." group.word 0x1BA++0x1 line.word 0x00 "RIC_RESIN221,TIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" ",P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,RLT1_UFSET,TOT3,TIOA4,?..." group.word 0x1BC++0x1 line.word 0x00 "RIC_RESIN222,TIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,RLT2_UFSET,TOT0,TIOA6,?..." group.word 0x1D6++0x1 line.word 0x00 "RIC_RESIN235,TIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT17,RLT17_UFSET,,TIOA8,?..." endif group.word 0x1D8++0x1 line.word 0x00 "RIC_RESIN236,TIN17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,P0_29,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,,TIOA10,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x1F6++0x1 line.word 0x00 "RIC_RESIN251,INT0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_18,P2_23,P0_01,,P3_16,P1_25,P2_19,?..." group.word 0x1F8++0x1 line.word 0x00 "RIC_RESIN252,INT1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_25,P3_00,P0_02,P0_13,P3_14,,P2_20,?..." group.word 0x1FA++0x1 line.word 0x00 "RIC_RESIN253,INT2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_15,P2_02,,P0_14,P3_18,P1_26,P2_21,?..." group.word 0x1FC++0x1 line.word 0x00 "RIC_RESIN254,INT3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_22,P2_09,,P0_16,P3_19,P1_27,P2_22,?..." group.word 0x1FE++0x1 line.word 0x00 "RIC_RESIN255,INT4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,P2_24,,P0_17,P3_21,P1_28,?..." group.word 0x200++0x1 line.word 0x00 "RIC_RESIN256,INT5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_26,P2_26,P0_03,P0_18,P3_22,?..." group.word 0x202++0x1 line.word 0x00 "RIC_RESIN257,INT6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,P3_09,P0_04,P0_19,P3_23,P1_30,?..." group.word 0x204++0x1 line.word 0x00 "RIC_RESIN258,INT7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,P3_30,P0_05,P0_20,,P1_31,?..." group.word 0x206++0x1 line.word 0x00 "RIC_RESIN259,INT8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,P3_11,P0_06,P0_21,?..." group.word 0x208++0x1 line.word 0x00 "RIC_RESIN260,INT9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,P3_31,P3_01,P0_23,P1_09,P2_01,?..." group.word 0x20A++0x1 line.word 0x00 "RIC_RESIN261,INT10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,,P3_02,P0_24,,P2_03,?..." group.word 0x20C++0x1 line.word 0x00 "RIC_RESIN262,INT11 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_01,P2_27,P3_03,,P1_11,P2_04,?..." group.word 0x20E++0x1 line.word 0x00 "RIC_RESIN263,INT12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_02,P0_29,P3_04,,P1_13,P2_05,?..." else group.word 0x1F6++0x1 line.word 0x00 "RIC_RESIN251,INT0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_18,P2_23,P0_01,,,P1_25,P2_19,?..." group.word 0x1F8++0x1 line.word 0x00 "RIC_RESIN252,INT1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_25,,P0_02,P0_13,,,P2_20,?..." group.word 0x1FA++0x1 line.word 0x00 "RIC_RESIN253,INT2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_15,P2_02,,P0_14,,P1_26,P2_21,?..." group.word 0x1FC++0x1 line.word 0x00 "RIC_RESIN254,INT3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_22,P2_09,,P0_16,,P1_27,P2_22,?..." group.word 0x1FE++0x1 line.word 0x00 "RIC_RESIN255,INT4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,P2_24,,P0_17,,P1_28,?..." group.word 0x200++0x1 line.word 0x00 "RIC_RESIN256,INT5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_26,P2_26,P0_03,P0_18,?..." group.word 0x202++0x1 line.word 0x00 "RIC_RESIN257,INT6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,,P0_04,P0_19,,P1_30,?..." group.word 0x204++0x1 line.word 0x00 "RIC_RESIN258,INT7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,,P0_05,P0_20,,P1_31,?..." group.word 0x206++0x1 line.word 0x00 "RIC_RESIN259,INT8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,,P0_06,P0_21,?..." group.word 0x208++0x1 line.word 0x00 "RIC_RESIN260,INT9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,,,P0_23,P1_09,P2_01,?..." group.word 0x20A++0x1 line.word 0x00 "RIC_RESIN261,INT10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,,,P0_24,,P2_03,?..." group.word 0x20C++0x1 line.word 0x00 "RIC_RESIN262,INT11 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_01,P2_27,,,P1_11,P2_04,?..." group.word 0x20E++0x1 line.word 0x00 "RIC_RESIN263,INT12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_02,P0_29,,,P1_13,P2_05,?..." endif group.word 0x210++0x1 line.word 0x00 "RIC_RESIN264,INT13 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,P2_28,,,P1_15,P2_06,?..." group.word 0x212++0x1 line.word 0x00 "RIC_RESIN265,INT14 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P1_06,,,P1_16,P2_07,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x214++0x1 line.word 0x00 "RIC_RESIN266,INT15 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P2_29,P3_05,,P1_17,P2_08,?..." group.word 0x216++0x1 line.word 0x00 "RIC_RESIN267,INT16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,,P3_06,,,P2_10,?..." group.word 0x218++0x1 line.word 0x00 "RIC_RESIN268,INT17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,P3_17,P3_07,P3_10,P1_18,P2_11,?..." group.word 0x21A++0x1 line.word 0x00 "RIC_RESIN269,INT18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,P3_08,P0_07,P3_13,P1_19,P2_12,?..." group.word 0x21C++0x1 line.word 0x00 "RIC_RESIN270,INT19 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P3_20,P0_08,P1_03,,P2_13,?..." group.word 0x21E++0x1 line.word 0x00 "RIC_RESIN271,INT20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_20,P3_15,P0_09,,P1_21,P2_14,?..." group.word 0x220++0x1 line.word 0x00 "RIC_RESIN272,INT21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,P3_12,P0_10,,P1_22,P2_15,?..." else group.word 0x214++0x1 line.word 0x00 "RIC_RESIN266,INT15 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P2_29,,,P1_17,P2_08,?..." group.word 0x216++0x1 line.word 0x00 "RIC_RESIN267,INT16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,,,,,P2_10,?..." group.word 0x218++0x1 line.word 0x00 "RIC_RESIN268,INT17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,,,,P1_18,P2_11,?..." group.word 0x21A++0x1 line.word 0x00 "RIC_RESIN269,INT18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,,P0_07,,P1_19,P2_12,?..." group.word 0x21C++0x1 line.word 0x00 "RIC_RESIN270,INT19 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,,P0_08,P1_03,,P2_13,?..." group.word 0x21E++0x1 line.word 0x00 "RIC_RESIN271,INT20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_20,,P0_09,,P1_21,P2_14,?..." group.word 0x220++0x1 line.word 0x00 "RIC_RESIN272,INT21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,,P0_10,,P1_22,P2_15,?..." endif group.word 0x222++0x1 line.word 0x00 "RIC_RESIN273,INT22 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,P0_11,,P1_24,P2_16,?..." group.word 0x224++0x1 line.word 0x00 "RIC_RESIN274,INT23 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_00,P0_00,P0_12,,,P2_17,?..." group.word 0x236++0x1 line.word 0x00 "RIC_RESIN283,TEXT0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,TIOA1,?..." group.word 0x238++0x1 line.word 0x00 "RIC_RESIN284,TEXT1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT2,TIOA3,?..." group.word 0x23A++0x1 line.word 0x00 "RIC_RESIN285,TEXT2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT3,TIOA5,?..." group.word 0x23C++0x1 line.word 0x00 "RIC_RESIN286,TEXT3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,TIOA7,?..." group.word 0x23E++0x1 line.word 0x00 "RIC_RESIN287,TEXT4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT2,TIOA9,?..." group.word 0x246++0x1 line.word 0x00 "RIC_RESIN291,TEXT8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,TIOA17,?..." group.word 0x248++0x1 line.word 0x00 "RIC_RESIN292,TEXT9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT2_UFSET,TIOA19,?..." group.word 0x24A++0x1 line.word 0x00 "RIC_RESIN293,TEXT10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT3_UFSET,TIOA21,?..." group.word 0x256++0x1 line.word 0x00 "RIC_RESIN299,OCU0/OCU1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,?..." group.word 0x258++0x1 line.word 0x00 "RIC_RESIN300,OCU0_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x25A++0x1 line.word 0x00 "RIC_RESIN301,OCU1_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x25C++0x1 line.word 0x00 "RIC_RESIN302,OCU2/OCU3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,?..." group.word 0x25E++0x1 line.word 0x00 "RIC_RESIN303,OCU2_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x260++0x1 line.word 0x00 "RIC_RESIN304,OCU3_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x262++0x1 line.word 0x00 "RIC_RESIN305,OCU4/OCU5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,FRT1,?..." group.word 0x264++0x1 line.word 0x00 "RIC_RESIN306,OCU4_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x266++0x1 line.word 0x00 "RIC_RESIN307,OCU5_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x286++0x1 line.word 0x00 "RIC_RESIN323,OCU16/OCU17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x288++0x1 line.word 0x00 "RIC_RESIN324,OCU16_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x28A++0x1 line.word 0x00 "RIC_RESIN325,OCU17_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x28C++0x1 line.word 0x00 "RIC_RESIN326,OCU18/OCU19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,?..." group.word 0x28E++0x1 line.word 0x00 "RIC_RESIN327,OCU18_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x290++0x1 line.word 0x00 "RIC_RESIN328,OCU19_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x292++0x1 line.word 0x00 "RIC_RESIN329,OCU20/OCU21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,?..." group.word 0x294++0x1 line.word 0x00 "RIC_RESIN330,OCU20_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x296++0x1 line.word 0x00 "RIC_RESIN331,OCU21_MOD Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x2B6++0x1 line.word 0x00 "RIC_RESIN347,IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,P3_08,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS0_LSYN,,TOT0,TOT1,?..." group.word 0x2B8++0x1 line.word 0x00 "RIC_RESIN348,IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_26,P3_09,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS1_LSYN,,TOT0,TOT2,?..." else group.word 0x2B6++0x1 line.word 0x00 "RIC_RESIN347,IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_25,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS0_LSYN,,TOT0,TOT1,?..." group.word 0x2B8++0x1 line.word 0x00 "RIC_RESIN348,IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_26,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS1_LSYN,,TOT0,TOT2,?..." endif group.word 0x2BA++0x1 line.word 0x00 "RIC_RESIN349,ICU0/ICU1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x2BC++0x1 line.word 0x00 "RIC_RESIN350,IN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,P3_10,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS2_LSYN,,TOT0,TOT3,?..." group.word 0x2BE++0x1 line.word 0x00 "RIC_RESIN351,IN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,P3_11,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS3_LSYN,,TOT0,TOT1,?..." else group.word 0x2BC++0x1 line.word 0x00 "RIC_RESIN350,IN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS2_LSYN,,TOT0,TOT3,?..." group.word 0x2BE++0x1 line.word 0x00 "RIC_RESIN351,IN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS3_LSYN,,TOT0,TOT1,?..." endif group.word 0x2C0++0x1 line.word 0x00 "RIC_RESIN352,ICU2/ICU3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x2C2++0x1 line.word 0x00 "RIC_RESIN353,IN4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,P3_12,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS4_LSYN,,TOT0,TOT2,?..." group.word 0x2C4++0x1 line.word 0x00 "RIC_RESIN354,IN5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_01,P3_13,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS5_LSYN,,TOT0,TOT3,?..." else group.word 0x2C2++0x1 line.word 0x00 "RIC_RESIN353,IN4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_00,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS4_LSYN,,TOT0,TOT2,?..." group.word 0x2C4++0x1 line.word 0x00 "RIC_RESIN354,IN5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_01,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS5_LSYN,,TOT0,TOT3,?..." endif group.word 0x2C6++0x1 line.word 0x00 "RIC_RESIN355,ICU4/ICU5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,FRT1,?..." group.word 0x2E6++0x1 line.word 0x00 "RIC_RESIN371,IN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_02,P0_29,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS6_LSYN,,TOT0,TOT1,?..." group.word 0x2E8++0x1 line.word 0x00 "RIC_RESIN372,IN17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P1_04,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS7_LSYN,,TOT0,TOT2,?..." group.word 0x2EA++0x1 line.word 0x00 "RIC_RESIN373,ICU16/ICU17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x2EC++0x1 line.word 0x00 "RIC_RESIN374,IN18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS8_LSYN,,TOT0,TOT3,?..." group.word 0x2EE++0x1 line.word 0x00 "RIC_RESIN375,IN19 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS9_LSYN,,TOT0,TOT1,?..." group.word 0x2F0++0x1 line.word 0x00 "RIC_RESIN376,ICU18/ICU19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,?..." sif cpuis("S6J336?J?")||cpuis("S6J337?J?") group.word 0x2F2++0x1 line.word 0x00 "RIC_RESIN377,IN20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P3_15,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS10_LSYN,,TOT0,TOT2,?..." group.word 0x2F4++0x1 line.word 0x00 "RIC_RESIN378,IN21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,P3_17,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS11_LSYN,,TOT0,TOT3,?..." else group.word 0x2F2++0x1 line.word 0x00 "RIC_RESIN377,IN20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS10_LSYN,,TOT0,TOT2,?..." group.word 0x2F4++0x1 line.word 0x00 "RIC_RESIN378,IN21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS11_LSYN,,TOT0,TOT3,?..." endif group.word 0x2F6++0x1 line.word 0x00 "RIC_RESIN379,ICU20/ICU21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,?..." group.word 0x346++0x1 line.word 0x00 "RIC_RESIN419,AIN8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TIOA0,TIOA1,TIOA2,?..." group.word 0x348++0x1 line.word 0x00 "RIC_RESIN420,BIN8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,TIOA1,TIOA2,TIOA0,?..." group.word 0x34A++0x1 line.word 0x00 "RIC_RESIN421,ZIN8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,TIOA2,TIOA0,TIOA1,?..." group.word 0x34C++0x1 line.word 0x00 "RIC_RESIN422,AIN9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,TIOA3,TIOA4,TIOA5,?..." group.word 0x34E++0x1 line.word 0x00 "RIC_RESIN423,BIN9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,TIOA4,TIOA5,TIOA3,?..." group.word 0x350++0x1 line.word 0x00 "RIC_RESIN424,ZIN9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT3,TIOA5,TIOA3,TIOA4,?..." group.word 0x376++0x1 line.word 0x00 "RIC_RESIN443,TIOB0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OUT0,?..." group.word 0x378++0x1 line.word 0x00 "RIC_RESIN444,TIOA1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x37A++0x1 line.word 0x00 "RIC_RESIN445,TIOB1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x37C++0x1 line.word 0x00 "RIC_RESIN446,TIOB2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT1_MTSF,OUT1,?..." group.word 0x37E++0x1 line.word 0x00 "RIC_RESIN447,TIOA3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x380++0x1 line.word 0x00 "RIC_RESIN448,TIOB3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x382++0x1 line.word 0x00 "RIC_RESIN449,TIOB4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT2_MTSF,OUT2,?..." group.word 0x384++0x1 line.word 0x00 "RIC_RESIN450,TIOA5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x386++0x1 line.word 0x00 "RIC_RESIN451,TIOB5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x388++0x1 line.word 0x00 "RIC_RESIN452,TIOB6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT3_MTSF,OUT3,?..." group.word 0x38A++0x1 line.word 0x00 "RIC_RESIN453,TIOA7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x38C++0x1 line.word 0x00 "RIC_RESIN454,TIOB7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x38E++0x1 line.word 0x00 "RIC_RESIN455,TIOB8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT4_MTSF,OUT4,?..." group.word 0x390++0x1 line.word 0x00 "RIC_RESIN456,TIOA9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x392++0x1 line.word 0x00 "RIC_RESIN457,TIOB9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x394++0x1 line.word 0x00 "RIC_RESIN458,TIOB10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_05,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OUT5,?..." group.word 0x396++0x1 line.word 0x00 "RIC_RESIN459,TIOA11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x398++0x1 line.word 0x00 "RIC_RESIN460,TIOB11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x39A++0x1 line.word 0x00 "RIC_RESIN461,TIOB12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P1_06,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT0,?..." group.word 0x39C++0x1 line.word 0x00 "RIC_RESIN462,TIOA13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x39E++0x1 line.word 0x00 "RIC_RESIN463,TIOB13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3A0++0x1 line.word 0x00 "RIC_RESIN464,TIOB14 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P1_06,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT9_MTSF,OUT1,?..." group.word 0x3A2++0x1 line.word 0x00 "RIC_RESIN465,TIOA15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3A4++0x1 line.word 0x00 "RIC_RESIN466,TIOB15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3A6++0x1 line.word 0x00 "RIC_RESIN467,TIOB16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P1_06,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT10_MTSF,OUT16,?..." group.word 0x3A8++0x1 line.word 0x00 "RIC_RESIN468,TIOA17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3AA++0x1 line.word 0x00 "RIC_RESIN469,TIOB17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3AC++0x1 line.word 0x00 "RIC_RESIN470,TIOB18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P1_06,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OUT17,?..." group.word 0x3AE++0x1 line.word 0x00 "RIC_RESIN471,TIOA19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B0++0x1 line.word 0x00 "RIC_RESIN472,TIOB19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B2++0x1 line.word 0x00 "RIC_RESIN473,TIOB20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P1_06,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT9_MTSF,OUT18,?..." group.word 0x3B4++0x1 line.word 0x00 "RIC_RESIN474,TIOA21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B6++0x1 line.word 0x00 "RIC_RESIN475,TIOB21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B8++0x1 line.word 0x00 "RIC_RESIN476,TIOB22 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P1_06,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT10_MTSF,OUT19,?..." group.word 0x3BA++0x1 line.word 0x00 "RIC_RESIN477,TIOA23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3BC++0x1 line.word 0x00 "RIC_RESIN478,TIOB23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3BE++0x1 line.word 0x00 "RIC_RESIN479,TIOB24 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,P2_12,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT0_MTSF,OUT20,?..." group.word 0x3C0++0x1 line.word 0x00 "RIC_RESIN480,TIOA25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C2++0x1 line.word 0x00 "RIC_RESIN481,TIOB25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C4++0x1 line.word 0x00 "RIC_RESIN482,TIOB26 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,P2_12,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT1_MTSF,OUT21,?..." group.word 0x3C6++0x1 line.word 0x00 "RIC_RESIN483,TIOA27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C8++0x1 line.word 0x00 "RIC_RESIN484,TIOB27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3CA++0x1 line.word 0x00 "RIC_RESIN485,TIOB28 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,P2_12,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT2_MTSF,OUT0,?..." group.word 0x3CC++0x1 line.word 0x00 "RIC_RESIN486,TIOA29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3CE++0x1 line.word 0x00 "RIC_RESIN487,TIOB29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3D0++0x1 line.word 0x00 "RIC_RESIN488,TIOB30 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,P2_12,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT3_MTSF,OUT1,?..." group.word 0x3D2++0x1 line.word 0x00 "RIC_RESIN489,TIOA31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3D4++0x1 line.word 0x00 "RIC_RESIN490,TIOB31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x436++0x1 line.word 0x00 "RIC_RESIN539,ADC0_TRG0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P1_08,?..." group.word 0x43A++0x1 line.word 0x00 "RIC_RESIN541,ADC0_HWTRG0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_000_A,BT_ADTO_000_B,?..." group.word 0x43C++0x1 line.word 0x00 "RIC_RESIN542,BT_ADTO_000_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x43E++0x1 line.word 0x00 "RIC_RESIN543,BT_ADTO_000_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x444++0x1 line.word 0x00 "RIC_RESIN546,ADC0_HWTRG1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT1,OUT2,BT_ADTO_001_A,BT_ADTO_001_B,?..." group.word 0x446++0x1 line.word 0x00 "RIC_RESIN547,BT_ADTO_001_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x448++0x1 line.word 0x00 "RIC_RESIN548,BT_ADTO_001_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x44E++0x1 line.word 0x00 "RIC_RESIN551,ADC0_HWTRG2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT2,OUT3,BT_ADTO_002_A,BT_ADTO_002_B,?..." group.word 0x450++0x1 line.word 0x00 "RIC_RESIN552,BT_ADTO_002_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x452++0x1 line.word 0x00 "RIC_RESIN553,BT_ADTO_002_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x458++0x1 line.word 0x00 "RIC_RESIN556,ADC0_HWTRG3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT3,OUT4,BT_ADTO_003_A,BT_ADTO_003_B,?..." group.word 0x45A++0x1 line.word 0x00 "RIC_RESIN557,BT_ADTO_003_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x45C++0x1 line.word 0x00 "RIC_RESIN558,BT_ADTO_003_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x462++0x1 line.word 0x00 "RIC_RESIN561,ADC0_HWTRG4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT4,OUT5,BT_ADTO_004_A,BT_ADTO_004_B,?..." group.word 0x464++0x1 line.word 0x00 "RIC_RESIN562,BT_ADTO_004_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x466++0x1 line.word 0x00 "RIC_RESIN563,BT_ADTO_004_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x46C++0x1 line.word 0x00 "RIC_RESIN566,ADC0_HWTRG5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT5,OUT16,BT_ADTO_005_A,BT_ADTO_005_B,?..." group.word 0x46E++0x1 line.word 0x00 "RIC_RESIN567,BT_ADTO_005_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x470++0x1 line.word 0x00 "RIC_RESIN568,BT_ADTO_005_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x476++0x1 line.word 0x00 "RIC_RESIN571,ADC0_HWTRG6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT16,OUT17,BT_ADTO_006_A,BT_ADTO_006_B,?..." group.word 0x478++0x1 line.word 0x00 "RIC_RESIN572,BT_ADTO_006_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x47A++0x1 line.word 0x00 "RIC_RESIN573,BT_ADTO_006_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x480++0x1 line.word 0x00 "RIC_RESIN576,ADC0_HWTRG7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT17,OUT18,BT_ADTO_007_A,BT_ADTO_007_B,?..." group.word 0x482++0x1 line.word 0x00 "RIC_RESIN577,BT_ADTO_007_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x484++0x1 line.word 0x00 "RIC_RESIN578,BT_ADTO_007_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x48A++0x1 line.word 0x00 "RIC_RESIN581,ADC0_HWTRG8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT18,OUT19,BT_ADTO_008_A,BT_ADTO_008_B,?..." group.word 0x48C++0x1 line.word 0x00 "RIC_RESIN582,BT_ADTO_008_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x48E++0x1 line.word 0x00 "RIC_RESIN583,BT_ADTO_008_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x494++0x1 line.word 0x00 "RIC_RESIN586,ADC0_HWTRG9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT19,OUT20,BT_ADTO_009_A,BT_ADTO_009_B,?..." group.word 0x496++0x1 line.word 0x00 "RIC_RESIN587,BT_ADTO_009_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x498++0x1 line.word 0x00 "RIC_RESIN588,BT_ADTO_009_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x49E++0x1 line.word 0x00 "RIC_RESIN591,ADC0_HWTRG10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT20,OUT21,BT_ADTO_010_A,BT_ADTO_010_B,?..." group.word 0x4A0++0x1 line.word 0x00 "RIC_RESIN592,BT_ADTO_010_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4A2++0x1 line.word 0x00 "RIC_RESIN593,BT_ADTO_010_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4A8++0x1 line.word 0x00 "RIC_RESIN596,ADC0_HWTRG11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT21,OUT0,BT_ADTO_011_A,BT_ADTO_011_B,?..." group.word 0x4AA++0x1 line.word 0x00 "RIC_RESIN597,BT_ADTO_011_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4AC++0x1 line.word 0x00 "RIC_RESIN598,BT_ADTO_011_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4B2++0x1 line.word 0x00 "RIC_RESIN601,ADC0_HWTRG12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_012_A,BT_ADTO_012_B,?..." group.word 0x4B4++0x1 line.word 0x00 "RIC_RESIN602,BT_ADTO_012_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4B6++0x1 line.word 0x00 "RIC_RESIN603,BT_ADTO_012_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4BC++0x1 line.word 0x00 "RIC_RESIN606,ADC0_HWTRG13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT1,OUT2,BT_ADTO_013_A,BT_ADTO_013_B,?..." group.word 0x4BE++0x1 line.word 0x00 "RIC_RESIN607,BT_ADTO_013_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4C0++0x1 line.word 0x00 "RIC_RESIN608,BT_ADTO_013_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4C6++0x1 line.word 0x00 "RIC_RESIN611,ADC0_HWTRG14 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT2,OUT3,BT_ADTO_014_A,BT_ADTO_014_B,?..." group.word 0x4C8++0x1 line.word 0x00 "RIC_RESIN612,BT_ADTO_014_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4CA++0x1 line.word 0x00 "RIC_RESIN613,BT_ADTO_014_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4D0++0x1 line.word 0x00 "RIC_RESIN616,ADC0_HWTRG15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT3,OUT4,BT_ADTO_015_A,BT_ADTO_015_B,?..." group.word 0x4D2++0x1 line.word 0x00 "RIC_RESIN617,BT_ADTO_015_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4D4++0x1 line.word 0x00 "RIC_RESIN618,BT_ADTO_015_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4DA++0x1 line.word 0x00 "RIC_RESIN621,ADC0_HWTRG16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT4,OUT5,BT_ADTO_016_A,BT_ADTO_016_B,?..." group.word 0x4DC++0x1 line.word 0x00 "RIC_RESIN622,BT_ADTO_016_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4DE++0x1 line.word 0x00 "RIC_RESIN623,BT_ADTO_016_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4E4++0x1 line.word 0x00 "RIC_RESIN626,ADC0_HWTRG17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT5,OUT16,BT_ADTO_017_A,BT_ADTO_017_B,?..." group.word 0x4E6++0x1 line.word 0x00 "RIC_RESIN627,BT_ADTO_017_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4E8++0x1 line.word 0x00 "RIC_RESIN628,BT_ADTO_017_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4EE++0x1 line.word 0x00 "RIC_RESIN631,ADC0_HWTRG18 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT16,OUT17,BT_ADTO_018_A,BT_ADTO_018_B,?..." group.word 0x4F0++0x1 line.word 0x00 "RIC_RESIN632,BT_ADTO_018_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4F2++0x1 line.word 0x00 "RIC_RESIN633,BT_ADTO_018_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4F8++0x1 line.word 0x00 "RIC_RESIN636,ADC0_HWTRG19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT17,OUT18,BT_ADTO_019_A,BT_ADTO_019_B,?..." group.word 0x4FA++0x1 line.word 0x00 "RIC_RESIN637,BT_ADTO_019_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4FC++0x1 line.word 0x00 "RIC_RESIN638,BT_ADTO_019_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x502++0x1 line.word 0x00 "RIC_RESIN641,ADC0_HWTRG20 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT18,OUT19,BT_ADTO_020_A,BT_ADTO_020_B,?..." group.word 0x504++0x1 line.word 0x00 "RIC_RESIN642,BT_ADTO_020_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x506++0x1 line.word 0x00 "RIC_RESIN643,BT_ADTO_020_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x50C++0x1 line.word 0x00 "RIC_RESIN646,ADC0_HWTRG21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT19,OUT20,BT_ADTO_021_A,BT_ADTO_021_B,?..." group.word 0x50E++0x1 line.word 0x00 "RIC_RESIN647,BT_ADTO_021_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x510++0x1 line.word 0x00 "RIC_RESIN648,BT_ADTO_021_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x516++0x1 line.word 0x00 "RIC_RESIN651,ADC0_HWTRG22 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT20,OUT21,BT_ADTO_022_A,BT_ADTO_022_B,?..." group.word 0x518++0x1 line.word 0x00 "RIC_RESIN652,BT_ADTO_022_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x51A++0x1 line.word 0x00 "RIC_RESIN653,BT_ADTO_022_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x520++0x1 line.word 0x00 "RIC_RESIN656,ADC0_HWTRG23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT21,OUT0,BT_ADTO_023_A,BT_ADTO_023_B,?..." group.word 0x522++0x1 line.word 0x00 "RIC_RESIN657,BT_ADTO_023_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x524++0x1 line.word 0x00 "RIC_RESIN658,BT_ADTO_023_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x52A++0x1 line.word 0x00 "RIC_RESIN661,ADC0_HWTRG24 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_024_A,BT_ADTO_024_B,?..." group.word 0x52C++0x1 line.word 0x00 "RIC_RESIN662,BT_ADTO_024_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x52E++0x1 line.word 0x00 "RIC_RESIN663,BT_ADTO_024_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x534++0x1 line.word 0x00 "RIC_RESIN666,ADC0_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT1,OUT2,BT_ADTO_025_A,BT_ADTO_025_B,?..." group.word 0x536++0x1 line.word 0x00 "RIC_RESIN667,BT_ADTO_025_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x538++0x1 line.word 0x00 "RIC_RESIN668,BT_ADTO_025_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x53E++0x1 line.word 0x00 "RIC_RESIN671,ADC0_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT2,OUT3,BT_ADTO_026_A,BT_ADTO_026_B,?..." group.word 0x540++0x1 line.word 0x00 "RIC_RESIN672,BT_ADTO_026_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x542++0x1 line.word 0x00 "RIC_RESIN673,BT_ADTO_026_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x548++0x1 line.word 0x00 "RIC_RESIN676,ADC0_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT3,OUT4,BT_ADTO_027_A,BT_ADTO_027_B,?..." group.word 0x54A++0x1 line.word 0x00 "RIC_RESIN677,BT_ADTO_027_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x54C++0x1 line.word 0x00 "RIC_RESIN678,BT_ADTO_027_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x552++0x1 line.word 0x00 "RIC_RESIN681,ADC0_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT4,OUT5,BT_ADTO_028_A,BT_ADTO_028_B,?..." group.word 0x554++0x1 line.word 0x00 "RIC_RESIN682,BT_ADTO_028_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x556++0x1 line.word 0x00 "RIC_RESIN683,BT_ADTO_028_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x55C++0x1 line.word 0x00 "RIC_RESIN686,ADC0_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT5,OUT16,BT_ADTO_029_A,BT_ADTO_029_B,?..." group.word 0x55E++0x1 line.word 0x00 "RIC_RESIN687,BT_ADTO_029_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x560++0x1 line.word 0x00 "RIC_RESIN688,BT_ADTO_029_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x566++0x1 line.word 0x00 "RIC_RESIN691,ADC0_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT16,OUT17,BT_ADTO_030_A,BT_ADTO_030_B,?..." group.word 0x568++0x1 line.word 0x00 "RIC_RESIN692,BT_ADTO_030_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x56A++0x1 line.word 0x00 "RIC_RESIN693,BT_ADTO_030_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x570++0x1 line.word 0x00 "RIC_RESIN696,ADC0_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT17,OUT18,BT_ADTO_031_A,BT_ADTO_031_B,?..." group.word 0x572++0x1 line.word 0x00 "RIC_RESIN697,BT_ADTO_031_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x574++0x1 line.word 0x00 "RIC_RESIN698,BT_ADTO_031_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x57A++0x1 line.word 0x00 "RIC_RESIN701,ADC0_HWTRG32 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT18,OUT19,BT_ADTO_032_A,BT_ADTO_032_B,?..." group.word 0x57C++0x1 line.word 0x00 "RIC_RESIN702,BT_ADTO_032_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x57E++0x1 line.word 0x00 "RIC_RESIN703,BT_ADTO_032_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x584++0x1 line.word 0x00 "RIC_RESIN706,ADC0_HWTRG33 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT19,OUT20,BT_ADTO_033_A,BT_ADTO_033_B,?..." group.word 0x586++0x1 line.word 0x00 "RIC_RESIN707,BT_ADTO_033_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x588++0x1 line.word 0x00 "RIC_RESIN708,BT_ADTO_033_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x58E++0x1 line.word 0x00 "RIC_RESIN711,ADC0_HWTRG34 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT20,OUT21,BT_ADTO_034_A,BT_ADTO_034_B,?..." group.word 0x590++0x1 line.word 0x00 "RIC_RESIN712,BT_ADTO_034_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x592++0x1 line.word 0x00 "RIC_RESIN713,BT_ADTO_034_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x598++0x1 line.word 0x00 "RIC_RESIN716,ADC0_HWTRG35 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT21,OUT0,BT_ADTO_035_A,BT_ADTO_035_B,?..." group.word 0x59A++0x1 line.word 0x00 "RIC_RESIN717,BT_ADTO_035_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x59C++0x1 line.word 0x00 "RIC_RESIN718,BT_ADTO_035_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5A2++0x1 line.word 0x00 "RIC_RESIN721,ADC0_HWTRG36 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_036_A,BT_ADTO_036_B,?..." group.word 0x5A4++0x1 line.word 0x00 "RIC_RESIN722,BT_ADTO_036_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5A6++0x1 line.word 0x00 "RIC_RESIN723,BT_ADTO_036_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5AC++0x1 line.word 0x00 "RIC_RESIN726,ADC0_HWTRG37 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT1,OUT2,BT_ADTO_037_A,BT_ADTO_037_B,?..." group.word 0x5AE++0x1 line.word 0x00 "RIC_RESIN727,BT_ADTO_037_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5B0++0x1 line.word 0x00 "RIC_RESIN728,BT_ADTO_037_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5B6++0x1 line.word 0x00 "RIC_RESIN731,ADC0_HWTRG38 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT2,OUT3,BT_ADTO_038_A,BT_ADTO_038_B,?..." group.word 0x5B8++0x1 line.word 0x00 "RIC_RESIN732,BT_ADTO_038_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5BA++0x1 line.word 0x00 "RIC_RESIN733,BT_ADTO_038_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5C0++0x1 line.word 0x00 "RIC_RESIN736,ADC0_HWTRG39 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT3,OUT4,BT_ADTO_039_A,BT_ADTO_039_B,?..." group.word 0x5C2++0x1 line.word 0x00 "RIC_RESIN737,BT_ADTO_039_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5C4++0x1 line.word 0x00 "RIC_RESIN738,BT_ADTO_039_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5CA++0x1 line.word 0x00 "RIC_RESIN741,ADC0_HWTRG40 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT4,OUT5,BT_ADTO_040_A,BT_ADTO_040_B,?..." group.word 0x5CC++0x1 line.word 0x00 "RIC_RESIN742,BT_ADTO_040_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5CE++0x1 line.word 0x00 "RIC_RESIN743,BT_ADTO_040_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5D4++0x1 line.word 0x00 "RIC_RESIN746,ADC0_HWTRG41 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT5,OUT16,BT_ADTO_041_A,BT_ADTO_041_B,?..." group.word 0x5D6++0x1 line.word 0x00 "RIC_RESIN747,BT_ADTO_041_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5D8++0x1 line.word 0x00 "RIC_RESIN748,BT_ADTO_041_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5DE++0x1 line.word 0x00 "RIC_RESIN751,ADC0_HWTRG42 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT0_UFSET,RLT1_UFSET,OUT16,OUT17,BT_ADTO_042_A,BT_ADTO_042_B,?..." group.word 0x5E0++0x1 line.word 0x00 "RIC_RESIN752,BT_ADTO_042_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5E2++0x1 line.word 0x00 "RIC_RESIN753,BT_ADTO_042_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5E8++0x1 line.word 0x00 "RIC_RESIN756,ADC0_HWTRG43 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT1_UFSET,RLT2_UFSET,OUT17,OUT18,BT_ADTO_043_A,BT_ADTO_043_B,?..." group.word 0x5EA++0x1 line.word 0x00 "RIC_RESIN757,BT_ADTO_043_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5EC++0x1 line.word 0x00 "RIC_RESIN758,BT_ADTO_043_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5F2++0x1 line.word 0x00 "RIC_RESIN761,ADC0_HWTRG44 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT2_UFSET,RLT3_UFSET,OUT18,OUT19,BT_ADTO_044_A,BT_ADTO_044_B,?..." group.word 0x5F4++0x1 line.word 0x00 "RIC_RESIN762,BT_ADTO_044_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5F6++0x1 line.word 0x00 "RIC_RESIN763,BT_ADTO_044_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5FC++0x1 line.word 0x00 "RIC_RESIN766,ADC0_HWTRG45 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT3_UFSET,RLT16_UFSET,OUT19,OUT20,BT_ADTO_045_A,BT_ADTO_045_B,?..." group.word 0x5FE++0x1 line.word 0x00 "RIC_RESIN767,BT_ADTO_045_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x600++0x1 line.word 0x00 "RIC_RESIN768,BT_ADTO_045_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x606++0x1 line.word 0x00 "RIC_RESIN771,ADC0_HWTRG46 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT16_UFSET,RLT17_UFSET,OUT20,OUT21,BT_ADTO_046_A,BT_ADTO_046_B,?..." group.word 0x608++0x1 line.word 0x00 "RIC_RESIN772,BT_ADTO_046_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x60A++0x1 line.word 0x00 "RIC_RESIN773,BT_ADTO_046_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x610++0x1 line.word 0x00 "RIC_RESIN776,ADC0_HWTRG47 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN(ADC0_TRG0),RLT17_UFSET,RLT0_UFSET,OUT21,OUT0,BT_ADTO_047_A,BT_ADTO_047_B,?..." group.word 0x612++0x1 line.word 0x00 "RIC_RESIN777,BT_ADTO_047_A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x614++0x1 line.word 0x00 "RIC_RESIN778,BT_ADTO_047_B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x94A++0x1 line.word 0x00 "RIC_RESIN1189,DDRHSSPI_MSTART Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" ",TOT0,TOT16,?..." group.word 0x950++0x1 line.word 0x00 "RIC_RESIN1192,I2S0_WS Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_05,P2_06,?..." group.word 0x952++0x1 line.word 0x00 "RIC_RESIN1193,I2S0_SD Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_04,P2_05,?..." group.word 0x954++0x1 line.word 0x00 "RIC_RESIN1194,I2S0_SCK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_06,P2_07,?..." group.word 0x956++0x1 line.word 0x00 "RIC_RESIN1195,I2S0_ECLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_03,P2_04,?..." newline bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,SYSC1_CLK_CD2,?..." group.word 0x95E++0x1 line.word 0x00 "RIC_RESIN1199,I2S1_ECLK Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,SYSC1_CLK_CD2,?..." group.word 0x960++0x1 line.word 0x00 "RIC_RESIN1200,SOUND_RST_N Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1 (Negate),Set 0 (Assert),?..." group.word 0x976++0x1 line.word 0x00 "RIC_RESIN1211,DMA[10] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_0,EXT_IRQ_8,EXT_IRQ_16,?..." group.word 0x978++0x1 line.word 0x00 "RIC_RESIN1212,DMA[11] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_1,EXT_IRQ_9,EXT_IRQ_17,?..." group.word 0x97A++0x1 line.word 0x00 "RIC_RESIN1213,DMA[12] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_2,EXT_IRQ_10,EXT_IRQ_18,?..." group.word 0x97C++0x1 line.word 0x00 "RIC_RESIN1214,DMA[13] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_3,EXT_IRQ_11,EXT_IRQ_19,?..." group.word 0x97E++0x1 line.word 0x00 "RIC_RESIN1215,DMA[14] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_4,EXT_IRQ_12,EXT_IRQ_20,?..." group.word 0x980++0x1 line.word 0x00 "RIC_RESIN1216,DMA[15] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_5,EXT_IRQ_13,EXT_IRQ_21,?..." group.word 0x982++0x1 line.word 0x00 "RIC_RESIN1217,DMA[16] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_6,EXT_IRQ_14,EXT_IRQ_22,?..." group.word 0x984++0x1 line.word 0x00 "RIC_RESIN1218,DMA[17] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "EXT_IRQ_7,EXT_IRQ_15,EXT_IRQ_23,?..." group.word 0x986++0x1 line.word 0x00 "RIC_RESIN1219,DMA[56] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_IRQ-0,BT0_IRQ-1,BT24_IRQ-0,BT24_IRQ-1,?..." group.word 0x988++0x1 line.word 0x00 "RIC_RESIN1220,DMA[57] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT1_IRQ-0,BT1_IRQ-1,BT25_IRQ-0,BT25_IRQ-1,?..." group.word 0x98A++0x1 line.word 0x00 "RIC_RESIN1221,DMA[58] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT2_IRQ-0,BT2_IRQ-1,BT26_IRQ-0,BT26_IRQ-1,?..." group.word 0x98C++0x1 line.word 0x00 "RIC_RESIN1222,DMA[59] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT3_IRQ-0,BT3_IRQ-1,BT27_IRQ-0,BT27_IRQ-1,?..." group.word 0x98E++0x1 line.word 0x00 "RIC_RESIN1223,DMA[60] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT4_IRQ-0,BT4_IRQ-1,BT28_IRQ-0,BT28_IRQ-1,?..." group.word 0x990++0x1 line.word 0x00 "RIC_RESIN1224,DMA[61] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT5_IRQ-0,BT5_IRQ-1,BT29_IRQ-0,BT29_IRQ-1,?..." group.word 0x992++0x1 line.word 0x00 "RIC_RESIN1225,DMA[62] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT6_IRQ-0,BT6_IRQ-1,BT30_IRQ-0,BT30_IRQ-1,?..." group.word 0x994++0x1 line.word 0x00 "RIC_RESIN1226,DMA[63] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT7_IRQ-0,BT7_IRQ-1,BT31_IRQ-0,BT31_IRQ-1,?..." group.word 0x996++0x1 line.word 0x00 "RIC_RESIN1227,DMA[64] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT8_IRQ-0,BT8_IRQ-1,?..." group.word 0x998++0x1 line.word 0x00 "RIC_RESIN1228,DMA[65] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT9_IRQ-0,BT9_IRQ-1,?..." group.word 0x99A++0x1 line.word 0x00 "RIC_RESIN1229,DMA[66] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT10_IRQ-0,BT10_IRQ-1,?..." group.word 0x99C++0x1 line.word 0x00 "RIC_RESIN1230,DMA[67] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT11_IRQ-0,BT11_IRQ-1,?..." group.word 0x99E++0x1 line.word 0x00 "RIC_RESIN1231,DMA[68] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT12_IRQ-0,BT12_IRQ-1,?..." group.word 0x9A0++0x1 line.word 0x00 "RIC_RESIN1232,DMA[69] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT13_IRQ-0,BT13_IRQ-1,?..." group.word 0x9A2++0x1 line.word 0x00 "RIC_RESIN1233,DMA[70] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT14_IRQ-0,BT14_IRQ-1,?..." group.word 0x9A4++0x1 line.word 0x00 "RIC_RESIN1234,DMA[71] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT15_IRQ-0,BT15_IRQ-1,?..." group.word 0x9A6++0x1 line.word 0x00 "RIC_RESIN1235,DMA[72] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_IRQ-0,BT16_IRQ-1,?..." group.word 0x9A8++0x1 line.word 0x00 "RIC_RESIN1236,DMA[73] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT17_IRQ-0,BT17_IRQ-1,?..." group.word 0x9AA++0x1 line.word 0x00 "RIC_RESIN1237,DMA[74] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT18_IRQ-0,BT18_IRQ-1,?..." group.word 0x9AC++0x1 line.word 0x00 "RIC_RESIN1238,DMA[75] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT19_IRQ-0,BT19_IRQ-1,?..." group.word 0x9AE++0x1 line.word 0x00 "RIC_RESIN1239,DMA[76] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT20_IRQ-0,BT20_IRQ-1,?..." group.word 0x9B0++0x1 line.word 0x00 "RIC_RESIN1240,DMA[77] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT21_IRQ-0,BT21_IRQ-1,?..." group.word 0x9B2++0x1 line.word 0x00 "RIC_RESIN1241,DMA[78] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT22_IRQ-0,BT22_IRQ-1,?..." group.word 0x9B4++0x1 line.word 0x00 "RIC_RESIN1242,DMA[79] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT23_IRQ-0,BT23_IRQ-1,?..." group.word 0x9B6++0x1 line.word 0x00 "RIC_RESIN1243,DMA[80] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0_MATCH,FRT0_ZERO,FRT2_MATCH,FRT2_ZERO,FRT4_MATCH,FRT4_ZERO,?..." group.word 0x9B8++0x1 line.word 0x00 "RIC_RESIN1244,DMA[81] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT1_MATCH,FRT1_ZERO,FRT3_MATCH,FRT3_ZERO,?..." group.word 0x9BA++0x1 line.word 0x00 "RIC_RESIN1245,DMA[82] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8_MATCH,FRT8_ZERO,FRT10_MATCH,FRT10_ZERO,?..." group.word 0x9BC++0x1 line.word 0x00 "RIC_RESIN1246,DMA[83] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT9_MATCH,FRT9_ZERO,?..." group.word 0x9BE++0x1 line.word 0x00 "RIC_RESIN1247,DMA[84] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "ICU0_IRQ0,ICU2_IRQ0,ICU4_IRQ0,?..." group.word 0x9C0++0x1 line.word 0x00 "RIC_RESIN1248,DMA[85] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "ICU16_IRQ0,ICU18_IRQ0,ICU20_IRQ0,?..." group.word 0x9C2++0x1 line.word 0x00 "RIC_RESIN1249,DMA[86] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "ICU1_IRQ1,ICU3_IRQ1,ICU5_IRQ1,?..." group.word 0x9C4++0x1 line.word 0x00 "RIC_RESIN1250,DMA[87] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "ICU17_IRQ1,ICU19_IRQ1,ICU21_IRQ1,?..." group.word 0x9C6++0x1 line.word 0x00 "RIC_RESIN1251,DMA[88] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "OCU0_IRQ0,OCU2_IRQ0,OCU4_IRQ0,?..." group.word 0x9C8++0x1 line.word 0x00 "RIC_RESIN1252,DMA[89] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "OCU16_IRQ0,OCU18_IRQ0,OCU20_IRQ0,?..." group.word 0x9CA++0x1 line.word 0x00 "RIC_RESIN1253,DMA[90] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "OCU1_IRQ1,OCU3_IRQ1,OCU5_IRQ1,?..." group.word 0x9CC++0x1 line.word 0x00 "RIC_RESIN1254,DMA[91] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "OCU17_IRQ1,OCU19_IRQ1,OCU21_IRQ1,?..." group.word 0x9CE++0x1 line.word 0x00 "RIC_RESIN1255,DMA[92] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "RLT0_IRQ,RLT2_IRQ,RLT16_IRQ,?..." group.word 0x9D0++0x1 line.word 0x00 "RIC_RESIN1256,DMA[93] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "RLT1_IRQ,RLT3_IRQ,RLT17_IRQ,?..." group.word 0x9D2++0x1 line.word 0x00 "RIC_RESIN1257,DMA[94] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "DMAC_RLT0,DMAC_RLT1,DMAC_RLT2,DMAC_RLT3,?..." newline group.long 0x1400++0x3 line.long 0x00 "RIC_KEYCDR,RIC Key Code Register" bitfld.long 0x00 30.--31. " KEY ,Key code bits" "1,2,3,4" bitfld.long 0x00 28.--29. " SIZE ,Access size bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x00 0.--14. 0x01 " RADR ,Port address bits" width 0x0B tree.end else tree "RIC" base ad:0xB4748000 width 14. sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x00++0x1 line.word 0x00 "RIC_RESIN0,SIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,P4_19,?..." group.word 0x02++0x1 line.word 0x00 "RIC_RESIN1,SCK16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P4_21,?..." else group.word 0x00++0x1 line.word 0x00 "RIC_RESIN0,SIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,,?..." group.word 0x02++0x1 line.word 0x00 "RIC_RESIN1,SCK16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,,?..." endif group.word 0x04++0x1 line.word 0x00 "RIC_RESIN2,SCL16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x06++0x1 line.word 0x00 "RIC_RESIN3,SDA16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x08++0x1 line.word 0x00 "RIC_RESIN4,MFS16_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT48,TOT49,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x0A++0x1 line.word 0x00 "RIC_RESIN5,SCS16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,P4_23,?..." else group.word 0x0A++0x1 line.word 0x00 "RIC_RESIN5,SCS16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,,?..." endif group.word 0x0E++0x1 line.word 0x00 "RIC_RESIN7,SIN17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P0_09,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x10++0x1 line.word 0x00 "RIC_RESIN8,SCK17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,P4_04,?..." else group.word 0x10++0x1 line.word 0x00 "RIC_RESIN8,SCK17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,,?..." endif group.word 0x12++0x1 line.word 0x00 "RIC_RESIN9,SCL17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x14++0x1 line.word 0x00 "RIC_RESIN10,SDA17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x16++0x1 line.word 0x00 "RIC_RESIN11,MFS17_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT48,TOT49,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x18++0x1 line.word 0x00 "RIC_RESIN12,SCS17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,P4_03,?..." else group.word 0x18++0x1 line.word 0x00 "RIC_RESIN12,SCS17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,,?..." endif group.word 0x2A++0x1 line.word 0x00 "RIC_RESIN21,SIN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P0_04,?..." group.word 0x2C++0x1 line.word 0x00 "RIC_RESIN22,SCK0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,P0_06,?..." group.word 0x2E++0x1 line.word 0x00 "RIC_RESIN23,SCL0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x30++0x1 line.word 0x00 "RIC_RESIN24,SDA0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x32++0x1 line.word 0x00 "RIC_RESIN25,MFS0_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,?..." group.word 0x34++0x1 line.word 0x00 "RIC_RESIN26,SCS0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,P0_07,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x38++0x1 line.word 0x00 "RIC_RESIN28,SIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_01,P3_00,?..." group.word 0x3A++0x1 line.word 0x00 "RIC_RESIN29,SCK1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_02,P3_01,?..." else group.word 0x38++0x1 line.word 0x00 "RIC_RESIN28,SIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_01,,?..." group.word 0x3A++0x1 line.word 0x00 "RIC_RESIN29,SCK1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_02,,?..." endif group.word 0x3C++0x1 line.word 0x00 "RIC_RESIN30,SCL1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x3E++0x1 line.word 0x00 "RIC_RESIN31,SDA1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x40++0x1 line.word 0x00 "RIC_RESIN32,MFS1_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x42++0x1 line.word 0x00 "RIC_RESIN33,SCS1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_04,P3_03,?..." sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x46++0x1 line.word 0x00 "RIC_RESIN35,SIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,P4_30,?..." group.word 0x48++0x1 line.word 0x00 "RIC_RESIN36,SCK2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_22,P4_31,?..." else group.word 0x46++0x1 line.word 0x00 "RIC_RESIN35,SIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,,?..." group.word 0x48++0x1 line.word 0x00 "RIC_RESIN36,SCK2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_22,,?..." endif else group.word 0x42++0x1 line.word 0x00 "RIC_RESIN33,SCS1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_04,,?..." group.word 0x46++0x1 line.word 0x00 "RIC_RESIN35,SIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,,?..." group.word 0x48++0x1 line.word 0x00 "RIC_RESIN36,SCK2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_22,,?..." endif group.word 0x4E++0x1 line.word 0x00 "RIC_RESIN39,MFS2_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x50++0x1 line.word 0x00 "RIC_RESIN40,SCS2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_24,P3_25,?..." group.word 0x54++0x1 line.word 0x00 "RIC_RESIN42,SIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,P3_28,?..." group.word 0x56++0x1 line.word 0x00 "RIC_RESIN43,SCK3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_29,P3_29,?..." else group.word 0x50++0x1 line.word 0x00 "RIC_RESIN40,SCS2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_24,,?..." group.word 0x54++0x1 line.word 0x00 "RIC_RESIN42,SIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,,?..." group.word 0x56++0x1 line.word 0x00 "RIC_RESIN43,SCK3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_29,,?..." endif group.word 0x5C++0x1 line.word 0x00 "RIC_RESIN46,MFS3_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x5E++0x1 line.word 0x00 "RIC_RESIN47,SCS3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,P3_31,?..." group.word 0x62++0x1 line.word 0x00 "RIC_RESIN49,SIN4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_13,P3_05,?..." else group.word 0x5E++0x1 line.word 0x00 "RIC_RESIN47,SCS3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,,?..." group.word 0x62++0x1 line.word 0x00 "RIC_RESIN49,SIN4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_13,,?..." endif group.word 0x64++0x1 line.word 0x00 "RIC_RESIN50,SCK4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_14,P0_14,?..." group.word 0x66++0x1 line.word 0x00 "RIC_RESIN51,SCL4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x68++0x1 line.word 0x00 "RIC_RESIN52,SDA4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x6A++0x1 line.word 0x00 "RIC_RESIN53,MFS4_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,?..." group.word 0x6C++0x1 line.word 0x00 "RIC_RESIN54,SCS4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_16,P0_15,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x9A++0x1 line.word 0x00 "RIC_RESIN77,SIN8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,P3_08,P0_27,?..." group.word 0x9C++0x1 line.word 0x00 "RIC_RESIN78,SCK8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_20,P3_09,P0_28,?..." else group.word 0x9A++0x1 line.word 0x00 "RIC_RESIN77,SIN8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,,P0_27,?..." group.word 0x9C++0x1 line.word 0x00 "RIC_RESIN78,SCK8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_20,,P0_28,?..." endif group.word 0x9E++0x1 line.word 0x00 "RIC_RESIN79,SCL8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xA0++0x1 line.word 0x00 "RIC_RESIN80,SDA8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xA2++0x1 line.word 0x00 "RIC_RESIN81,MFS8_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0xA4++0x1 line.word 0x00 "RIC_RESIN82,SCS8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,P3_11,P0_30,?..." group.word 0xA8++0x1 line.word 0x00 "RIC_RESIN84,SIN9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,P3_18,P0_21,?..." group.word 0xAA++0x1 line.word 0x00 "RIC_RESIN85,SCK9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_24,P3_19,P0_23,?..." else group.word 0xA4++0x1 line.word 0x00 "RIC_RESIN82,SCS8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_22,,P0_30,?..." group.word 0xA8++0x1 line.word 0x00 "RIC_RESIN84,SIN9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,,P0_21,?..." group.word 0xAA++0x1 line.word 0x00 "RIC_RESIN85,SCK9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_24,,P0_23,?..." endif group.word 0xAC++0x1 line.word 0x00 "RIC_RESIN86,SCL9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xAE++0x1 line.word 0x00 "RIC_RESIN87,SDA9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xB0++0x1 line.word 0x00 "RIC_RESIN88,MFS9_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0xB2++0x1 line.word 0x00 "RIC_RESIN89,SCS9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_26,P3_21,P0_24,?..." group.word 0xB6++0x1 line.word 0x00 "RIC_RESIN91,SIN10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_28,P3_12,?..." group.word 0xB8++0x1 line.word 0x00 "RIC_RESIN92,SCK10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_13,?..." else group.word 0xB2++0x1 line.word 0x00 "RIC_RESIN89,SCS9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_26,,P0_24,?..." group.word 0xB6++0x1 line.word 0x00 "RIC_RESIN91,SIN10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_28,,?..." group.word 0xB8++0x1 line.word 0x00 "RIC_RESIN92,SCK10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." endif group.word 0xBA++0x1 line.word 0x00 "RIC_RESIN93,SCL10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xBC++0x1 line.word 0x00 "RIC_RESIN94,SDA10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x0BE++0x1 line.word 0x00 "RIC_RESIN95,MFS10_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0xC0++0x1 line.word 0x00 "RIC_RESIN96,SCS10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,P3_15,?..." else group.word 0xC0++0x1 line.word 0x00 "RIC_RESIN96,SCS10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_31,,?..." endif group.word 0xC8++0x1 line.word 0x00 "RIC_RESIN100,SCL11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xCA++0x1 line.word 0x00 "RIC_RESIN101,SDA11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0x0CC++0x1 line.word 0x00 "RIC_RESIN102,MFS11_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")&&!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0xD2++0x1 line.word 0x00 "RIC_RESIN105,SIN12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_05,P4_18,?..." else group.word 0xD2++0x1 line.word 0x00 "RIC_RESIN105,SIN12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_05,,?..." endif group.word 0xD4++0x1 line.word 0x00 "RIC_RESIN106,SCK12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,P1_15,?..." group.word 0xD6++0x1 line.word 0x00 "RIC_RESIN107,SCL12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xD8++0x1 line.word 0x00 "RIC_RESIN108,SDA12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." group.word 0xDA++0x1 line.word 0x00 "RIC_RESIN109,MFS12_TRIGGER Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0xDC++0x1 line.word 0x00 "RIC_RESIN110,SCS12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_08,P3_23,?..." group.word 0x10A++0x1 line.word 0x00 "RIC_RESIN133,RX5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,P3_19,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN5_PIN_AND_TX,?..." group.word 0x10C++0x1 line.word 0x00 "RIC_RESIN134,RX6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_21,P3_22,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN6_PIN_AND_TX,?..." sif cpuis("S6J335???") sif (!cpuis("S6J335?J?")) group.word 0x10E++0x1 line.word 0x00 "RIC_RESIN135,RX7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P4_22,P2_18,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN7_PIN_AND_TX,?..." else group.word 0x10E++0x1 line.word 0x00 "RIC_RESIN135,RX7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" ",P2_18,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN7_PIN_AND_TX,?..." endif endif sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x110++0x1 line.word 0x00 "RIC_RESIN136,RX0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_09,P4_00,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN0_PIN_AND_TX,?..." else group.word 0x110++0x1 line.word 0x00 "RIC_RESIN136,RX0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_09,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN0_PIN_AND_TX,?..." endif group.word 0x112++0x1 line.word 0x00 "RIC_RESIN137,RX1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P3_11,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN1_PIN_AND_TX,?..." group.word 0x114++0x1 line.word 0x00 "RIC_RESIN138,RX2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,P3_14,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN2_PIN_AND_TX,?..." sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x116++0x1 line.word 0x00 "RIC_RESIN139,RX3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,P3_16,P4_03,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN3_PIN_AND_TX,?..." else group.word 0x116++0x1 line.word 0x00 "RIC_RESIN139,RX3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,P3_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN3_PIN_AND_TX,?..." endif sif cpuis("S6J335???") group.word 0x118++0x1 line.word 0x00 "RIC_RESIN140,RX4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN4_PIN_AND_TX,?..." endif group.word 0x11A++0x1 line.word 0x00 "RIC_RESIN141,TIN48 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,P3_16,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT49,RLT49_UFSET,?..." group.word 0x11C++0x1 line.word 0x00 "RIC_RESIN142,TIN49 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT48,RLT48_UFSET,?..." group.word 0x11E++0x1 line.word 0x00 "RIC_RESIN143,TIN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P3_08,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,RLT1_UFSET,,PPG0_TOUT0,?..." group.word 0x122++0x1 line.word 0x00 "RIC_RESIN145,TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_10,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,,PPG1_TOUT0,?..." group.word 0x140++0x1 line.word 0x00 "RIC_RESIN160,TIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P3_12,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT17,RLT17_UFSET,,PPG6_TOUT0,?..." group.word 0x142++0x1 line.word 0x00 "RIC_RESIN161,TIN17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,P3_14,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,,PPG7_TOUT0,?..." group.word 0x180++0x1 line.word 0x00 "RIC_RESIN192,EINT0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_13,P0_00,P0_08,P0_20,P3_17,P2_01,P2_16,?..." sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x182++0x1 line.word 0x00 "RIC_RESIN193,EINT1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_01,P3_00,P0_09,P0_22,P4_16,P4_27,P2_17,?..." group.word 0x184++0x1 line.word 0x00 "RIC_RESIN194,EINT2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,P4_30,P4_03,P0_23,P3_20,P2_02,P2_18,?..." group.word 0x186++0x1 line.word 0x00 "RIC_RESIN195,EINT3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,P3_28,P4_04,P0_24,P3_21,P2_03,P2_19,?..." group.word 0x188++0x1 line.word 0x00 "RIC_RESIN196,EINT4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P0_02,P4_05,P0_25,P3_23,P2_04,?..." group.word 0x18A++0x1 line.word 0x00 "RIC_RESIN197,EINT5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,P0_03,P0_10,P0_26,P4_17,P4_28,?..." group.word 0x18C++0x1 line.word 0x00 "RIC_RESIN198,EINT6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_09,P0_11,P0_27,P4_18,P2_06,?..." group.word 0x18E++0x1 line.word 0x00 "RIC_RESIN199,EINT7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,P4_00,P0_12,P0_29,P4_20,P2_07,?..." group.word 0x190++0x1 line.word 0x00 "RIC_RESIN200,EINT8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P3_11,P0_13,P0_30,P4_21,P4_29,?..." group.word 0x192++0x1 line.word 0x00 "RIC_RESIN201,EINT9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,P4_01,P3_01,P0_31,P1_16,P2_08,?..." group.word 0x194++0x1 line.word 0x00 "RIC_RESIN202,EINT10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P4_02,P3_02,P1_00,P4_23,P4_31,?..." group.word 0x196++0x1 line.word 0x00 "RIC_RESIN203,EINT11 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,P0_04,P3_03,P1_01,P1_18,P3_24,?..." group.word 0x198++0x1 line.word 0x00 "RIC_RESIN204,EINT12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,P3_14,P3_04,P1_02,P1_20,P3_25,?..." group.word 0x19A++0x1 line.word 0x00 "RIC_RESIN205,EINT13 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,P0_05,P4_06,P4_08,P1_22,P3_26,?..." group.word 0x19C++0x1 line.word 0x00 "RIC_RESIN206,EINT14 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,P3_16,P4_07,P4_09,P1_24,P3_27,?..." group.word 0x19E++0x1 line.word 0x00 "RIC_RESIN207,EINT15 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P0_06,P3_05,P4_10,P1_25,P2_09,?..." group.word 0x1A0++0x1 line.word 0x00 "RIC_RESIN208,EINT16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,P4_19,P3_06,P4_11,P4_24,P3_29,?..." group.word 0x1A2++0x1 line.word 0x00 "RIC_RESIN209,EINT17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,P3_19,P0_14,P3_10,P1_26,P3_30,?..." group.word 0x1A4++0x1 line.word 0x00 "RIC_RESIN210,EINT18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,P3_08,P0_15,P3_13,P1_27,P3_31,?..." group.word 0x1A6++0x1 line.word 0x00 "RIC_RESIN211,EINT19 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_21,P3_22,P0_16,P3_15,P4_25,P2_10,?..." group.word 0x1A8++0x1 line.word 0x00 "RIC_RESIN212,EINT20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,P3_18,P3_07,P4_12,P1_29,P2_11,?..." group.word 0x1AA++0x1 line.word 0x00 "RIC_RESIN213,EINT21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_28,P3_12,P0_17,P4_13,P1_30,P2_12,?..." group.word 0x1AC++0x1 line.word 0x00 "RIC_RESIN214,EINT22 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_00,P4_22,P0_18,P4_14,P1_31,P2_14,?..." group.word 0x1AE++0x1 line.word 0x00 "RIC_RESIN215,EINT23 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_05,P0_07,P0_19,P4_15,P4_26,P2_15,?..." else group.word 0x182++0x1 line.word 0x00 "RIC_RESIN193,EINT1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_01,P3_00,P0_09,P0_22,,,P2_17,?..." group.word 0x184++0x1 line.word 0x00 "RIC_RESIN194,EINT2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,,,P0_23,P3_20,P2_02,P2_18,?..." group.word 0x186++0x1 line.word 0x00 "RIC_RESIN195,EINT3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,P3_28,,P0_24,P3_21,P2_03,P2_19,?..." group.word 0x188++0x1 line.word 0x00 "RIC_RESIN196,EINT4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P0_02,,P0_25,P3_23,P2_04,?..." group.word 0x18A++0x1 line.word 0x00 "RIC_RESIN197,EINT5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,P0_03,P0_10,P0_26,,,?..." group.word 0x18C++0x1 line.word 0x00 "RIC_RESIN198,EINT6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_09,P0_11,P0_27,,P2_06,?..." group.word 0x18E++0x1 line.word 0x00 "RIC_RESIN199,EINT7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,,P0_12,P0_29,,P2_07,?..." group.word 0x190++0x1 line.word 0x00 "RIC_RESIN200,EINT8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P3_11,P0_13,P0_30,,,?..." group.word 0x192++0x1 line.word 0x00 "RIC_RESIN201,EINT9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,,P3_01,P0_31,P1_16,P2_08,?..." group.word 0x194++0x1 line.word 0x00 "RIC_RESIN202,EINT10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,,P3_02,P1_00,,,?..." group.word 0x196++0x1 line.word 0x00 "RIC_RESIN203,EINT11 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,P0_04,P3_03,P1_01,P1_18,P3_24,?..." group.word 0x198++0x1 line.word 0x00 "RIC_RESIN204,EINT12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,P3_14,P3_04,P1_02,P1_20,P3_25,?..." group.word 0x19A++0x1 line.word 0x00 "RIC_RESIN205,EINT13 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,P0_05,,,P1_22,P3_26,?..." group.word 0x19C++0x1 line.word 0x00 "RIC_RESIN206,EINT14 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,P3_16,,,P1_24,P3_27,?..." group.word 0x19E++0x1 line.word 0x00 "RIC_RESIN207,EINT15 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P0_06,P3_05,,P1_25,P2_09,?..." group.word 0x1A0++0x1 line.word 0x00 "RIC_RESIN208,EINT16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,,P3_06,,,P3_29,?..." group.word 0x1A2++0x1 line.word 0x00 "RIC_RESIN209,EINT17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,P3_19,P0_14,P3_10,P1_26,P3_30,?..." group.word 0x1A4++0x1 line.word 0x00 "RIC_RESIN210,EINT18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,P3_08,P0_15,P3_13,P1_27,P3_31,?..." group.word 0x1A6++0x1 line.word 0x00 "RIC_RESIN211,EINT19 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_21,P3_22,P0_16,P3_15,,P2_10,?..." group.word 0x1A8++0x1 line.word 0x00 "RIC_RESIN212,EINT20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,P3_18,P3_07,,P1_29,P2_11,?..." group.word 0x1AA++0x1 line.word 0x00 "RIC_RESIN213,EINT21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_28,P3_12,P0_17,,P1_30,P2_12,?..." group.word 0x1AC++0x1 line.word 0x00 "RIC_RESIN214,EINT22 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_00,,P0_18,,P1_31,P2_14,?..." group.word 0x1AE++0x1 line.word 0x00 "RIC_RESIN215,EINT23 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_05,P0_07,P0_19,,,P2_15,?..." endif else group.word 0xDC++0x1 line.word 0x00 "RIC_RESIN110,SCS12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_08,,?..." group.word 0x10A++0x1 line.word 0x00 "RIC_RESIN133,RX5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN5_PIN_AND_TX,?..." group.word 0x10C++0x1 line.word 0x00 "RIC_RESIN134,RX6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_21,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN6_PIN_AND_TX,?..." sif cpuis("S6J335???") group.word 0x10E++0x1 line.word 0x00 "RIC_RESIN135,RX7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" ",P2_18,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN7_PIN_AND_TX,?..." endif group.word 0x110++0x1 line.word 0x00 "RIC_RESIN136,RX0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN0_PIN_AND_TX,?..." group.word 0x112++0x1 line.word 0x00 "RIC_RESIN137,RX1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN1_PIN_AND_TX,?..." group.word 0x114++0x1 line.word 0x00 "RIC_RESIN138,RX2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN2_PIN_AND_TX,?..." group.word 0x116++0x1 line.word 0x00 "RIC_RESIN139,RX3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN3_PIN_AND_TX,?..." sif cpuis("S6J335???") group.word 0x118++0x1 line.word 0x00 "RIC_RESIN140,RX4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MCAN4_PIN_AND_TX,?..." endif group.word 0x11A++0x1 line.word 0x00 "RIC_RESIN141,TIN48 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT49,RLT49_UFSET,?..." group.word 0x11C++0x1 line.word 0x00 "RIC_RESIN142,TIN49 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT48,RLT48_UFSET,?..." group.word 0x11E++0x1 line.word 0x00 "RIC_RESIN143,TIN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,RLT1_UFSET,,PPG0_TOUT0,?..." group.word 0x122++0x1 line.word 0x00 "RIC_RESIN145,TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,,PPG1_TOUT0,?..." group.word 0x140++0x1 line.word 0x00 "RIC_RESIN160,TIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT17,RLT17_UFSET,,PPG6_TOUT0,?..." group.word 0x142++0x1 line.word 0x00 "RIC_RESIN161,TIN17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,,PPG7_TOUT0,?..." group.word 0x180++0x1 line.word 0x00 "RIC_RESIN192,EINT0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_13,P0_00,P0_08,P0_20,,P2_01,P2_16,?..." group.word 0x182++0x1 line.word 0x00 "RIC_RESIN193,EINT1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_01,,P0_09,P0_22,,,P2_17,?..." group.word 0x184++0x1 line.word 0x00 "RIC_RESIN194,EINT2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_21,,,P0_23,,P2_02,P2_18,?..." group.word 0x186++0x1 line.word 0x00 "RIC_RESIN195,EINT3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,,,P0_24,,P2_03,P2_19,?..." group.word 0x188++0x1 line.word 0x00 "RIC_RESIN196,EINT4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P0_02,,P0_25,,P2_04,?..." group.word 0x18A++0x1 line.word 0x00 "RIC_RESIN197,EINT5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,P0_03,P0_10,P0_26,,,?..." group.word 0x18C++0x1 line.word 0x00 "RIC_RESIN198,EINT6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,,P0_11,P0_27,,P2_06,?..." group.word 0x18E++0x1 line.word 0x00 "RIC_RESIN199,EINT7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,,P0_12,P0_29,,P2_07,?..." group.word 0x190++0x1 line.word 0x00 "RIC_RESIN200,EINT8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,,P0_13,P0_30,,,?..." group.word 0x192++0x1 line.word 0x00 "RIC_RESIN201,EINT9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,,,P0_31,P1_16,P2_08,?..." group.word 0x194++0x1 line.word 0x00 "RIC_RESIN202,EINT10 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,,,P1_00,,,?..." group.word 0x196++0x1 line.word 0x00 "RIC_RESIN203,EINT11 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,P0_04,,P1_01,P1_18,,?..." group.word 0x198++0x1 line.word 0x00 "RIC_RESIN204,EINT12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,,,P1_02,P1_20,,?..." group.word 0x19A++0x1 line.word 0x00 "RIC_RESIN205,EINT13 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,P0_05,,,P1_22,,?..." group.word 0x19C++0x1 line.word 0x00 "RIC_RESIN206,EINT14 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_13,,,,P1_24,,?..." group.word 0x19E++0x1 line.word 0x00 "RIC_RESIN207,EINT15 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P0_06,,,P1_25,P2_09,?..." group.word 0x1A0++0x1 line.word 0x00 "RIC_RESIN208,EINT16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,?..." group.word 0x1A2++0x1 line.word 0x00 "RIC_RESIN209,EINT17 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_17,,P0_14,,P1_26,,?..." group.word 0x1A4++0x1 line.word 0x00 "RIC_RESIN210,EINT18 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_19,,P0_15,,P1_27,,?..." group.word 0x1A6++0x1 line.word 0x00 "RIC_RESIN211,EINT19 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_21,,P0_16,,,P2_10,?..." group.word 0x1A8++0x1 line.word 0x00 "RIC_RESIN212,EINT20 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_23,,,,P1_29,P2_11,?..." group.word 0x1AA++0x1 line.word 0x00 "RIC_RESIN213,EINT21 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_28,,P0_17,,P1_30,P2_12,?..." group.word 0x1AC++0x1 line.word 0x00 "RIC_RESIN214,EINT22 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_00,,P0_18,,P1_31,P2_14,?..." group.word 0x1AE++0x1 line.word 0x00 "RIC_RESIN215,EINT23 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_05,P0_07,P0_19,,,P2_15,?..." endif group.word 0x1B0++0x1 line.word 0x00 "RIC_RESIN216,TEXT0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,PPG0_TOUT2,?..." group.word 0x1B2++0x1 line.word 0x00 "RIC_RESIN217,TEXT1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,PPG1_TOUT2,?..." group.word 0x1B4++0x1 line.word 0x00 "RIC_RESIN218,TEXT2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,PPG2_TOUT2,?..." group.word 0x1B6++0x1 line.word 0x00 "RIC_RESIN219,TEXT3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,PPG3_TOUT2,?..." group.word 0x1B8++0x1 line.word 0x00 "RIC_RESIN220,TEXT4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,PPG4_TOUT2,?..." group.word 0x1C0++0x1 line.word 0x00 "RIC_RESIN224,TEXT8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,PPG6_TOUT2,?..." group.word 0x1C2++0x1 line.word 0x00 "RIC_RESIN225,TEXT9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,PPG7_TOUT2,?..." group.word 0x1C4++0x1 line.word 0x00 "RIC_RESIN226,TEXT10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,PPG8_TOUT2,?..." group.word 0x1D0++0x1 line.word 0x00 "RIC_RESIN232,OCU0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x1D2++0x1 line.word 0x00 "RIC_RESIN233,OCU0_MOD0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x1D4++0x1 line.word 0x00 "RIC_RESIN234,OCU0_MOD1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x1D6++0x1 line.word 0x00 "RIC_RESIN235,OCU1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x1D8++0x1 line.word 0x00 "RIC_RESIN236,OCU1_MOD0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x1DA++0x1 line.word 0x00 "RIC_RESIN237,OCU1_MOD1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x1DC++0x1 line.word 0x00 "RIC_RESIN238,OCU2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x1DE++0x1 line.word 0x00 "RIC_RESIN239,OCU2_MOD0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x1E0++0x1 line.word 0x00 "RIC_RESIN240,OCU2_MOD1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x200++0x1 line.word 0x00 "RIC_RESIN256,OCU8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x202++0x1 line.word 0x00 "RIC_RESIN257,OCU8_MOD0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x204++0x1 line.word 0x00 "RIC_RESIN258,OCU8_MOD1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x206++0x1 line.word 0x00 "RIC_RESIN259,OCU9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x208++0x1 line.word 0x00 "RIC_RESIN260,OCU9_MOD0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x20A++0x1 line.word 0x00 "RIC_RESIN261,OCU9_MOD1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x20C++0x1 line.word 0x00 "RIC_RESIN262,OCU10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x20E++0x1 line.word 0x00 "RIC_RESIN263,OCU10_MOD0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x210++0x1 line.word 0x00 "RIC_RESIN264,OCU10_MOD1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x230++0x1 line.word 0x00 "RIC_RESIN280,ICU0_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,P3_08,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS0_LSYN,?..." group.word 0x232++0x1 line.word 0x00 "RIC_RESIN281,ICU0_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,P3_09,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS1_LSYN,?..." group.word 0x234++0x1 line.word 0x00 "RIC_RESIN282,ICU0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x236++0x1 line.word 0x00 "RIC_RESIN283,ICU1_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,P3_10,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS2_LSYN,?..." group.word 0x238++0x1 line.word 0x00 "RIC_RESIN284,ICU1_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,P3_11,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS3_LSYN,?..." group.word 0x23A++0x1 line.word 0x00 "RIC_RESIN285,ICU1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x23C++0x1 line.word 0x00 "RIC_RESIN286,ICU2_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,P3_12,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS4_LSYN,?..." group.word 0x23E++0x1 line.word 0x00 "RIC_RESIN287,ICU2_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,P3_13,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,?..." group.word 0x240++0x1 line.word 0x00 "RIC_RESIN288,ICU2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x260++0x1 line.word 0x00 "RIC_RESIN304,ICU8_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,P3_14,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS8_LSYN,?..." group.word 0x262++0x1 line.word 0x00 "RIC_RESIN305,ICU8_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,P3_15,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS9_LSYN,?..." group.word 0x264++0x1 line.word 0x00 "RIC_RESIN306,ICU8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x266++0x1 line.word 0x00 "RIC_RESIN307,ICU9_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,P3_16,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS10_LSYN,?..." group.word 0x268++0x1 line.word 0x00 "RIC_RESIN308,ICU9_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,P3_17,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS11_LSYN,?..." group.word 0x26A++0x1 line.word 0x00 "RIC_RESIN309,ICU9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x26C++0x1 line.word 0x00 "RIC_RESIN310,ICU10_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,P3_18,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS12_LSYN,?..." group.word 0x26E++0x1 line.word 0x00 "RIC_RESIN311,ICU10_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,P3_19,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,?..." else group.word 0x230++0x1 line.word 0x00 "RIC_RESIN280,ICU0_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_03,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS0_LSYN,?..." group.word 0x232++0x1 line.word 0x00 "RIC_RESIN281,ICU0_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_04,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS1_LSYN,?..." group.word 0x234++0x1 line.word 0x00 "RIC_RESIN282,ICU0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x236++0x1 line.word 0x00 "RIC_RESIN283,ICU1_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_05,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS2_LSYN,?..." group.word 0x238++0x1 line.word 0x00 "RIC_RESIN284,ICU1_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_06,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS3_LSYN,?..." group.word 0x23A++0x1 line.word 0x00 "RIC_RESIN285,ICU1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x23C++0x1 line.word 0x00 "RIC_RESIN286,ICU2_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_07,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS4_LSYN,?..." group.word 0x23E++0x1 line.word 0x00 "RIC_RESIN287,ICU2_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_08,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,?..." group.word 0x240++0x1 line.word 0x00 "RIC_RESIN288,ICU2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,?..." group.word 0x260++0x1 line.word 0x00 "RIC_RESIN304,ICU8_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_09,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS8_LSYN,?..." group.word 0x262++0x1 line.word 0x00 "RIC_RESIN305,ICU8_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_10,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS9_LSYN,?..." group.word 0x264++0x1 line.word 0x00 "RIC_RESIN306,ICU8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x266++0x1 line.word 0x00 "RIC_RESIN307,ICU9_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_11,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS10_LSYN,?..." group.word 0x268++0x1 line.word 0x00 "RIC_RESIN308,ICU9_IN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_12,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS11_LSYN,?..." group.word 0x26A++0x1 line.word 0x00 "RIC_RESIN309,ICU9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x26C++0x1 line.word 0x00 "RIC_RESIN310,ICU10_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_14,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS12_LSYN,?..." group.word 0x26E++0x1 line.word 0x00 "RIC_RESIN311,ICU10_IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_15,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,?..." endif group.word 0x270++0x1 line.word 0x00 "RIC_RESIN312,ICU10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,,?..." group.word 0x2C0++0x1 line.word 0x00 "RIC_RESIN352,AIN8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,?..." group.word 0x2C2++0x1 line.word 0x00 "RIC_RESIN353,BIN8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,?..." group.word 0x2C4++0x1 line.word 0x00 "RIC_RESIN354,ZIN8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,PPG6_TOUT0,PPG6_TOUT2,PPG7_TOUT0,?..." group.word 0x2C6++0x1 line.word 0x00 "RIC_RESIN355,AIN9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,?..." group.word 0x2C8++0x1 line.word 0x00 "RIC_RESIN356,BIN9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT17,?..." group.word 0x2CA++0x1 line.word 0x00 "RIC_RESIN357,ZIN9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,PPG6_TOUT0,PPG6_TOUT2,PPG7_TOUT0,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x2F0++0x1 line.word 0x00 "RIC_RESIN376,PPG0_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_04,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x2F2++0x1 line.word 0x00 "RIC_RESIN377,PPG0_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2F4++0x1 line.word 0x00 "RIC_RESIN378,PPG0_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2F6++0x1 line.word 0x00 "RIC_RESIN379,PPG1_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_04,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x2F8++0x1 line.word 0x00 "RIC_RESIN380,PPG1_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2FA++0x1 line.word 0x00 "RIC_RESIN381,PPG1_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2FC++0x1 line.word 0x00 "RIC_RESIN382,PPG2_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_04,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x2FE++0x1 line.word 0x00 "RIC_RESIN383,PPG2_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x300++0x1 line.word 0x00 "RIC_RESIN384,PPG2_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x302++0x1 line.word 0x00 "RIC_RESIN385,PPG3_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_04,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x304++0x1 line.word 0x00 "RIC_RESIN386,PPG3_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x306++0x1 line.word 0x00 "RIC_RESIN387,PPG3_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x308++0x1 line.word 0x00 "RIC_RESIN388,PPG3_TIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_04,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x30A++0x1 line.word 0x00 "RIC_RESIN389,PPG3_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x30C++0x1 line.word 0x00 "RIC_RESIN390,PPG4_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x30E++0x1 line.word 0x00 "RIC_RESIN391,PPG5_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P3_04,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x310++0x1 line.word 0x00 "RIC_RESIN392,PPG5_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x312++0x1 line.word 0x00 "RIC_RESIN393,PPG5_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x314++0x1 line.word 0x00 "RIC_RESIN394,PPG6_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x316++0x1 line.word 0x00 "RIC_RESIN395,PPG6_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x318++0x1 line.word 0x00 "RIC_RESIN396,PPG6_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x31A++0x1 line.word 0x00 "RIC_RESIN397,PPG7_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x31C++0x1 line.word 0x00 "RIC_RESIN398,PPG7_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x31E++0x1 line.word 0x00 "RIC_RESIN399,PPG7_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x320++0x1 line.word 0x00 "RIC_RESIN400,PPG8_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x322++0x1 line.word 0x00 "RIC_RESIN401,PPG8_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x324++0x1 line.word 0x00 "RIC_RESIN402,PPG8_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x326++0x1 line.word 0x00 "RIC_RESIN403,PPG9_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x328++0x1 line.word 0x00 "RIC_RESIN404,PPG9_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x32A++0x1 line.word 0x00 "RIC_RESIN405,PPG9_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x32C++0x1 line.word 0x00 "RIC_RESIN406,PPG10_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x32E++0x1 line.word 0x00 "RIC_RESIN407,PPG10_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x330++0x1 line.word 0x00 "RIC_RESIN408,PPG10_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x332++0x1 line.word 0x00 "RIC_RESIN409,PPG11_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,P3_20,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x334++0x1 line.word 0x00 "RIC_RESIN410,PPG11_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x336++0x1 line.word 0x00 "RIC_RESIN411,PPG11_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x35C++0x1 line.word 0x00 "RIC_RESIN430,PPG12_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,P3_31,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x35E++0x1 line.word 0x00 "RIC_RESIN431,PPG12_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x360++0x1 line.word 0x00 "RIC_RESIN432,PPG12_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x362++0x1 line.word 0x00 "RIC_RESIN433,PPG13_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,P3_31,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x364++0x1 line.word 0x00 "RIC_RESIN434,PPG13_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x366++0x1 line.word 0x00 "RIC_RESIN435,PPG13_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x368++0x1 line.word 0x00 "RIC_RESIN436,PPG14_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,P3_31,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x36A++0x1 line.word 0x00 "RIC_RESIN437,PPG14_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x36C++0x1 line.word 0x00 "RIC_RESIN438,PPG14_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x36E++0x1 line.word 0x00 "RIC_RESIN439,PPG15_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,P3_31,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." else group.word 0x2F0++0x1 line.word 0x00 "RIC_RESIN376,PPG0_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x2F2++0x1 line.word 0x00 "RIC_RESIN377,PPG0_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2F4++0x1 line.word 0x00 "RIC_RESIN378,PPG0_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2F6++0x1 line.word 0x00 "RIC_RESIN379,PPG1_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x2F8++0x1 line.word 0x00 "RIC_RESIN380,PPG1_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2FA++0x1 line.word 0x00 "RIC_RESIN381,PPG1_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x2FC++0x1 line.word 0x00 "RIC_RESIN382,PPG2_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x2FE++0x1 line.word 0x00 "RIC_RESIN383,PPG2_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x300++0x1 line.word 0x00 "RIC_RESIN384,PPG2_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x302++0x1 line.word 0x00 "RIC_RESIN385,PPG3_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x304++0x1 line.word 0x00 "RIC_RESIN386,PPG3_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x306++0x1 line.word 0x00 "RIC_RESIN387,PPG3_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x308++0x1 line.word 0x00 "RIC_RESIN388,PPG3_TIN3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x30A++0x1 line.word 0x00 "RIC_RESIN389,PPG3_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x30C++0x1 line.word 0x00 "RIC_RESIN390,PPG4_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x30E++0x1 line.word 0x00 "RIC_RESIN391,PPG5_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OCU0_OTD0,?..." group.word 0x310++0x1 line.word 0x00 "RIC_RESIN392,PPG5_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x312++0x1 line.word 0x00 "RIC_RESIN393,PPG5_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x314++0x1 line.word 0x00 "RIC_RESIN394,PPG6_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x316++0x1 line.word 0x00 "RIC_RESIN395,PPG6_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x318++0x1 line.word 0x00 "RIC_RESIN396,PPG6_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x31A++0x1 line.word 0x00 "RIC_RESIN397,PPG7_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x31C++0x1 line.word 0x00 "RIC_RESIN398,PPG7_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x31E++0x1 line.word 0x00 "RIC_RESIN399,PPG7_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x320++0x1 line.word 0x00 "RIC_RESIN400,PPG8_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x322++0x1 line.word 0x00 "RIC_RESIN401,PPG8_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x324++0x1 line.word 0x00 "RIC_RESIN402,PPG8_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x326++0x1 line.word 0x00 "RIC_RESIN403,PPG9_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x328++0x1 line.word 0x00 "RIC_RESIN404,PPG9_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x32A++0x1 line.word 0x00 "RIC_RESIN405,PPG9_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x32C++0x1 line.word 0x00 "RIC_RESIN406,PPG10_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x32E++0x1 line.word 0x00 "RIC_RESIN407,PPG10_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x330++0x1 line.word 0x00 "RIC_RESIN408,PPG10_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x332++0x1 line.word 0x00 "RIC_RESIN409,PPG11_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_29,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OCU8_OTD0,?..." group.word 0x334++0x1 line.word 0x00 "RIC_RESIN410,PPG11_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x336++0x1 line.word 0x00 "RIC_RESIN411,PPG11_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x35C++0x1 line.word 0x00 "RIC_RESIN430,PPG12_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x35E++0x1 line.word 0x00 "RIC_RESIN431,PPG12_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x360++0x1 line.word 0x00 "RIC_RESIN432,PPG12_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x362++0x1 line.word 0x00 "RIC_RESIN433,PPG13_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x364++0x1 line.word 0x00 "RIC_RESIN434,PPG13_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x366++0x1 line.word 0x00 "RIC_RESIN435,PPG13_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x368++0x1 line.word 0x00 "RIC_RESIN436,PPG14_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x36A++0x1 line.word 0x00 "RIC_RESIN437,PPG14_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x36C++0x1 line.word 0x00 "RIC_RESIN438,PPG14_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x36E++0x1 line.word 0x00 "RIC_RESIN439,PPG15_TIN1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P2_06,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." endif group.word 0x370++0x1 line.word 0x00 "RIC_RESIN440,PPG15_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x372++0x1 line.word 0x00 "RIC_RESIN441,PPG15_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." sif cpuis("S6J335???") group.word 0x374++0x1 line.word 0x00 "RIC_RESIN442,PPG16_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x376++0x1 line.word 0x00 "RIC_RESIN443,PPG16_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x378++0x1 line.word 0x00 "RIC_RESIN444,PPG16_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x37A++0x1 line.word 0x00 "RIC_RESIN445,PPG17_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x37C++0x1 line.word 0x00 "RIC_RESIN446,PPG17_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x37E++0x1 line.word 0x00 "RIC_RESIN447,PPG17_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x380++0x1 line.word 0x00 "RIC_RESIN448,PPG18_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x382++0x1 line.word 0x00 "RIC_RESIN449,PPG18_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x384++0x1 line.word 0x00 "RIC_RESIN450,PPG18_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x386++0x1 line.word 0x00 "RIC_RESIN451,PPG19_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x388++0x1 line.word 0x00 "RIC_RESIN452,PPG19_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x38A++0x1 line.word 0x00 "RIC_RESIN453,PPG19_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x38C++0x1 line.word 0x00 "RIC_RESIN454,PPG20_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x38E++0x1 line.word 0x00 "RIC_RESIN455,PPG20_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x390++0x1 line.word 0x00 "RIC_RESIN456,PPG20_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x392++0x1 line.word 0x00 "RIC_RESIN457,PPG21_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x394++0x1 line.word 0x00 "RIC_RESIN458,PPG21_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x396++0x1 line.word 0x00 "RIC_RESIN459,PPG21_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x398++0x1 line.word 0x00 "RIC_RESIN460,PPG22_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x39A++0x1 line.word 0x00 "RIC_RESIN461,PPG22_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x39C++0x1 line.word 0x00 "RIC_RESIN462,PPG22_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x39E++0x1 line.word 0x00 "RIC_RESIN463,PPG23_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3A0++0x1 line.word 0x00 "RIC_RESIN464,PPG23_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3A2++0x1 line.word 0x00 "RIC_RESIN465,PPG23_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3A4++0x1 line.word 0x00 "RIC_RESIN466,PPG24_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3A6++0x1 line.word 0x00 "RIC_RESIN467,PPG24_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3A8++0x1 line.word 0x00 "RIC_RESIN468,PPG24_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3AA++0x1 line.word 0x00 "RIC_RESIN469,PPG25_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3AC++0x1 line.word 0x00 "RIC_RESIN470,PPG25_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3AE++0x1 line.word 0x00 "RIC_RESIN471,PPG25_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B0++0x1 line.word 0x00 "RIC_RESIN472,PPG26_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3B2++0x1 line.word 0x00 "RIC_RESIN473,PPG26_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B4++0x1 line.word 0x00 "RIC_RESIN474,PPG26_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3B6++0x1 line.word 0x00 "RIC_RESIN475,PPG27_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3B8++0x1 line.word 0x00 "RIC_RESIN476,PPG27_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3BA++0x1 line.word 0x00 "RIC_RESIN477,PPG27_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3BC++0x1 line.word 0x00 "RIC_RESIN478,PPG28_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3BE++0x1 line.word 0x00 "RIC_RESIN479,PPG28_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C0++0x1 line.word 0x00 "RIC_RESIN480,PPG28_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C2++0x1 line.word 0x00 "RIC_RESIN481,PPG29_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3C4++0x1 line.word 0x00 "RIC_RESIN482,PPG29_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C6++0x1 line.word 0x00 "RIC_RESIN483,PPG29_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3C8++0x1 line.word 0x00 "RIC_RESIN484,PPG30_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3CA++0x1 line.word 0x00 "RIC_RESIN485,PPG30_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3CC++0x1 line.word 0x00 "RIC_RESIN486,PPG30_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3CE++0x1 line.word 0x00 "RIC_RESIN487,PPG31_TIN1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,?..." group.word 0x3D0++0x1 line.word 0x00 "RIC_RESIN488,PPG31_TIN2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." group.word 0x3D2++0x1 line.word 0x00 "RIC_RESIN489,PPG31_TIN3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Set 0,?..." endif group.word 0x3D4++0x1 line.word 0x00 "RIC_RESIN490,ADC12B0_HWTRG0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU1_OTD0,PPG0_TOUT0,PPG1_TOUT2,PPG3_TOUT2,?..." group.word 0x3D6++0x1 line.word 0x00 "RIC_RESIN491,ADC12B0_HWTRG1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU2_OTD0,PPG0_TOUT2,PPG2_TOUT0,PPG4_TOUT0,?..." group.word 0x3D8++0x1 line.word 0x00 "RIC_RESIN492,ADC12B0_HWTRG2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,PPG1_TOUT0,PPG2_TOUT2,PPG4_TOUT2,?..." group.word 0x3DA++0x1 line.word 0x00 "RIC_RESIN493,ADC12B0_HWTRG3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,PPG1_TOUT2,PPG3_TOUT0,PPG5_TOUT0,?..." group.word 0x3DC++0x1 line.word 0x00 "RIC_RESIN494,ADC12B0_HWTRG4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU10_OTD0,PPG2_TOUT0,PPG3_TOUT2,PPG5_TOUT2,?..." group.word 0x3DE++0x1 line.word 0x00 "RIC_RESIN495,ADC12B0_HWTRG5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU0_OTD0,PPG2_TOUT2,PPG4_TOUT0,PPG6_TOUT0,?..." group.word 0x3E0++0x1 line.word 0x00 "RIC_RESIN496,ADC12B0_HWTRG6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU2_OTD0,PPG3_TOUT0,PPG4_TOUT2,PPG6_TOUT2,?..." group.word 0x3E2++0x1 line.word 0x00 "RIC_RESIN497,ADC12B0_HWTRG7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU8_OTD0,PPG3_TOUT2,PPG5_TOUT0,PPG7_TOUT0,?..." group.word 0x3E4++0x1 line.word 0x00 "RIC_RESIN498,ADC12B0_HWTRG8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU9_OTD0,PPG4_TOUT0,PPG5_TOUT2,PPG7_TOUT2,?..." group.word 0x3E6++0x1 line.word 0x00 "RIC_RESIN499,ADC12B0_HWTRG9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU10_OTD0,PPG4_TOUT2,PPG6_TOUT0,PPG8_TOUT0,?..." group.word 0x3E8++0x1 line.word 0x00 "RIC_RESIN500,ADC12B0_HWTRG10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU0_OTD0,PPG5_TOUT0,PPG6_TOUT2,PPG8_TOUT2,?..." group.word 0x3EA++0x1 line.word 0x00 "RIC_RESIN501,ADC12B0_HWTRG11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU1_OTD0,PPG5_TOUT2,PPG7_TOUT0,PPG9_TOUT0,?..." group.word 0x3EC++0x1 line.word 0x00 "RIC_RESIN502,ADC12B0_HWTRG12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU8_OTD0,PPG6_TOUT0,PPG7_TOUT2,PPG9_TOUT2,?..." group.word 0x3EE++0x1 line.word 0x00 "RIC_RESIN503,ADC12B0_HWTRG13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU9_OTD0,PPG6_TOUT2,PPG8_TOUT0,PPG10_TOUT0,?..." group.word 0x3F0++0x1 line.word 0x00 "RIC_RESIN504,ADC12B0_HWTRG14 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU10_OTD0,PPG7_TOUT0,PPG8_TOUT2,PPG10_TOUT2,?..." group.word 0x3F2++0x1 line.word 0x00 "RIC_RESIN505,ADC12B0_HWTRG15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU0_OTD0,PPG7_TOUT2,PPG9_TOUT0,PPG11_TOUT0,?..." group.word 0x3F4++0x1 line.word 0x00 "RIC_RESIN506,ADC12B0_HWTRG16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU1_OTD0,PPG8_TOUT0,PPG9_TOUT2,PPG11_TOUT2,?..." group.word 0x3F6++0x1 line.word 0x00 "RIC_RESIN507,ADC12B0_HWTRG17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU2_OTD0,PPG8_TOUT2,PPG10_TOUT0,PPG12_TOUT0,?..." group.word 0x3F8++0x1 line.word 0x00 "RIC_RESIN508,ADC12B0_HWTRG18 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU9_OTD0,PPG9_TOUT0,PPG10_TOUT2,PPG12_TOUT2,?..." group.word 0x3FA++0x1 line.word 0x00 "RIC_RESIN509,ADC12B0_HWTRG19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU10_OTD0,PPG9_TOUT2,PPG11_TOUT0,PPG13_TOUT0,?..." group.word 0x3FC++0x1 line.word 0x00 "RIC_RESIN510,ADC12B0_HWTRG20 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU0_OTD0,PPG10_TOUT0,PPG11_TOUT2,PPG13_TOUT2,?..." group.word 0x3FE++0x1 line.word 0x00 "RIC_RESIN511,ADC12B0_HWTRG21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU1_OTD0,PPG10_TOUT2,PPG12_TOUT0,PPG14_TOUT0,?..." group.word 0x400++0x1 line.word 0x00 "RIC_RESIN512,ADC12B0_HWTRG22 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU2_OTD0,PPG11_TOUT0,PPG12_TOUT2,PPG14_TOUT2,?..." group.word 0x402++0x1 line.word 0x00 "RIC_RESIN513,ADC12B0_HWTRG23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU8_OTD0,PPG11_TOUT2,PPG13_TOUT0,PPG15_TOUT0,?..." group.word 0x404++0x1 line.word 0x00 "RIC_RESIN514,ADC12B0_HWTRG24 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU10_OTD0,PPG12_TOUT0,PPG13_TOUT2,PPG15_TOUT2,?..." sif cpuis("S6J335???") group.word 0x406++0x1 line.word 0x00 "RIC_RESIN515,ADC12B0_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU0_OTD0,PPG12_TOUT2,PPG14_TOUT0,PPG16_TOUT0,?..." group.word 0x408++0x1 line.word 0x00 "RIC_RESIN516,ADC12B0_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,PPG13_TOUT0,PPG14_TOUT2,PPG16_TOUT2,?..." group.word 0x40A++0x1 line.word 0x00 "RIC_RESIN517,ADC12B0_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,PPG13_TOUT2,PPG15_TOUT0,PPG17_TOUT0,?..." group.word 0x40C++0x1 line.word 0x00 "RIC_RESIN518,ADC12B0_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU8_OTD0,PPG14_TOUT0,PPG15_TOUT2,PPG17_TOUT2,?..." group.word 0x40E++0x1 line.word 0x00 "RIC_RESIN519,ADC12B0_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU9_OTD0,PPG14_TOUT2,PPG16_TOUT0,PPG18_TOUT0,?..." group.word 0x410++0x1 line.word 0x00 "RIC_RESIN520,ADC12B0_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU1_OTD0,PPG15_TOUT0,PPG16_TOUT2,PPG18_TOUT2,?..." group.word 0x412++0x1 line.word 0x00 "RIC_RESIN521,ADC12B0_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU2_OTD0,PPG15_TOUT2,PPG17_TOUT0,PPG19_TOUT0,?..." group.word 0x414++0x1 line.word 0x00 "RIC_RESIN522,ADC12B0_HWTRG32 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,PPG16_TOUT0,PPG17_TOUT2,PPG19_TOUT2,?..." group.word 0x416++0x1 line.word 0x00 "RIC_RESIN523,ADC12B0_HWTRG33 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,PPG16_TOUT2,PPG18_TOUT0,PPG20_TOUT0,?..." group.word 0x418++0x1 line.word 0x00 "RIC_RESIN524,ADC12B0_HWTRG34 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU10_OTD0,PPG17_TOUT0,PPG18_TOUT2,PPG20_TOUT2,?..." group.word 0x41A++0x1 line.word 0x00 "RIC_RESIN525,ADC12B0_HWTRG35 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU0_OTD0,PPG17_TOUT2,PPG19_TOUT0,PPG21_TOUT0,?..." group.word 0x41C++0x1 line.word 0x00 "RIC_RESIN526,ADC12B0_HWTRG36 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU2_OTD0,PPG18_TOUT0,PPG19_TOUT2,PPG21_TOUT2,?..." group.word 0x41E++0x1 line.word 0x00 "RIC_RESIN527,ADC12B0_HWTRG37 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU8_OTD0,PPG18_TOUT2,PPG20_TOUT0,PPG22_TOUT0,?..." group.word 0x420++0x1 line.word 0x00 "RIC_RESIN528,ADC12B0_HWTRG38 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU9_OTD0,PPG19_TOUT0,PPG20_TOUT2,PPG22_TOUT2,?..." group.word 0x422++0x1 line.word 0x00 "RIC_RESIN529,ADC12B0_HWTRG39 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU10_OTD0,PPG19_TOUT2,PPG21_TOUT0,PPG23_TOUT0,?..." group.word 0x424++0x1 line.word 0x00 "RIC_RESIN530,ADC12B0_HWTRG40 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU0_OTD0,PPG20_TOUT0,PPG21_TOUT2,PPG23_TOUT2,?..." group.word 0x426++0x1 line.word 0x00 "RIC_RESIN531,ADC12B0_HWTRG41 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU1_OTD0,PPG20_TOUT2,PPG22_TOUT0,PPG24_TOUT0,?..." group.word 0x428++0x1 line.word 0x00 "RIC_RESIN532,ADC12B0_HWTRG42 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU8_OTD0,PPG21_TOUT0,PPG22_TOUT2,PPG24_TOUT2,?..." group.word 0x42A++0x1 line.word 0x00 "RIC_RESIN533,ADC12B0_HWTRG43 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU9_OTD0,PPG21_TOUT2,PPG23_TOUT0,PPG25_TOUT0,?..." group.word 0x42C++0x1 line.word 0x00 "RIC_RESIN534,ADC12B0_HWTRG44 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU10_OTD0,PPG22_TOUT0,PPG23_TOUT2,PPG25_TOUT2,?..." group.word 0x42E++0x1 line.word 0x00 "RIC_RESIN535,ADC12B0_HWTRG45 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU0_OTD0,PPG22_TOUT2,PPG24_TOUT0,PPG26_TOUT0,?..." group.word 0x430++0x1 line.word 0x00 "RIC_RESIN536,ADC12B0_HWTRG46 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU1_OTD0,PPG23_TOUT0,PPG24_TOUT2,PPG26_TOUT2,?..." group.word 0x432++0x1 line.word 0x00 "RIC_RESIN537,ADC12B0_HWTRG47 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU2_OTD0,PPG23_TOUT2,PPG25_TOUT0,PPG27_TOUT0,?..." group.word 0x434++0x1 line.word 0x00 "RIC_RESIN538,ADC12B0_HWTRG48 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU9_OTD0,PPG24_TOUT0,PPG25_TOUT2,PPG27_TOUT2,?..." group.word 0x436++0x1 line.word 0x00 "RIC_RESIN539,ADC12B0_HWTRG49 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU10_OTD0,PPG24_TOUT2,PPG26_TOUT0,PPG28_TOUT0,?..." group.word 0x438++0x1 line.word 0x00 "RIC_RESIN540,ADC12B0_HWTRG50 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU0_OTD0,PPG25_TOUT0,PPG26_TOUT2,PPG28_TOUT2,?..." group.word 0x43A++0x1 line.word 0x00 "RIC_RESIN541,ADC12B0_HWTRG51 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU1_OTD0,PPG25_TOUT2,PPG27_TOUT0,PPG29_TOUT0,?..." group.word 0x43C++0x1 line.word 0x00 "RIC_RESIN542,ADC12B0_HWTRG52 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU2_OTD0,PPG26_TOUT0,PPG27_TOUT2,PPG29_TOUT2,?..." group.word 0x43E++0x1 line.word 0x00 "RIC_RESIN543,ADC12B0_HWTRG53 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU8_OTD0,PPG26_TOUT2,PPG28_TOUT0,PPG30_TOUT0,?..." group.word 0x440++0x1 line.word 0x00 "RIC_RESIN544,ADC12B0_HWTRG54 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU10_OTD0,PPG27_TOUT0,PPG28_TOUT2,PPG30_TOUT2,?..." group.word 0x442++0x1 line.word 0x00 "RIC_RESIN545,ADC12B0_HWTRG55 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU0_OTD0,PPG27_TOUT2,PPG29_TOUT0,PPG31_TOUT0,?..." group.word 0x444++0x1 line.word 0x00 "RIC_RESIN546,ADC12B0_HWTRG56 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,PPG28_TOUT0,PPG29_TOUT2,PPG31_TOUT2,?..." group.word 0x446++0x1 line.word 0x00 "RIC_RESIN547,ADC12B0_HWTRG57 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,PPG28_TOUT2,PPG30_TOUT0,PPG0_TOUT0,?..." group.word 0x448++0x1 line.word 0x00 "RIC_RESIN548,ADC12B0_HWTRG58 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU8_OTD0,PPG29_TOUT0,PPG30_TOUT2,PPG0_TOUT2,?..." group.word 0x44A++0x1 line.word 0x00 "RIC_RESIN549,ADC12B0_HWTRG59 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU9_OTD0,PPG29_TOUT2,PPG31_TOUT0,PPG1_TOUT0,?..." group.word 0x44C++0x1 line.word 0x00 "RIC_RESIN550,ADC12B0_HWTRG60 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU1_OTD0,PPG30_TOUT0,PPG31_TOUT2,PPG1_TOUT2,?..." group.word 0x44E++0x1 line.word 0x00 "RIC_RESIN551,ADC12B0_HWTRG61 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU2_OTD0,PPG30_TOUT2,PPG0_TOUT0,PPG2_TOUT0,?..." group.word 0x450++0x1 line.word 0x00 "RIC_RESIN552,ADC12B0_HWTRG62 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,PPG31_TOUT0,PPG0_TOUT2,PPG2_TOUT2,?..." group.word 0x452++0x1 line.word 0x00 "RIC_RESIN553,ADC12B0_HWTRG63 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,PPG31_TOUT2,PPG1_TOUT0,PPG3_TOUT0,?..." else group.word 0x406++0x1 line.word 0x00 "RIC_RESIN515,ADC12B0_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU0_OTD0,PPG12_TOUT2,PPG14_TOUT0,?..." group.word 0x408++0x1 line.word 0x00 "RIC_RESIN516,ADC12B0_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,PPG13_TOUT0,PPG14_TOUT2,?..." group.word 0x40A++0x1 line.word 0x00 "RIC_RESIN517,ADC12B0_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,PPG13_TOUT2,PPG15_TOUT0,?..." group.word 0x40C++0x1 line.word 0x00 "RIC_RESIN518,ADC12B0_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU8_OTD0,PPG14_TOUT0,PPG15_TOUT2,?..." group.word 0x40E++0x1 line.word 0x00 "RIC_RESIN519,ADC12B0_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU9_OTD0,PPG14_TOUT2,?..." group.word 0x410++0x1 line.word 0x00 "RIC_RESIN520,ADC12B0_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU1_OTD0,PPG15_TOUT0,?..." group.word 0x412++0x1 line.word 0x00 "RIC_RESIN521,ADC12B0_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU2_OTD0,PPG15_TOUT2,?..." group.word 0x414++0x1 line.word 0x00 "RIC_RESIN522,ADC12B0_HWTRG32 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,?..." group.word 0x416++0x1 line.word 0x00 "RIC_RESIN523,ADC12B0_HWTRG33 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,?..." group.word 0x418++0x1 line.word 0x00 "RIC_RESIN524,ADC12B0_HWTRG34 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU10_OTD0,?..." group.word 0x41A++0x1 line.word 0x00 "RIC_RESIN525,ADC12B0_HWTRG35 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU0_OTD0,?..." group.word 0x41C++0x1 line.word 0x00 "RIC_RESIN526,ADC12B0_HWTRG36 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU2_OTD0,?..." group.word 0x41E++0x1 line.word 0x00 "RIC_RESIN527,ADC12B0_HWTRG37 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU8_OTD0,?..." group.word 0x420++0x1 line.word 0x00 "RIC_RESIN528,ADC12B0_HWTRG38 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU9_OTD0,?..." group.word 0x422++0x1 line.word 0x00 "RIC_RESIN529,ADC12B0_HWTRG39 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU10_OTD0,?..." group.word 0x424++0x1 line.word 0x00 "RIC_RESIN530,ADC12B0_HWTRG40 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU0_OTD0,?..." group.word 0x426++0x1 line.word 0x00 "RIC_RESIN531,ADC12B0_HWTRG41 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU1_OTD0,?..." group.word 0x428++0x1 line.word 0x00 "RIC_RESIN532,ADC12B0_HWTRG42 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU8_OTD0,?..." group.word 0x42A++0x1 line.word 0x00 "RIC_RESIN533,ADC12B0_HWTRG43 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU9_OTD0,?..." group.word 0x42C++0x1 line.word 0x00 "RIC_RESIN534,ADC12B0_HWTRG44 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU10_OTD0,?..." group.word 0x42E++0x1 line.word 0x00 "RIC_RESIN535,ADC12B0_HWTRG45 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU0_OTD0,?..." group.word 0x430++0x1 line.word 0x00 "RIC_RESIN536,ADC12B0_HWTRG46 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU1_OTD0,?..." group.word 0x432++0x1 line.word 0x00 "RIC_RESIN537,ADC12B0_HWTRG47 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU2_OTD0,?..." group.word 0x434++0x1 line.word 0x00 "RIC_RESIN538,ADC12B0_HWTRG48 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU9_OTD0,?..." group.word 0x436++0x1 line.word 0x00 "RIC_RESIN539,ADC12B0_HWTRG49 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU10_OTD0,?..." group.word 0x438++0x1 line.word 0x00 "RIC_RESIN540,ADC12B0_HWTRG50 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU0_OTD0,?..." group.word 0x43A++0x1 line.word 0x00 "RIC_RESIN541,ADC12B0_HWTRG51 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU1_OTD0,?..." group.word 0x43C++0x1 line.word 0x00 "RIC_RESIN542,ADC12B0_HWTRG52 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU2_OTD0,?..." group.word 0x43E++0x1 line.word 0x00 "RIC_RESIN543,ADC12B0_HWTRG53 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU8_OTD0,?..." group.word 0x440++0x1 line.word 0x00 "RIC_RESIN544,ADC12B0_HWTRG54 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU10_OTD0,?..." group.word 0x442++0x1 line.word 0x00 "RIC_RESIN545,ADC12B0_HWTRG55 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU0_OTD0,?..." group.word 0x444++0x1 line.word 0x00 "RIC_RESIN546,ADC12B0_HWTRG56 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,?..." group.word 0x446++0x1 line.word 0x00 "RIC_RESIN547,ADC12B0_HWTRG57 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,,,PPG0_TOUT0,?..." group.word 0x448++0x1 line.word 0x00 "RIC_RESIN548,ADC12B0_HWTRG58 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU8_OTD0,,,PPG0_TOUT2,?..." group.word 0x44A++0x1 line.word 0x00 "RIC_RESIN549,ADC12B0_HWTRG59 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU9_OTD0,,,PPG1_TOUT0,?..." group.word 0x44C++0x1 line.word 0x00 "RIC_RESIN550,ADC12B0_HWTRG60 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU1_OTD0,,,PPG1_TOUT2,?..." group.word 0x44E++0x1 line.word 0x00 "RIC_RESIN551,ADC12B0_HWTRG61 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU2_OTD0,,PPG0_TOUT0,PPG2_TOUT0,?..." group.word 0x450++0x1 line.word 0x00 "RIC_RESIN552,ADC12B0_HWTRG62 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,,PPG0_TOUT2,PPG2_TOUT2,?..." group.word 0x452++0x1 line.word 0x00 "RIC_RESIN553,ADC12B0_HWTRG63 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,,PPG1_TOUT0,PPG3_TOUT0,?..." endif group.word 0x454++0x1 line.word 0x00 "RIC_RESIN554,ADC12B1_HWTRG0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU1_OTD0,PPG0_TOUT0,PPG1_TOUT2,PPG3_TOUT2,?..." group.word 0x456++0x1 line.word 0x00 "RIC_RESIN555,ADC12B1_HWTRG1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU2_OTD0,PPG0_TOUT2,PPG2_TOUT0,PPG4_TOUT0,?..." group.word 0x458++0x1 line.word 0x00 "RIC_RESIN556,ADC12B1_HWTRG2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,PPG1_TOUT0,PPG2_TOUT2,PPG4_TOUT2,?..." group.word 0x45A++0x1 line.word 0x00 "RIC_RESIN557,ADC12B1_HWTRG3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,PPG1_TOUT2,PPG3_TOUT0,PPG5_TOUT0,?..." group.word 0x45C++0x1 line.word 0x00 "RIC_RESIN558,ADC12B1_HWTRG4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU10_OTD0,PPG2_TOUT0,PPG3_TOUT2,PPG5_TOUT2,?..." group.word 0x45E++0x1 line.word 0x00 "RIC_RESIN559,ADC12B1_HWTRG5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU0_OTD0,PPG2_TOUT2,PPG4_TOUT0,PPG6_TOUT0,?..." group.word 0x460++0x1 line.word 0x00 "RIC_RESIN560,ADC12B1_HWTRG6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU2_OTD0,PPG3_TOUT0,PPG4_TOUT2,PPG6_TOUT2,?..." group.word 0x462++0x1 line.word 0x00 "RIC_RESIN561,ADC12B1_HWTRG7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU8_OTD0,PPG3_TOUT2,PPG5_TOUT0,PPG7_TOUT0,?..." group.word 0x464++0x1 line.word 0x00 "RIC_RESIN562,ADC12B1_HWTRG8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU9_OTD0,PPG4_TOUT0,PPG5_TOUT2,PPG7_TOUT2,?..." group.word 0x466++0x1 line.word 0x00 "RIC_RESIN563,ADC12B1_HWTRG9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU10_OTD0,PPG4_TOUT2,PPG6_TOUT0,PPG8_TOUT0,?..." group.word 0x468++0x1 line.word 0x00 "RIC_RESIN564,ADC12B1_HWTRG10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU0_OTD0,PPG5_TOUT0,PPG6_TOUT2,PPG8_TOUT2,?..." group.word 0x46A++0x1 line.word 0x00 "RIC_RESIN565,ADC12B1_HWTRG11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU1_OTD0,PPG5_TOUT2,PPG7_TOUT0,PPG9_TOUT0,?..." group.word 0x46C++0x1 line.word 0x00 "RIC_RESIN566,ADC12B1_HWTRG12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU8_OTD0,PPG6_TOUT0,PPG7_TOUT2,PPG9_TOUT2,?..." group.word 0x46E++0x1 line.word 0x00 "RIC_RESIN567,ADC12B1_HWTRG13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU9_OTD0,PPG6_TOUT2,PPG8_TOUT0,PPG10_TOUT0,?..." group.word 0x470++0x1 line.word 0x00 "RIC_RESIN568,ADC12B1_HWTRG14 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU10_OTD0,PPG7_TOUT0,PPG8_TOUT2,PPG10_TOUT2,?..." group.word 0x472++0x1 line.word 0x00 "RIC_RESIN569,ADC12B1_HWTRG15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU0_OTD0,PPG7_TOUT2,PPG9_TOUT0,PPG11_TOUT0,?..." group.word 0x474++0x1 line.word 0x00 "RIC_RESIN570,ADC12B1_HWTRG16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU1_OTD0,PPG8_TOUT0,PPG9_TOUT2,PPG11_TOUT2,?..." group.word 0x476++0x1 line.word 0x00 "RIC_RESIN571,ADC12B1_HWTRG17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU2_OTD0,PPG8_TOUT2,PPG10_TOUT0,PPG12_TOUT0,?..." group.word 0x478++0x1 line.word 0x00 "RIC_RESIN572,ADC12B1_HWTRG18 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU9_OTD0,PPG9_TOUT0,PPG10_TOUT2,PPG12_TOUT2,?..." group.word 0x47A++0x1 line.word 0x00 "RIC_RESIN573,ADC12B1_HWTRG19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU10_OTD0,PPG9_TOUT2,PPG11_TOUT0,PPG13_TOUT0,?..." group.word 0x47C++0x1 line.word 0x00 "RIC_RESIN574,ADC12B1_HWTRG20 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU0_OTD0,PPG10_TOUT0,PPG11_TOUT2,PPG13_TOUT2,?..." group.word 0x47E++0x1 line.word 0x00 "RIC_RESIN575,ADC12B1_HWTRG21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU1_OTD0,PPG10_TOUT2,PPG12_TOUT0,PPG14_TOUT0,?..." group.word 0x480++0x1 line.word 0x00 "RIC_RESIN576,ADC12B1_HWTRG22 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU2_OTD0,PPG11_TOUT0,PPG12_TOUT2,PPG14_TOUT2,?..." group.word 0x482++0x1 line.word 0x00 "RIC_RESIN577,ADC12B1_HWTRG23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU8_OTD0,PPG11_TOUT2,PPG13_TOUT0,PPG15_TOUT0,?..." group.word 0x484++0x1 line.word 0x00 "RIC_RESIN578,ADC12B1_HWTRG24 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU10_OTD0,PPG12_TOUT0,PPG13_TOUT2,PPG15_TOUT2,?..." sif cpuis("S6J335???") group.word 0x486++0x1 line.word 0x00 "RIC_RESIN579,ADC12B1_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU0_OTD0,PPG12_TOUT2,PPG14_TOUT0,PPG16_TOUT0,?..." group.word 0x488++0x1 line.word 0x00 "RIC_RESIN580,ADC12B1_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,PPG13_TOUT0,PPG14_TOUT2,PPG16_TOUT2,?..." group.word 0x48A++0x1 line.word 0x00 "RIC_RESIN581,ADC12B1_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,PPG13_TOUT2,PPG15_TOUT0,PPG17_TOUT0,?..." group.word 0x48C++0x1 line.word 0x00 "RIC_RESIN582,ADC12B1_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU8_OTD0,PPG14_TOUT0,PPG15_TOUT2,PPG17_TOUT2,?..." group.word 0x48E++0x1 line.word 0x00 "RIC_RESIN583,ADC12B1_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU9_OTD0,PPG14_TOUT2,PPG16_TOUT0,PPG18_TOUT0,?..." group.word 0x490++0x1 line.word 0x00 "RIC_RESIN584,ADC12B1_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU1_OTD0,PPG15_TOUT0,PPG16_TOUT2,PPG18_TOUT2,?..." group.word 0x492++0x1 line.word 0x00 "RIC_RESIN585,ADC12B1_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU2_OTD0,PPG15_TOUT2,PPG17_TOUT0,PPG19_TOUT0,?..." group.word 0x494++0x1 line.word 0x00 "RIC_RESIN586,ADC12B1_HWTRG32 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,PPG16_TOUT0,PPG17_TOUT2,PPG19_TOUT2,?..." group.word 0x496++0x1 line.word 0x00 "RIC_RESIN587,ADC12B1_HWTRG33 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,PPG16_TOUT2,PPG18_TOUT0,PPG20_TOUT0,?..." group.word 0x498++0x1 line.word 0x00 "RIC_RESIN588,ADC12B1_HWTRG34 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU10_OTD0,PPG17_TOUT0,PPG18_TOUT2,PPG20_TOUT2,?..." group.word 0x49A++0x1 line.word 0x00 "RIC_RESIN589,ADC12B1_HWTRG35 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU0_OTD0,PPG17_TOUT2,PPG19_TOUT0,PPG21_TOUT0,?..." group.word 0x49C++0x1 line.word 0x00 "RIC_RESIN590,ADC12B1_HWTRG36 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU2_OTD0,PPG18_TOUT0,PPG19_TOUT2,PPG21_TOUT2,?..." group.word 0x49E++0x1 line.word 0x00 "RIC_RESIN591,ADC12B1_HWTRG37 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU8_OTD0,PPG18_TOUT2,PPG20_TOUT0,PPG22_TOUT0,?..." group.word 0x4A0++0x1 line.word 0x00 "RIC_RESIN592,ADC12B1_HWTRG38 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU9_OTD0,PPG19_TOUT0,PPG20_TOUT2,PPG22_TOUT2,?..." group.word 0x4A2++0x1 line.word 0x00 "RIC_RESIN593,ADC12B1_HWTRG39 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU10_OTD0,PPG19_TOUT2,PPG21_TOUT0,PPG23_TOUT0,?..." group.word 0x4A4++0x1 line.word 0x00 "RIC_RESIN594,ADC12B1_HWTRG40 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU0_OTD0,PPG20_TOUT0,PPG21_TOUT2,PPG23_TOUT2,?..." group.word 0x4A6++0x1 line.word 0x00 "RIC_RESIN595,ADC12B1_HWTRG41 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU1_OTD0,PPG20_TOUT2,PPG22_TOUT0,PPG24_TOUT0,?..." group.word 0x4A8++0x1 line.word 0x00 "RIC_RESIN596,ADC12B1_HWTRG42 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU8_OTD0,PPG21_TOUT0,PPG22_TOUT2,PPG24_TOUT2,?..." group.word 0x4AA++0x1 line.word 0x00 "RIC_RESIN597,ADC12B1_HWTRG43 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU9_OTD0,PPG21_TOUT2,PPG23_TOUT0,PPG25_TOUT0,?..." group.word 0x4AC++0x1 line.word 0x00 "RIC_RESIN598,ADC12B1_HWTRG44 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU10_OTD0,PPG22_TOUT0,PPG23_TOUT2,PPG25_TOUT2,?..." group.word 0x4AE++0x1 line.word 0x00 "RIC_RESIN599,ADC12B1_HWTRG45 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU0_OTD0,PPG22_TOUT2,PPG24_TOUT0,PPG26_TOUT0,?..." group.word 0x4B0++0x1 line.word 0x00 "RIC_RESIN600,ADC12B1_HWTRG46 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU1_OTD0,PPG23_TOUT0,PPG24_TOUT2,PPG26_TOUT2,?..." group.word 0x4B2++0x1 line.word 0x00 "RIC_RESIN601,ADC12B1_HWTRG47 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU2_OTD0,PPG23_TOUT2,PPG25_TOUT0,PPG27_TOUT0,?..." group.word 0x4B4++0x1 line.word 0x00 "RIC_RESIN602,ADC12B1_HWTRG48 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU9_OTD0,PPG24_TOUT0,PPG25_TOUT2,PPG27_TOUT2,?..." group.word 0x4B6++0x1 line.word 0x00 "RIC_RESIN603,ADC12B1_HWTRG49 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU10_OTD0,PPG24_TOUT2,PPG26_TOUT0,PPG28_TOUT0,?..." group.word 0x4B8++0x1 line.word 0x00 "RIC_RESIN604,ADC12B1_HWTRG50 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU0_OTD0,PPG25_TOUT0,PPG26_TOUT2,PPG28_TOUT2,?..." group.word 0x4BA++0x1 line.word 0x00 "RIC_RESIN605,ADC12B1_HWTRG51 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU1_OTD0,PPG25_TOUT2,PPG27_TOUT0,PPG29_TOUT0,?..." group.word 0x4BC++0x1 line.word 0x00 "RIC_RESIN606,ADC12B1_HWTRG52 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU2_OTD0,PPG26_TOUT0,PPG27_TOUT2,PPG29_TOUT2,?..." group.word 0x4BE++0x1 line.word 0x00 "RIC_RESIN607,ADC12B1_HWTRG53 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU8_OTD0,PPG26_TOUT2,PPG28_TOUT0,PPG30_TOUT0,?..." group.word 0x4C0++0x1 line.word 0x00 "RIC_RESIN608,ADC12B1_HWTRG54 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU10_OTD0,PPG27_TOUT0,PPG28_TOUT2,PPG30_TOUT2,?..." group.word 0x4C2++0x1 line.word 0x00 "RIC_RESIN609,ADC12B1_HWTRG55 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU0_OTD0,PPG27_TOUT2,PPG29_TOUT0,PPG31_TOUT0,?..." group.word 0x4C4++0x1 line.word 0x00 "RIC_RESIN610,ADC12B1_HWTRG56 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,PPG28_TOUT0,PPG29_TOUT2,PPG31_TOUT2,?..." group.word 0x4C6++0x1 line.word 0x00 "RIC_RESIN611,ADC12B1_HWTRG57 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,PPG28_TOUT2,PPG30_TOUT0,PPG0_TOUT0,?..." group.word 0x4C8++0x1 line.word 0x00 "RIC_RESIN612,ADC12B1_HWTRG58 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU8_OTD0,PPG29_TOUT0,PPG30_TOUT2,PPG0_TOUT2,?..." group.word 0x4CA++0x1 line.word 0x00 "RIC_RESIN613,ADC12B1_HWTRG59 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU9_OTD0,PPG29_TOUT2,PPG31_TOUT0,PPG1_TOUT0,?..." group.word 0x4CC++0x1 line.word 0x00 "RIC_RESIN614,ADC12B1_HWTRG60 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU1_OTD0,PPG30_TOUT0,PPG31_TOUT2,PPG1_TOUT2,?..." group.word 0x4CE++0x1 line.word 0x00 "RIC_RESIN615,ADC12B1_HWTRG61 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU2_OTD0,PPG30_TOUT2,PPG0_TOUT0,PPG2_TOUT0,?..." group.word 0x4D0++0x1 line.word 0x00 "RIC_RESIN616,ADC12B1_HWTRG62 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,PPG31_TOUT0,PPG0_TOUT2,PPG2_TOUT2,?..." group.word 0x4D2++0x1 line.word 0x00 "RIC_RESIN617,ADC12B1_HWTRG63 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,PPG31_TOUT2,PPG1_TOUT0,PPG3_TOUT0,?..." else group.word 0x486++0x1 line.word 0x00 "RIC_RESIN579,ADC12B1_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU0_OTD0,PPG12_TOUT2,PPG14_TOUT0,?..." group.word 0x488++0x1 line.word 0x00 "RIC_RESIN580,ADC12B1_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,PPG13_TOUT0,PPG14_TOUT2,?..." group.word 0x48A++0x1 line.word 0x00 "RIC_RESIN581,ADC12B1_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,PPG13_TOUT2,PPG15_TOUT0,?..." group.word 0x48C++0x1 line.word 0x00 "RIC_RESIN582,ADC12B1_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU8_OTD0,PPG14_TOUT0,PPG15_TOUT2,?..." group.word 0x48E++0x1 line.word 0x00 "RIC_RESIN583,ADC12B1_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU9_OTD0,PPG14_TOUT2,?..." group.word 0x490++0x1 line.word 0x00 "RIC_RESIN584,ADC12B1_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU1_OTD0,PPG15_TOUT0,?..." group.word 0x492++0x1 line.word 0x00 "RIC_RESIN585,ADC12B1_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU2_OTD0,PPG15_TOUT2,?..." group.word 0x494++0x1 line.word 0x00 "RIC_RESIN586,ADC12B1_HWTRG32 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,?..." group.word 0x496++0x1 line.word 0x00 "RIC_RESIN587,ADC12B1_HWTRG33 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,?..." group.word 0x498++0x1 line.word 0x00 "RIC_RESIN588,ADC12B1_HWTRG34 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU10_OTD0,?..." group.word 0x49A++0x1 line.word 0x00 "RIC_RESIN589,ADC12B1_HWTRG35 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU0_OTD0,?..." group.word 0x49C++0x1 line.word 0x00 "RIC_RESIN590,ADC12B1_HWTRG36 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU2_OTD0,?..." group.word 0x49E++0x1 line.word 0x00 "RIC_RESIN591,ADC12B1_HWTRG37 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU8_OTD0,?..." group.word 0x4A0++0x1 line.word 0x00 "RIC_RESIN592,ADC12B1_HWTRG38 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU9_OTD0,?..." group.word 0x4A2++0x1 line.word 0x00 "RIC_RESIN593,ADC12B1_HWTRG39 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU10_OTD0,?..." group.word 0x4A4++0x1 line.word 0x00 "RIC_RESIN594,ADC12B1_HWTRG40 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU0_OTD0,?..." group.word 0x4A6++0x1 line.word 0x00 "RIC_RESIN595,ADC12B1_HWTRG41 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU1_OTD0,?..." group.word 0x4A8++0x1 line.word 0x00 "RIC_RESIN596,ADC12B1_HWTRG42 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU8_OTD0,?..." group.word 0x4AA++0x1 line.word 0x00 "RIC_RESIN597,ADC12B1_HWTRG43 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU9_OTD0,?..." group.word 0x4AC++0x1 line.word 0x00 "RIC_RESIN598,ADC12B1_HWTRG44 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU10_OTD0,?..." group.word 0x4AE++0x1 line.word 0x00 "RIC_RESIN599,ADC12B1_HWTRG45 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU0_OTD0,?..." group.word 0x4B0++0x1 line.word 0x00 "RIC_RESIN600,ADC12B1_HWTRG46 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU1_OTD0,?..." group.word 0x4B2++0x1 line.word 0x00 "RIC_RESIN601,ADC12B1_HWTRG47 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU2_OTD0,?..." group.word 0x4B4++0x1 line.word 0x00 "RIC_RESIN602,ADC12B1_HWTRG48 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU9_OTD0,?..." group.word 0x4B6++0x1 line.word 0x00 "RIC_RESIN603,ADC12B1_HWTRG49 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU10_OTD0,?..." group.word 0x4B8++0x1 line.word 0x00 "RIC_RESIN604,ADC12B1_HWTRG50 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU0_OTD0,?..." group.word 0x4BA++0x1 line.word 0x00 "RIC_RESIN605,ADC12B1_HWTRG51 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU1_OTD0,?..." group.word 0x4BC++0x1 line.word 0x00 "RIC_RESIN606,ADC12B1_HWTRG52 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT16_UFSET,OCU9_OTD0,OCU2_OTD0,?..." group.word 0x4BE++0x1 line.word 0x00 "RIC_RESIN607,ADC12B1_HWTRG53 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT17_UFSET,OCU10_OTD0,OCU8_OTD0,?..." group.word 0x4C0++0x1 line.word 0x00 "RIC_RESIN608,ADC12B1_HWTRG54 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT0_UFSET,OCU0_OTD0,OCU10_OTD0,?..." group.word 0x4C2++0x1 line.word 0x00 "RIC_RESIN609,ADC12B1_HWTRG55 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT1_UFSET,OCU1_OTD0,OCU0_OTD0,?..." group.word 0x4C4++0x1 line.word 0x00 "RIC_RESIN610,ADC12B1_HWTRG56 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT17_UFSET,OCU2_OTD0,OCU1_OTD0,?..." group.word 0x4C6++0x1 line.word 0x00 "RIC_RESIN611,ADC12B1_HWTRG57 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT0_UFSET,OCU8_OTD0,OCU2_OTD0,?..." group.word 0x4C8++0x1 line.word 0x00 "RIC_RESIN612,ADC12B1_HWTRG58 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT1_UFSET,OCU9_OTD0,OCU8_OTD0,?..." group.word 0x4CA++0x1 line.word 0x00 "RIC_RESIN613,ADC12B1_HWTRG59 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT16_UFSET,OCU10_OTD0,OCU9_OTD0,?..." group.word 0x4CC++0x1 line.word 0x00 "RIC_RESIN614,ADC12B1_HWTRG60 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OCU0_OTD0,OCU1_OTD0,,,PPG1_TOUT2,?..." group.word 0x4CE++0x1 line.word 0x00 "RIC_RESIN615,ADC12B1_HWTRG61 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT16_UFSET,OCU1_OTD0,OCU2_OTD0,,PPG0_TOUT0,PPG2_TOUT0,?..." group.word 0x4D0++0x1 line.word 0x00 "RIC_RESIN616,ADC12B1_HWTRG62 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OCU2_OTD0,OCU8_OTD0,,PPG0_TOUT2,PPG2_TOUT2,?..." group.word 0x4D2++0x1 line.word 0x00 "RIC_RESIN617,ADC12B1_HWTRG63 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OCU8_OTD0,OCU9_OTD0,,PPG1_TOUT0,PPG3_TOUT0,?..." endif group.word 0x4E4++0x1 line.word 0x00 "RIC_RESIN626,DDRHSSPI_MSTART Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" ",TOT0,TOT16,?..." sif (!cpuis("S6J331?H?")&&!cpuis("S6J332?H?")&&!cpuis("S6J333?H?")&&!cpuis("S6J334?H?")&&!cpuis("S6J335?H?")) group.word 0x4EA++0x1 line.word 0x00 "RIC_RESIN629,MDIO Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,P3_06,?..." group.word 0x4EC++0x1 line.word 0x00 "RIC_RESIN630,CRS Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_02,P0_20,?..." group.word 0x4EE++0x1 line.word 0x00 "RIC_RESIN631,RXD0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,P3_04,?..." sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x4F0++0x1 line.word 0x00 "RIC_RESIN632,RXD1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,P4_06,?..." group.word 0x4F2++0x1 line.word 0x00 "RIC_RESIN633,RXD2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_29,P4_07,?..." else group.word 0x4F0++0x1 line.word 0x00 "RIC_RESIN632,RXD1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,,?..." group.word 0x4F2++0x1 line.word 0x00 "RIC_RESIN633,RXD2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_29,,?..." endif group.word 0x4F4++0x1 line.word 0x00 "RIC_RESIN634,RXD3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,P3_05,?..." group.word 0x4F6++0x1 line.word 0x00 "RIC_RESIN635,COL Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_01,P0_19,?..." sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x4F8++0x1 line.word 0x00 "RIC_RESIN636,RXDV Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_19,P4_02,?..." group.word 0x4FA++0x1 line.word 0x00 "RIC_RESIN637,RXER Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_18,P4_01,?..." group.word 0x4FC++0x1 line.word 0x00 "RIC_RESIN638,RXCLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_17,P4_00,?..." group.word 0x4FE++0x1 line.word 0x00 "RIC_RESIN639,TXCLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_20,P4_03,?..." else group.word 0x4F8++0x1 line.word 0x00 "RIC_RESIN636,RXDV Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_19,,?..." group.word 0x4FA++0x1 line.word 0x00 "RIC_RESIN637,RXER Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_18,,?..." group.word 0x4FC++0x1 line.word 0x00 "RIC_RESIN638,RXCLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_17,,?..." group.word 0x4FE++0x1 line.word 0x00 "RIC_RESIN639,TXCLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_20,,?..." endif sif (!cpuis("S6J335???")) group.word 0x506++0x1 line.word 0x00 "RIC_RESIN643,I2S0_WS Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_12,P3_26,?..." group.word 0x508++0x1 line.word 0x00 "RIC_RESIN644,I2S0_SD Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_11,P3_25,?..." group.word 0x50A++0x1 line.word 0x00 "RIC_RESIN645,I2S0_SCK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_13,P3_27,?..." group.word 0x50C++0x1 line.word 0x00 "RIC_RESIN646,I2S0_ECLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_10,P3_24,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,SYSC1_CLK_CD4,?..." group.word 0x514++0x1 line.word 0x00 "RIC_RESIN650,I2S1_ECLK Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,SYSC1_CLK_CD4,?..." endif group.word 0x55A++0x1 line.word 0x00 "RIC_RESIN685,ADTRG0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P2_10,?..." sif (!cpuis("S6J331?J?")&&!cpuis("S6J332?J?")&&!cpuis("S6J333?J?")&&!cpuis("S6J334?J?")&&!cpuis("S6J335?J?")) group.word 0x55C++0x1 line.word 0x00 "RIC_RESIN686,ADTRG1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P4_22,P1_08,P2_11,?..." else group.word 0x55C++0x1 line.word 0x00 "RIC_RESIN686,ADTRG1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" ",P1_08,P2_11,?..." endif else group.word 0x4EA++0x1 line.word 0x00 "RIC_RESIN629,MDIO Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_31,,?..." group.word 0x4EC++0x1 line.word 0x00 "RIC_RESIN630,CRS Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_02,P0_20,?..." group.word 0x4EE++0x1 line.word 0x00 "RIC_RESIN631,RXD0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_27,,?..." group.word 0x4F0++0x1 line.word 0x00 "RIC_RESIN632,RXD1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_28,,?..." group.word 0x4F2++0x1 line.word 0x00 "RIC_RESIN633,RXD2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_29,,?..." group.word 0x4F4++0x1 line.word 0x00 "RIC_RESIN634,RXD3 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_30,,?..." group.word 0x4F6++0x1 line.word 0x00 "RIC_RESIN635,COL Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_01,P0_19,?..." group.word 0x4F8++0x1 line.word 0x00 "RIC_RESIN636,RXDV Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_19,,?..." group.word 0x4FA++0x1 line.word 0x00 "RIC_RESIN637,RXER Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_18,,?..." group.word 0x4FC++0x1 line.word 0x00 "RIC_RESIN638,RXCLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_17,,?..." group.word 0x4FE++0x1 line.word 0x00 "RIC_RESIN639,TXCLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_20,,?..." sif (!cpuis("S6J335???")) group.word 0x506++0x1 line.word 0x00 "RIC_RESIN643,I2S0_WS Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_12,,?..." group.word 0x508++0x1 line.word 0x00 "RIC_RESIN644,I2S0_SD Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_11,,?..." group.word 0x50A++0x1 line.word 0x00 "RIC_RESIN645,I2S0_SCK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_13,,?..." group.word 0x50C++0x1 line.word 0x00 "RIC_RESIN646,I2S0_ECLK Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P0_10,,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,SYSC1_CLK_CD4,?..." group.word 0x514++0x1 line.word 0x00 "RIC_RESIN650,I2S1_ECLK Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,SYSC1_CLK_CD4,?..." endif group.word 0x55A++0x1 line.word 0x00 "RIC_RESIN685,ADTRG0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P1_16,P2_10,?..." group.word 0x55C++0x1 line.word 0x00 "RIC_RESIN686,ADTRG1 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" ",P1_08,P2_11,?..." endif width 0x0B tree.end endif tree.end tree "PPU (Peripheral Protection Unit)" base ad:0xB4750000 width 8. group.long 0x00++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 29. " MODE ,PPU mode bit" "R/W,R/A" bitfld.long 0x00 23. " VCLR ,PPU violation information clear" "No effect,Clear" bitfld.long 0x00 9. " FPQSET ,PPU privilege mode forced change function quick set" "No effect,Set" bitfld.long 0x00 8. " FPQCLR ,PPU privilege mode forced change function quick clear" "No effect,Clear" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x04++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 23. " VD ,Violation detection bit" "Not generated,Generated" bitfld.long 0x00 22. " VP ,Violation privileged level bit" "User,Privilege" bitfld.long 0x00 21. " VW ,Violation write access bit" "Read,Write" newline bitfld.long 0x00 16.--20. " VL ,Violation location" ",MCU config,SYSC1,Memory config/Scratch pad RAM,CPERI0,CPERI1,CPERI2,EBI,SHE,DDRHSSPI,Application specific area 0,Application specific area 1,Application specific area 2,Application specific area 3,Application specific area 4,Application specific area 5,Application specific area 6,?..." bitfld.long 0x00 0. " LST ,Lock status bit" "Unlocked,Locked" else group.long 0x04++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 23. " VD ,Violation detection bit" "Not generated,Generated" bitfld.long 0x00 22. " VP ,Violation privileged level bit" "User,Privilege" bitfld.long 0x00 21. " VW ,Violation write access bit" "Read,Write" newline bitfld.long 0x00 16.--20. " VL ,Violation location" ",MCU config,SYSC1,Memory config/Scratch pad RAM,CPERI0,CPERI1,CPERI2,EBI,SHE,DDRHSSPI,Application specific area 0,Application specific area 1,Application specific area 2,Application specific area 3,Application specific area 4,Application specific area 5,Application specific area 6,?..." bitfld.long 0x00 0. " LST ,Lock status bit" "Unlocked,Locked" endif wgroup.long 0x08++0x03 line.long 0x00 "UNLOCK,Unlock Register" if ((per.l(ad:0xB4750000+0x04)&0x01)==0x00) wgroup.long 0x0C++0x0F line.long 0x00 "WPQCLR,Privileged Write Attribute Quick Clear Register" bitfld.long 0x00 0. " WPQCLR ,PPU privileged write attribute quick clear" "No effect,Clear" line.long 0x04 "WUQCLR,User Write Attribute Quick Clear Register" bitfld.long 0x04 0. " WUQCLR ,PPU user write attribute quick clear" "No effect,Clear" line.long 0x08 "RPQCLR,Privileged Read Attribute Quick Clear Register" bitfld.long 0x08 0. " RPQCLR ,PPU privileged read attribute quick clear" "No effect,Clear" line.long 0x0C "RUQCLR,User Read Attribute Quick Clear Register" bitfld.long 0x0C 0. " RUQCLR ,PPU user read attribute quick clear" "No effect,Clear" group.long 0x80++0x03 line.long 0x00 "PPR0,Privileged Read Attribute Register 0" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x84++0x03 line.long 0x00 "PPR1,Privileged Read Attribute Register 1" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x88++0x03 line.long 0x00 "PPR2,Privileged Read Attribute Register 2" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x8C++0x03 line.long 0x00 "PPR3,Privileged Read Attribute Register 3" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x90++0x03 line.long 0x00 "PPR4,Privileged Read Attribute Register 4" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "PPR5,Privileged Read Attribute Register 5" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "PPR6,Privileged Read Attribute Register 6" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x9C++0x03 line.long 0x00 "PPR7,Privileged Read Attribute Register 7" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PPR8,Privileged Read Attribute Register 8" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xA4++0x03 line.long 0x00 "PPR9,Privileged Read Attribute Register 9" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xA8++0x03 line.long 0x00 "PPR10,Privileged Read Attribute Register 10" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xAC++0x03 line.long 0x00 "PPR11,Privileged Read Attribute Register 11" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xB0++0x03 line.long 0x00 "PPR12,Privileged Read Attribute Register 12" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xB4++0x03 line.long 0x00 "PPR13,Privileged Read Attribute Register 13" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xB8++0x03 line.long 0x00 "PPR14,Privileged Read Attribute Register 14" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xBC++0x03 line.long 0x00 "PPR15,Privileged Read Attribute Register 15" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xC0++0x03 line.long 0x00 "PPR16,Privileged Read Attribute Register 16" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "PPR17,Privileged Read Attribute Register 17" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xC8++0x03 line.long 0x00 "PPR18,Privileged Read Attribute Register 18" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xCC++0x03 line.long 0x00 "PPR19,Privileged Read Attribute Register 19" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xD0++0x03 line.long 0x00 "PPR20,Privileged Read Attribute Register 20" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xD4++0x03 line.long 0x00 "PPR21,Privileged Read Attribute Register 21" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xD8++0x03 line.long 0x00 "PPR22,Privileged Read Attribute Register 22" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xDC++0x03 line.long 0x00 "PPR23,Privileged Read Attribute Register 23" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xE0++0x03 line.long 0x00 "PPR24,Privileged Read Attribute Register 24" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xE4++0x03 line.long 0x00 "PPR25,Privileged Read Attribute Register 25" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xE8++0x03 line.long 0x00 "PPR26,Privileged Read Attribute Register 26" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xEC++0x03 line.long 0x00 "PPR27,Privileged Read Attribute Register 27" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xF0++0x03 line.long 0x00 "PPR28,Privileged Read Attribute Register 28" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xF4++0x03 line.long 0x00 "PPR29,Privileged Read Attribute Register 29" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x100++0x03 line.long 0x00 "PUR0,User Read Attribute Register 0" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x104++0x03 line.long 0x00 "PUR1,User Read Attribute Register 1" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x108++0x03 line.long 0x00 "PUR2,User Read Attribute Register 2" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x10C++0x03 line.long 0x00 "PUR3,User Read Attribute Register 3" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x110++0x03 line.long 0x00 "PUR4,User Read Attribute Register 4" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x114++0x03 line.long 0x00 "PUR5,User Read Attribute Register 5" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x118++0x03 line.long 0x00 "PUR6,User Read Attribute Register 6" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x11C++0x03 line.long 0x00 "PUR7,User Read Attribute Register 7" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "PUR8,User Read Attribute Register 8" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "PUR9,User Read Attribute Register 9" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x128++0x03 line.long 0x00 "PUR10,User Read Attribute Register 10" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x12C++0x03 line.long 0x00 "PUR11,User Read Attribute Register 11" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x130++0x03 line.long 0x00 "PUR12,User Read Attribute Register 12" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x134++0x03 line.long 0x00 "PUR13,User Read Attribute Register 13" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "PUR14,User Read Attribute Register 14" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x13C++0x03 line.long 0x00 "PUR15,User Read Attribute Register 15" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x140++0x03 line.long 0x00 "PUR16,User Read Attribute Register 16" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "PUR17,User Read Attribute Register 17" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "PUR18,User Read Attribute Register 18" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "PUR19,User Read Attribute Register 19" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "PUR20,User Read Attribute Register 20" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "PUR21,User Read Attribute Register 21" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x158++0x03 line.long 0x00 "PUR22,User Read Attribute Register 22" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x15C++0x03 line.long 0x00 "PUR23,User Read Attribute Register 23" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "PUR24,User Read Attribute Register 24" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x164++0x03 line.long 0x00 "PUR25,User Read Attribute Register 25" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x168++0x03 line.long 0x00 "PUR26,User Read Attribute Register 26" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x16C++0x03 line.long 0x00 "PUR27,User Read Attribute Register 27" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x170++0x03 line.long 0x00 "PUR28,User Read Attribute Register 28" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "PUR29,User Read Attribute Register 29" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" newline group.long 0x180++0x03 line.long 0x00 "PPWA0,Privileged Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x184++0x03 line.long 0x00 "PPWA1,Privileged Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x188++0x03 line.long 0x00 "PPWA2,Privileged Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x18C++0x03 line.long 0x00 "PPWA3,Privileged Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x190++0x03 line.long 0x00 "PPWA4,Privileged Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x194++0x03 line.long 0x00 "PPWA5,Privileged Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x198++0x03 line.long 0x00 "PPWA6,Privileged Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x19C++0x03 line.long 0x00 "PPWA7,Privileged Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1A0++0x03 line.long 0x00 "PPWA8,Privileged Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1A4++0x03 line.long 0x00 "PPWA9,Privileged Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1A8++0x03 line.long 0x00 "PPWA10,Privileged Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1AC++0x03 line.long 0x00 "PPWA11,Privileged Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1B0++0x03 line.long 0x00 "PPWA12,Privileged Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1B4++0x03 line.long 0x00 "PPWA13,Privileged Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1B8++0x03 line.long 0x00 "PPWA14,Privileged Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1BC++0x03 line.long 0x00 "PPWA15,Privileged Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1C0++0x03 line.long 0x00 "PPWA16,Privileged Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1C4++0x03 line.long 0x00 "PPWA17,Privileged Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1C8++0x03 line.long 0x00 "PPWA18,Privileged Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1CC++0x03 line.long 0x00 "PPWA19,Privileged Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1D0++0x03 line.long 0x00 "PPWA20,Privileged Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1D4++0x03 line.long 0x00 "PPWA21,Privileged Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1D8++0x03 line.long 0x00 "PPWA22,Privileged Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1DC++0x03 line.long 0x00 "PPWA23,Privileged Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1E0++0x03 line.long 0x00 "PPWA24,Privileged Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1E4++0x03 line.long 0x00 "PPWA25,Privileged Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1E8++0x03 line.long 0x00 "PPWA26,Privileged Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1EC++0x03 line.long 0x00 "PPWA27,Privileged Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1F0++0x03 line.long 0x00 "PPWA28,Privileged Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1F4++0x03 line.long 0x00 "PPWA29,Privileged Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x200++0x03 line.long 0x00 "PUWA0,User Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x204++0x03 line.long 0x00 "PUWA1,User Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x208++0x03 line.long 0x00 "PUWA2,User Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x20C++0x03 line.long 0x00 "PUWA3,User Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x210++0x03 line.long 0x00 "PUWA4,User Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x214++0x03 line.long 0x00 "PUWA5,User Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x218++0x03 line.long 0x00 "PUWA6,User Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x21C++0x03 line.long 0x00 "PUWA7,User Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "PUWA8,User Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x224++0x03 line.long 0x00 "PUWA9,User Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x228++0x03 line.long 0x00 "PUWA10,User Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x22C++0x03 line.long 0x00 "PUWA11,User Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x230++0x03 line.long 0x00 "PUWA12,User Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x234++0x03 line.long 0x00 "PUWA13,User Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x238++0x03 line.long 0x00 "PUWA14,User Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x23C++0x03 line.long 0x00 "PUWA15,User Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x240++0x03 line.long 0x00 "PUWA16,User Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x244++0x03 line.long 0x00 "PUWA17,User Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x248++0x03 line.long 0x00 "PUWA18,User Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x24C++0x03 line.long 0x00 "PUWA19,User Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x250++0x03 line.long 0x00 "PUWA20,User Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x254++0x03 line.long 0x00 "PUWA21,User Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x258++0x03 line.long 0x00 "PUWA22,User Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x25C++0x03 line.long 0x00 "PUWA23,User Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x260++0x03 line.long 0x00 "PUWA24,User Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x264++0x03 line.long 0x00 "PUWA25,User Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x268++0x03 line.long 0x00 "PUWA26,User Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x26C++0x03 line.long 0x00 "PUWA27,User Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x270++0x03 line.long 0x00 "PUWA28,User Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x274++0x03 line.long 0x00 "PUWA29,User Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" else hgroup.long 0x0C++0x03 hide.long 0x00 "WPQCLR,Privileged Write Attribute Quick Clear Register" hgroup.long 0x10++0x03 hide.long 0x00 "WUQCLR,User Write Attribute Quick Clear Register" hgroup.long 0x14++0x03 hide.long 0x00 "RPQCLR,Privileged Read Attribute Quick Clear Register" hgroup.long 0x18++0x03 hide.long 0x00 "RUQCLR,User Read Attribute Quick Clear Register" rgroup.long 0x80++0x03 line.long 0x00 "PPR0,Privileged Read Attribute Register 0" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x84++0x03 line.long 0x00 "PPR1,Privileged Read Attribute Register 1" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x88++0x03 line.long 0x00 "PPR2,Privileged Read Attribute Register 2" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x8C++0x03 line.long 0x00 "PPR3,Privileged Read Attribute Register 3" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x90++0x03 line.long 0x00 "PPR4,Privileged Read Attribute Register 4" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x94++0x03 line.long 0x00 "PPR5,Privileged Read Attribute Register 5" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x98++0x03 line.long 0x00 "PPR6,Privileged Read Attribute Register 6" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x9C++0x03 line.long 0x00 "PPR7,Privileged Read Attribute Register 7" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xA0++0x03 line.long 0x00 "PPR8,Privileged Read Attribute Register 8" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xA4++0x03 line.long 0x00 "PPR9,Privileged Read Attribute Register 9" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xA8++0x03 line.long 0x00 "PPR10,Privileged Read Attribute Register 10" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xAC++0x03 line.long 0x00 "PPR11,Privileged Read Attribute Register 11" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xB0++0x03 line.long 0x00 "PPR12,Privileged Read Attribute Register 12" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xB4++0x03 line.long 0x00 "PPR13,Privileged Read Attribute Register 13" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xB8++0x03 line.long 0x00 "PPR14,Privileged Read Attribute Register 14" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xBC++0x03 line.long 0x00 "PPR15,Privileged Read Attribute Register 15" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xC0++0x03 line.long 0x00 "PPR16,Privileged Read Attribute Register 16" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xC4++0x03 line.long 0x00 "PPR17,Privileged Read Attribute Register 17" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xC8++0x03 line.long 0x00 "PPR18,Privileged Read Attribute Register 18" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xCC++0x03 line.long 0x00 "PPR19,Privileged Read Attribute Register 19" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xD0++0x03 line.long 0x00 "PPR20,Privileged Read Attribute Register 20" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xD4++0x03 line.long 0x00 "PPR21,Privileged Read Attribute Register 21" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xD8++0x03 line.long 0x00 "PPR22,Privileged Read Attribute Register 22" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xDC++0x03 line.long 0x00 "PPR23,Privileged Read Attribute Register 23" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xE0++0x03 line.long 0x00 "PPR24,Privileged Read Attribute Register 24" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xE4++0x03 line.long 0x00 "PPR25,Privileged Read Attribute Register 25" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xE8++0x03 line.long 0x00 "PPR26,Privileged Read Attribute Register 26" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xEC++0x03 line.long 0x00 "PPR27,Privileged Read Attribute Register 27" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xF0++0x03 line.long 0x00 "PPR28,Privileged Read Attribute Register 28" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xF4++0x03 line.long 0x00 "PPR29,Privileged Read Attribute Register 29" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x100++0x03 line.long 0x00 "PUR0,User Read Attribute Register 0" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x104++0x03 line.long 0x00 "PUR1,User Read Attribute Register 1" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x108++0x03 line.long 0x00 "PUR2,User Read Attribute Register 2" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x10C++0x03 line.long 0x00 "PUR3,User Read Attribute Register 3" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x110++0x03 line.long 0x00 "PUR4,User Read Attribute Register 4" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x114++0x03 line.long 0x00 "PUR5,User Read Attribute Register 5" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x118++0x03 line.long 0x00 "PUR6,User Read Attribute Register 6" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x11C++0x03 line.long 0x00 "PUR7,User Read Attribute Register 7" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x120++0x03 line.long 0x00 "PUR8,User Read Attribute Register 8" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x124++0x03 line.long 0x00 "PUR9,User Read Attribute Register 9" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x128++0x03 line.long 0x00 "PUR10,User Read Attribute Register 10" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x12C++0x03 line.long 0x00 "PUR11,User Read Attribute Register 11" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x130++0x03 line.long 0x00 "PUR12,User Read Attribute Register 12" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x134++0x03 line.long 0x00 "PUR13,User Read Attribute Register 13" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x138++0x03 line.long 0x00 "PUR14,User Read Attribute Register 14" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x13C++0x03 line.long 0x00 "PUR15,User Read Attribute Register 15" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x140++0x03 line.long 0x00 "PUR16,User Read Attribute Register 16" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x144++0x03 line.long 0x00 "PUR17,User Read Attribute Register 17" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x148++0x03 line.long 0x00 "PUR18,User Read Attribute Register 18" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x14C++0x03 line.long 0x00 "PUR19,User Read Attribute Register 19" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x150++0x03 line.long 0x00 "PUR20,User Read Attribute Register 20" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x154++0x03 line.long 0x00 "PUR21,User Read Attribute Register 21" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x158++0x03 line.long 0x00 "PUR22,User Read Attribute Register 22" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x15C++0x03 line.long 0x00 "PUR23,User Read Attribute Register 23" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x160++0x03 line.long 0x00 "PUR24,User Read Attribute Register 24" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x164++0x03 line.long 0x00 "PUR25,User Read Attribute Register 25" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x168++0x03 line.long 0x00 "PUR26,User Read Attribute Register 26" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x16C++0x03 line.long 0x00 "PUR27,User Read Attribute Register 27" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x170++0x03 line.long 0x00 "PUR28,User Read Attribute Register 28" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x174++0x03 line.long 0x00 "PUR29,User Read Attribute Register 29" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x180++0x03 line.long 0x00 "PPWA0,Privileged Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x184++0x03 line.long 0x00 "PPWA1,Privileged Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x188++0x03 line.long 0x00 "PPWA2,Privileged Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x18C++0x03 line.long 0x00 "PPWA3,Privileged Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x190++0x03 line.long 0x00 "PPWA4,Privileged Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x194++0x03 line.long 0x00 "PPWA5,Privileged Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x198++0x03 line.long 0x00 "PPWA6,Privileged Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x19C++0x03 line.long 0x00 "PPWA7,Privileged Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1A0++0x03 line.long 0x00 "PPWA8,Privileged Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1A4++0x03 line.long 0x00 "PPWA9,Privileged Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1A8++0x03 line.long 0x00 "PPWA10,Privileged Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1AC++0x03 line.long 0x00 "PPWA11,Privileged Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1B0++0x03 line.long 0x00 "PPWA12,Privileged Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1B4++0x03 line.long 0x00 "PPWA13,Privileged Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1B8++0x03 line.long 0x00 "PPWA14,Privileged Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1BC++0x03 line.long 0x00 "PPWA15,Privileged Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1C0++0x03 line.long 0x00 "PPWA16,Privileged Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1C4++0x03 line.long 0x00 "PPWA17,Privileged Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1C8++0x03 line.long 0x00 "PPWA18,Privileged Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1CC++0x03 line.long 0x00 "PPWA19,Privileged Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1D0++0x03 line.long 0x00 "PPWA20,Privileged Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1D4++0x03 line.long 0x00 "PPWA21,Privileged Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1D8++0x03 line.long 0x00 "PPWA22,Privileged Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1DC++0x03 line.long 0x00 "PPWA23,Privileged Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1E0++0x03 line.long 0x00 "PPWA24,Privileged Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1E4++0x03 line.long 0x00 "PPWA25,Privileged Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1E8++0x03 line.long 0x00 "PPWA26,Privileged Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1EC++0x03 line.long 0x00 "PPWA27,Privileged Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1F0++0x03 line.long 0x00 "PPWA28,Privileged Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1F4++0x03 line.long 0x00 "PPWA29,Privileged Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x200++0x03 line.long 0x00 "PUWA0,User Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x204++0x03 line.long 0x00 "PUWA1,User Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x208++0x03 line.long 0x00 "PUWA2,User Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x20C++0x03 line.long 0x00 "PUWA3,User Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x210++0x03 line.long 0x00 "PUWA4,User Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x214++0x03 line.long 0x00 "PUWA5,User Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x218++0x03 line.long 0x00 "PUWA6,User Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x21C++0x03 line.long 0x00 "PUWA7,User Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x220++0x03 line.long 0x00 "PUWA8,User Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x224++0x03 line.long 0x00 "PUWA9,User Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x228++0x03 line.long 0x00 "PUWA10,User Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x22C++0x03 line.long 0x00 "PUWA11,User Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x230++0x03 line.long 0x00 "PUWA12,User Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x234++0x03 line.long 0x00 "PUWA13,User Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x238++0x03 line.long 0x00 "PUWA14,User Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x23C++0x03 line.long 0x00 "PUWA15,User Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x240++0x03 line.long 0x00 "PUWA16,User Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x244++0x03 line.long 0x00 "PUWA17,User Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x248++0x03 line.long 0x00 "PUWA18,User Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x24C++0x03 line.long 0x00 "PUWA19,User Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x250++0x03 line.long 0x00 "PUWA20,User Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x254++0x03 line.long 0x00 "PUWA21,User Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x258++0x03 line.long 0x00 "PUWA22,User Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x25C++0x03 line.long 0x00 "PUWA23,User Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x260++0x03 line.long 0x00 "PUWA24,User Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x264++0x03 line.long 0x00 "PUWA25,User Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x268++0x03 line.long 0x00 "PUWA26,User Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x26C++0x03 line.long 0x00 "PUWA27,User Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x270++0x03 line.long 0x00 "PUWA28,User Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x274++0x03 line.long 0x00 "PUWA29,User Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" endif wgroup.long 0xF8++0x03 line.long 0x00 "LOCK0,Lock Register 0" wgroup.long 0x178++0x03 line.long 0x00 "LOCK1,Lock Register 1" wgroup.long 0x1F8++0x03 line.long 0x00 "LOCK2,Lock Register 2" wgroup.long 0x278++0x03 line.long 0x00 "LOCK3,Lock Register 3" wgroup.long 0x2F8++0x03 line.long 0x00 "LOCK4,Lock Register 4" if ((per.l(ad:0xB4750000+0x04)&0x01)==0x00) group.long 0x280++0x03 line.long 0x00 "PFEN0,Privilege Mode Forced Change Function Enable Register 0" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x284++0x03 line.long 0x00 "PFEN1,Privilege Mode Forced Change Function Enable Register 1" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x288++0x03 line.long 0x00 "PFEN2,Privilege Mode Forced Change Function Enable Register 2" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x28C++0x03 line.long 0x00 "PFEN3,Privilege Mode Forced Change Function Enable Register 3" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x290++0x03 line.long 0x00 "PFEN4,Privilege Mode Forced Change Function Enable Register 4" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x294++0x03 line.long 0x00 "PFEN5,Privilege Mode Forced Change Function Enable Register 5" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x298++0x03 line.long 0x00 "PFEN6,Privilege Mode Forced Change Function Enable Register 6" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x29C++0x03 line.long 0x00 "PFEN7,Privilege Mode Forced Change Function Enable Register 7" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2A0++0x03 line.long 0x00 "PFEN8,Privilege Mode Forced Change Function Enable Register 8" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2A4++0x03 line.long 0x00 "PFEN9,Privilege Mode Forced Change Function Enable Register 9" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2A8++0x03 line.long 0x00 "PFEN10,Privilege Mode Forced Change Function Enable Register 10" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2AC++0x03 line.long 0x00 "PFEN11,Privilege Mode Forced Change Function Enable Register 11" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2B0++0x03 line.long 0x00 "PFEN12,Privilege Mode Forced Change Function Enable Register 12" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2B4++0x03 line.long 0x00 "PFEN13,Privilege Mode Forced Change Function Enable Register 13" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2B8++0x03 line.long 0x00 "PFEN14,Privilege Mode Forced Change Function Enable Register 14" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2BC++0x03 line.long 0x00 "PFEN15,Privilege Mode Forced Change Function Enable Register 15" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2C0++0x03 line.long 0x00 "PFEN16,Privilege Mode Forced Change Function Enable Register 16" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2C4++0x03 line.long 0x00 "PFEN17,Privilege Mode Forced Change Function Enable Register 17" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2C8++0x03 line.long 0x00 "PFEN18,Privilege Mode Forced Change Function Enable Register 18" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2CC++0x03 line.long 0x00 "PFEN19,Privilege Mode Forced Change Function Enable Register 19" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2D0++0x03 line.long 0x00 "PFEN20,Privilege Mode Forced Change Function Enable Register 20" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2D4++0x03 line.long 0x00 "PFEN21,Privilege Mode Forced Change Function Enable Register 21" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2D8++0x03 line.long 0x00 "PFEN22,Privilege Mode Forced Change Function Enable Register 22" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2DC++0x03 line.long 0x00 "PFEN23,Privilege Mode Forced Change Function Enable Register 23" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2E0++0x03 line.long 0x00 "PFEN24,Privilege Mode Forced Change Function Enable Register 24" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2E4++0x03 line.long 0x00 "PFEN25,Privilege Mode Forced Change Function Enable Register 25" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2E8++0x03 line.long 0x00 "PFEN26,Privilege Mode Forced Change Function Enable Register 26" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2EC++0x03 line.long 0x00 "PFEN27,Privilege Mode Forced Change Function Enable Register 27" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2F0++0x03 line.long 0x00 "PFEN28,Privilege Mode Forced Change Function Enable Register 28" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2F4++0x03 line.long 0x00 "PFEN29,Privilege Mode Forced Change Function Enable Register 29" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" else rgroup.long 0x280++0x03 line.long 0x00 "PFEN0,Privilege Mode Forced Change Function Enable Register 0" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x284++0x03 line.long 0x00 "PFEN1,Privilege Mode Forced Change Function Enable Register 1" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x288++0x03 line.long 0x00 "PFEN2,Privilege Mode Forced Change Function Enable Register 2" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x28C++0x03 line.long 0x00 "PFEN3,Privilege Mode Forced Change Function Enable Register 3" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x290++0x03 line.long 0x00 "PFEN4,Privilege Mode Forced Change Function Enable Register 4" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x294++0x03 line.long 0x00 "PFEN5,Privilege Mode Forced Change Function Enable Register 5" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x298++0x03 line.long 0x00 "PFEN6,Privilege Mode Forced Change Function Enable Register 6" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x29C++0x03 line.long 0x00 "PFEN7,Privilege Mode Forced Change Function Enable Register 7" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2A0++0x03 line.long 0x00 "PFEN8,Privilege Mode Forced Change Function Enable Register 8" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2A4++0x03 line.long 0x00 "PFEN9,Privilege Mode Forced Change Function Enable Register 9" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2A8++0x03 line.long 0x00 "PFEN10,Privilege Mode Forced Change Function Enable Register 10" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2AC++0x03 line.long 0x00 "PFEN11,Privilege Mode Forced Change Function Enable Register 11" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2B0++0x03 line.long 0x00 "PFEN12,Privilege Mode Forced Change Function Enable Register 12" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2B4++0x03 line.long 0x00 "PFEN13,Privilege Mode Forced Change Function Enable Register 13" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2B8++0x03 line.long 0x00 "PFEN14,Privilege Mode Forced Change Function Enable Register 14" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2BC++0x03 line.long 0x00 "PFEN15,Privilege Mode Forced Change Function Enable Register 15" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2C0++0x03 line.long 0x00 "PFEN16,Privilege Mode Forced Change Function Enable Register 16" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2C4++0x03 line.long 0x00 "PFEN17,Privilege Mode Forced Change Function Enable Register 17" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2C8++0x03 line.long 0x00 "PFEN18,Privilege Mode Forced Change Function Enable Register 18" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2CC++0x03 line.long 0x00 "PFEN19,Privilege Mode Forced Change Function Enable Register 19" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2D0++0x03 line.long 0x00 "PFEN20,Privilege Mode Forced Change Function Enable Register 20" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2D4++0x03 line.long 0x00 "PFEN21,Privilege Mode Forced Change Function Enable Register 21" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2D8++0x03 line.long 0x00 "PFEN22,Privilege Mode Forced Change Function Enable Register 22" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2DC++0x03 line.long 0x00 "PFEN23,Privilege Mode Forced Change Function Enable Register 23" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2E0++0x03 line.long 0x00 "PFEN24,Privilege Mode Forced Change Function Enable Register 24" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2E4++0x03 line.long 0x00 "PFEN25,Privilege Mode Forced Change Function Enable Register 25" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2E8++0x03 line.long 0x00 "PFEN26,Privilege Mode Forced Change Function Enable Register 26" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2EC++0x03 line.long 0x00 "PFEN27,Privilege Mode Forced Change Function Enable Register 27" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2F0++0x03 line.long 0x00 "PFEN28,Privilege Mode Forced Change Function Enable Register 28" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2F4++0x03 line.long 0x00 "PFEN29,Privilege Mode Forced Change Function Enable Register 29" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" endif width 0x0B tree.end tree "DDRHSSPI (DDR High Speed SPI Controller)" base ad:0xB0101000 width 19. if (((per.l(ad:0xB0101000))&0x02)==0x02) group.long 0x00++0x03 line.long 0x00 "MCTRL,Module Control Register" bitfld.long 0x00 5. " DLPEN ,Data learning pattern enable" "Disabled,Enabled" rbitfld.long 0x00 4. " MES ,Module enable status" "Disabled,Enabled" bitfld.long 0x00 1. " CSEN ,Command sequencer mode enable" "Direct mode,Command Sequencer mode" newline bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "MCTRL,Module Control Register" rbitfld.long 0x00 4. " MES ,Module enable status" "Disabled,Enabled" bitfld.long 0x00 1. " CSEN ,Command sequencer mode enable" "Direct mode,Command Sequencer mode" newline bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled" endif if (((per.b(ad:0xB0101000+0x3B))&0x20)==0x20) group.long 0x4++0x03 line.long 0x00 "PCC0,Peripheral Communication Configuration Register 0" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" else group.long 0x4++0x03 line.long 0x00 "PCC0,Peripheral Communication Configuration Register 0" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" newline bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes" endif if (((per.b(ad:0xB0101000+0x3B))&0x20)==0x20) group.long 0x8++0x03 line.long 0x00 "PCC1,Peripheral Communication Configuration Register 1" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" else group.long 0x8++0x03 line.long 0x00 "PCC1,Peripheral Communication Configuration Register 1" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" newline bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes" endif if (((per.b(ad:0xB0101000+0x3B))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "PCC2,Peripheral Communication Configuration Register 2" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" else group.long 0xC++0x03 line.long 0x00 "PCC2,Peripheral Communication Configuration Register 2" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" newline bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes" endif if (((per.b(ad:0xB0101000+0x3B))&0x20)==0x20) group.long 0x10++0x03 line.long 0x00 "PCC3,Peripheral Communication Configuration Register 3" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" else group.long 0x10++0x03 line.long 0x00 "PCC3,Peripheral Communication Configuration Register 3" bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK" bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3" newline bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes" endif group.long 0x14++0x03 line.long 0x00 "TXF_SET/CLR,TX Interrupt Flag Register" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TSSRS ,Slave select released" "Not generated,Generated" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TFMTS ,TX-FIFO fill level is more than threshold" "No,Yes" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TFLETS ,TX-FIFO fill level is less than or equal to threshold" "No,Yes" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TFOS ,TX-FIFO overrun" "No,Yes" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TFES ,TX-FIFO and shift register are empty" "Not empty,Empty" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TFFS ,TX-FIFO full" "Not full,Full" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") if (((per.l(ad:0xB0101000+0x120)))==(0x00000100||0x00000300)) group.long 0x20++0x03 line.long 0x00 "RXF,RX Interrupt Flag Register" bitfld.long 0x00 8. " TEST ,Test" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DLPERR_SET/CLR ,Data learning pattern reception error" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RSSRS_SET/CLR ,Slave select released" "Not generated,Generated" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RFMTS_SET/CLR ,RX-FIFO fill level is more than threshold" "No,Yes" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RFLETS_SET/CLR ,RX-FIFO fill level is less than or equal to threshold" "No,Yes" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RFUS_SET/CLR ,RX-FIFO underrun" "No,Yes" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RFES_SET/CLR ,RX-FIFO empty" "Not empty,Empty" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RFFS_SET/CLR ,RX-FIFO full" "Not full,Full" else group.long 0x20++0x03 line.long 0x00 "RXF,RX Interrupt Flag Register" bitfld.long 0x00 8. " TEST ,Test" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RSSRS_SET/CLR ,Slave select released" "Not generated,Generated" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RFMTS_SET/CLR ,RX-FIFO fill level is more than threshold" "No,Yes" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RFLETS_SET/CLR ,RX-FIFO fill level is less than or equal to threshold" "No,Yes" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RFUS_SET/CLR ,RX-FIFO underrun" "No,Yes" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RFES_SET/CLR ,RX-FIFO empty" "Not empty,Empty" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RFFS_SET/CLR ,RX-FIFO full" "Not full,Full" endif elif cpuis("S6J336*")||cpuis("S6J337*") group.long 0x20++0x03 line.long 0x00 "RXF,RX Interrupt Flag Register" bitfld.long 0x00 8. " TEST ,Test" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DLPERR_SET/CLR ,Data learning pattern reception error" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RSSRS_SET/CLR ,Slave select released" "Not generated,Generated" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RFMTS_SET/CLR ,RX-FIFO fill level is more than threshold" "No,Yes" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RFLETS_SET/CLR ,RX-FIFO fill level is less than or equal to threshold" "No,Yes" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RFUS_SET/CLR ,RX-FIFO underrun" "No,Yes" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RFES_SET/CLR ,RX-FIFO empty" "Not empty,Empty" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RFFS_SET/CLR ,RX-FIFO full" "Not full,Full" else if (((per.l(ad:0xB0101000+0x120))&0x00000100)==0x00000100) group.long 0x20++0x03 line.long 0x00 "RXF,RX Interrupt Flag Register" bitfld.long 0x00 8. " TEST ,Test" "0,1" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DLPERR_SET/CLR ,Data learning pattern reception error" "No error,Error" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RSSRS_SET/CLR ,Slave select released" "Not generated,Generated" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RFMTS_SET/CLR ,RX-FIFO fill level is more than threshold" "No,Yes" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RFLETS_SET/CLR ,RX-FIFO fill level is less than or equal to threshold" "No,Yes" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RFUS_SET/CLR ,RX-FIFO underrun" "No,Yes" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RFES_SET/CLR ,RX-FIFO empty" "Not empty,Empty" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RFFS_SET/CLR ,RX-FIFO full" "Not full,Full" else group.long 0x20++0x03 line.long 0x00 "RXF,RX Interrupt Flag Register" bitfld.long 0x00 8. " TEST ,Test" "0,1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RSSRS_SET/CLR ,Slave select released" "Not generated,Generated" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RFMTS_SET/CLR ,RX-FIFO fill level is more than threshold" "No,Yes" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RFLETS_SET/CLR ,RX-FIFO fill level is less than or equal to threshold" "No,Yes" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RFUS_SET/CLR ,RX-FIFO underrun" "No,Yes" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RFES_SET/CLR ,RX-FIFO empty" "Not empty,Empty" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RFFS_SET/CLR ,RX-FIFO full" "Not full,Full" endif endif rgroup.long 0x2C++0x03 line.long 0x00 "FAULTF,Fault Status Flag Register" bitfld.long 0x00 6. " DLPFS ,DLP error fault" "Not detected,Detected" bitfld.long 0x00 4. " DRCBSFS ,DMA read channel block size fault" "Not detected,Detected" bitfld.long 0x00 3. " DWCBSFS ,DMA write channel block size fault" "Not detected,Detected" newline bitfld.long 0x00 2. " PVFS ,Protection violation fault" "Not detected,Detected" bitfld.long 0x00 0. " UMAFS ,Unmapped memory access fault" "Not detected,Detected" wgroup.long 0x30++0x03 line.long 0x00 "FAULTC,Fault Status Flag Clear Register" bitfld.long 0x00 6. " DLPFS ,DLP error fault clear" "No effect,Clear" bitfld.long 0x00 4. " DRCBSFS ,DMA read channel block size fault clear" "No effect,Clear" bitfld.long 0x00 3. " DWCBSFS ,DMA write channel block size fault clear" "No effect,Clear" newline bitfld.long 0x00 2. " PVFS ,Protection violation fault clear" "No effect,Clear" bitfld.long 0x00 0. " UMAFS ,Unmapped memory access fault clear" "No effect,Clear" if (((per.l(ad:0xB0101000))&0x02)==0x00) group.byte 0x34++0x01 line.byte 0x00 "DMCFG,Direct Mode Configuration Register" bitfld.byte 0x00 1. " SSDC ,Slave select deassertion control" ",Byte counter mode" line.byte 0x01 "DMAEN,DMA Enable Register" bitfld.byte 0x01 1. " TXDMAEN ,TX DMA enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXDMAEN ,RX DMA enable" "Disabled,Enabled" group.byte 0x38++0x00 line.byte 0x00 "DMSTART,Direct Mode Start Register" bitfld.byte 0x00 0. " START ,Start transfer" "No effect,Start" group.byte 0x3A++0x00 line.byte 0x00 "DMPSEL,Direct Mode Peripheral Select Register" bitfld.byte 0x00 0.--1. " PSEL ,Peripheral select" "0,1,2,3" else hgroup.byte 0x34++0x00 hide.byte 0x00 "DMCFG,Direct Mode Configuration Register" hgroup.byte 0x35++0x00 hide.byte 0x00 "DMAEN,DMA Enable Register" hgroup.byte 0x38++0x00 hide.byte 0x00 "DMSTART,Direct Mode Start Register" hgroup.byte 0x3A++0x00 hide.byte 0x00 "DMPSEL,Direct Mode Peripheral Select Register" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") if (((per.l(ad:0xB0101000))&0x02)==0x00)&&(((per.l(ad:0xB0101000+0x120)))==(0x00000100||0x00000300)) group.byte 0x3B++0x00 line.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR" bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol[duplex/protocol]" "TX and RX/Legacy,,,TX and RX/Octal,,,,,TX only/Legacy,,TX only/Quad,TX only/Octal,?..." elif (((per.l(ad:0xB0101000))&0x02)==0x00)&&(((per.l(ad:0xB0101000+0x120)))!=0x00000100)&&(((per.l(ad:0xB0101000+0x120)))!=0x00000300) group.byte 0x3B++0x00 line.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR" bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol[duplex/protocol]" "TX and RX/Legacy,,,,,,,,TX only/Legacy,,TX only/Quad,?..." else hgroup.byte 0x3B++0x00 hide.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" endif elif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000))&0x02)==0x00) group.byte 0x3B++0x00 line.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR" bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol[duplex/protocol]" "TX and RX/Legacy,,,TX and RX/Octal,,,,,TX only/Legacy,,TX only/Quad,TX only/Octal,?..." else hgroup.byte 0x3B++0x00 hide.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" endif else if (((per.l(ad:0xB0101000))&0x02)==0x00)&&(((per.l(ad:0xB0101000+0x120))&0x00000100)==0x00000100) group.byte 0x3B++0x00 line.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR" bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol[duplex/protocol]" "TX and RX/Legacy,,,TX and RX/Octal,,,,,TX only/Legacy,,TX only/Quad,TX only/Octal,?..." elif (((per.l(ad:0xB0101000))&0x02)==0x00)&&(((per.l(ad:0xB0101000+0x120))&0x00000100)!=0x00000100) group.byte 0x3B++0x00 line.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR" bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol[duplex/protocol]" "TX and RX/Legacy,,,,,,,,TX only/Legacy,,TX only/Quad,?..." else hgroup.byte 0x3B++0x00 hide.byte 0x00 "DMTRP,Direct Mode Transfer Protocol Register" endif endif if (((per.l(ad:0xB0101000))&0x02)==0x00)&&(((per.b(ad:0xB0101000+0x34))&0x02)==0x02) group.word 0x3C++0x01 line.word 0x00 "DMBCC,Byte Count Control Register" else hgroup.word 0x3C++0x01 hide.word 0x00 "DMBCC,Byte Count Control Register" endif if (((per.l(ad:0xB0101000+0x00))&0x02)==0x00)&&(((per.b(ad:0xB0101000+0x34))&0x02)==0x02) sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") rgroup.word 0x3E++0x01 line.word 0x00 "DMBCS,Byte Count Status Register" else group.word 0x3E++0x01 line.word 0x00 "DMBCS,Byte Count Status Register" endif else hgroup.word 0x3E++0x01 hide.word 0x00 "DMBCS,Byte Count Status Register" endif if (((per.l(ad:0xB0101000+0x00))&0x02)==0x00) sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") rgroup.long 0x40++0x03 line.long 0x00 "DMFIFOSTATUS,Direct Mode FIFO Status Register" bitfld.long 0x00 16. " SSACTIVE ,Slave select active" "Inactive,Active" bitfld.long 0x00 8.--12. " TXFLEVEL ,Current fill level of TX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RXFLEVEL ,Current fill level of RX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x40++0x03 line.long 0x00 "DMFIFOSTATUS,Direct Mode FIFO Status Register" bitfld.long 0x00 16. " SSACTIVE ,Slave select active" "Inactive,Active" bitfld.long 0x00 8.--12. " TXFLEVEL ,Current fill level of TX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RXFLEVEL ,Current fill level of RX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else hgroup.long 0x40++0x03 hide.long 0x00 "DMFIFOSTATUS,Direct Mode FIFO Status Register" endif group.long 0x44++0x03 line.long 0x00 "DMFIFOCFG,Direct Mode FIFO Configuration Register" bitfld.long 0x00 20. " TXFLSH ,TX-FIFO flush" "No effect,Flush" bitfld.long 0x00 19. " RXFLSH ,RX-FIFO flush" "No effect,Flush" bitfld.long 0x00 18. " TXCTRL ,TXCTRL bit to be written to TX-FIFO" "0,1" newline sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 16.--17. " FWIDTH ,FIFO width" "8-bit,16-bit,,32-bit" else bitfld.long 0x00 16.--17. " FWIDTH ,FIFO width" "8-bit,16-bit,32-bit,?..." endif bitfld.long 0x00 8.--12. " TXFTH ,TX-FIFO threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." bitfld.long 0x00 0.--4. " RXFTH ,RX-FIFO threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." if (((per.l(ad:0xB0101000))&0x02)==0x00) wgroup.long 0x48++0x03 line.long 0x00 "TXFIFO0,TX-FIFO Data Register 0" wgroup.long 0x4C++0x03 line.long 0x00 "TXFIFO1,TX-FIFO Data Register 1" wgroup.long 0x50++0x03 line.long 0x00 "TXFIFO2,TX-FIFO Data Register 2" wgroup.long 0x54++0x03 line.long 0x00 "TXFIFO3,TX-FIFO Data Register 3" wgroup.long 0x58++0x03 line.long 0x00 "TXFIFO4,TX-FIFO Data Register 4" wgroup.long 0x5C++0x03 line.long 0x00 "TXFIFO5,TX-FIFO Data Register 5" wgroup.long 0x60++0x03 line.long 0x00 "TXFIFO6,TX-FIFO Data Register 6" wgroup.long 0x64++0x03 line.long 0x00 "TXFIFO7,TX-FIFO Data Register 7" wgroup.long 0x68++0x03 line.long 0x00 "TXFIFO8,TX-FIFO Data Register 8" wgroup.long 0x6C++0x03 line.long 0x00 "TXFIFO9,TX-FIFO Data Register 9" wgroup.long 0x70++0x03 line.long 0x00 "TXFIFO10,TX-FIFO Data Register 10" wgroup.long 0x74++0x03 line.long 0x00 "TXFIFO11,TX-FIFO Data Register 11" wgroup.long 0x78++0x03 line.long 0x00 "TXFIFO12,TX-FIFO Data Register 12" wgroup.long 0x7C++0x03 line.long 0x00 "TXFIFO13,TX-FIFO Data Register 13" wgroup.long 0x80++0x03 line.long 0x00 "TXFIFO14,TX-FIFO Data Register 14" wgroup.long 0x84++0x03 line.long 0x00 "TXFIFO15,TX-FIFO Data Register 15" wgroup.long 0x88++0x03 line.long 0x00 "TXFIFO16,TX-FIFO Data Register 16" wgroup.long 0x8C++0x03 line.long 0x00 "TXFIFO17,TX-FIFO Data Register 17" wgroup.long 0x90++0x03 line.long 0x00 "TXFIFO18,TX-FIFO Data Register 18" wgroup.long 0x94++0x03 line.long 0x00 "TXFIFO19,TX-FIFO Data Register 19" wgroup.long 0x98++0x03 line.long 0x00 "TXFIFO20,TX-FIFO Data Register 20" wgroup.long 0x9C++0x03 line.long 0x00 "TXFIFO21,TX-FIFO Data Register 21" wgroup.long 0xA0++0x03 line.long 0x00 "TXFIFO22,TX-FIFO Data Register 22" wgroup.long 0xA4++0x03 line.long 0x00 "TXFIFO23,TX-FIFO Data Register 23" else hgroup.long 0x48++0x03 hide.long 0x00 "TXFIFO0,TX-FIFO Data Register 0" hgroup.long 0x4C++0x03 hide.long 0x00 "TXFIFO1,TX-FIFO Data Register 1" hgroup.long 0x50++0x03 hide.long 0x00 "TXFIFO2,TX-FIFO Data Register 2" hgroup.long 0x54++0x03 hide.long 0x00 "TXFIFO3,TX-FIFO Data Register 3" hgroup.long 0x58++0x03 hide.long 0x00 "TXFIFO4,TX-FIFO Data Register 4" hgroup.long 0x5C++0x03 hide.long 0x00 "TXFIFO5,TX-FIFO Data Register 5" hgroup.long 0x60++0x03 hide.long 0x00 "TXFIFO6,TX-FIFO Data Register 6" hgroup.long 0x64++0x03 hide.long 0x00 "TXFIFO7,TX-FIFO Data Register 7" hgroup.long 0x68++0x03 hide.long 0x00 "TXFIFO8,TX-FIFO Data Register 8" hgroup.long 0x6C++0x03 hide.long 0x00 "TXFIFO9,TX-FIFO Data Register 9" hgroup.long 0x70++0x03 hide.long 0x00 "TXFIFO10,TX-FIFO Data Register 10" hgroup.long 0x74++0x03 hide.long 0x00 "TXFIFO11,TX-FIFO Data Register 11" hgroup.long 0x78++0x03 hide.long 0x00 "TXFIFO12,TX-FIFO Data Register 12" hgroup.long 0x7C++0x03 hide.long 0x00 "TXFIFO13,TX-FIFO Data Register 13" hgroup.long 0x80++0x03 hide.long 0x00 "TXFIFO14,TX-FIFO Data Register 14" hgroup.long 0x84++0x03 hide.long 0x00 "TXFIFO15,TX-FIFO Data Register 15" hgroup.long 0x88++0x03 hide.long 0x00 "TXFIFO16,TX-FIFO Data Register 16" hgroup.long 0x8C++0x03 hide.long 0x00 "TXFIFO17,TX-FIFO Data Register 17" hgroup.long 0x90++0x03 hide.long 0x00 "TXFIFO18,TX-FIFO Data Register 18" hgroup.long 0x94++0x03 hide.long 0x00 "TXFIFO19,TX-FIFO Data Register 19" hgroup.long 0x98++0x03 hide.long 0x00 "TXFIFO20,TX-FIFO Data Register 20" hgroup.long 0x9C++0x03 hide.long 0x00 "TXFIFO21,TX-FIFO Data Register 21" hgroup.long 0xA0++0x03 hide.long 0x00 "TXFIFO22,TX-FIFO Data Register 22" hgroup.long 0xA4++0x03 hide.long 0x00 "TXFIFO23,TX-FIFO Data Register 23" endif if (((per.l(ad:0xB0101000))&0x02)==0x00) hgroup.long 0xA8++0x03 hide.long 0x00 "RXFIFO0,RX-FIFO Data Register 0" in hgroup.long 0xAC++0x03 hide.long 0x00 "RXFIFO1,RX-FIFO Data Register 1" in hgroup.long 0xB0++0x03 hide.long 0x00 "RXFIFO2,RX-FIFO Data Register 2" in hgroup.long 0xB4++0x03 hide.long 0x00 "RXFIFO3,RX-FIFO Data Register 3" in hgroup.long 0xB8++0x03 hide.long 0x00 "RXFIFO4,RX-FIFO Data Register 4" in hgroup.long 0xBC++0x03 hide.long 0x00 "RXFIFO5,RX-FIFO Data Register 5" in hgroup.long 0xC0++0x03 hide.long 0x00 "RXFIFO6,RX-FIFO Data Register 6" in hgroup.long 0xC4++0x03 hide.long 0x00 "RXFIFO7,RX-FIFO Data Register 7" in hgroup.long 0xC8++0x03 hide.long 0x00 "RXFIFO8,RX-FIFO Data Register 8" in hgroup.long 0xCC++0x03 hide.long 0x00 "RXFIFO9,RX-FIFO Data Register 9" in hgroup.long 0xD0++0x03 hide.long 0x00 "RXFIFO10,RX-FIFO Data Register 10" in hgroup.long 0xD4++0x03 hide.long 0x00 "RXFIFO11,RX-FIFO Data Register 11" in hgroup.long 0xD8++0x03 hide.long 0x00 "RXFIFO12,RX-FIFO Data Register 12" in hgroup.long 0xDC++0x03 hide.long 0x00 "RXFIFO13,RX-FIFO Data Register 13" in hgroup.long 0xE0++0x03 hide.long 0x00 "RXFIFO14,RX-FIFO Data Register 14" in hgroup.long 0xE4++0x03 hide.long 0x00 "RXFIFO15,RX-FIFO Data Register 15" in hgroup.long 0xE8++0x03 hide.long 0x00 "RXFIFO16,RX-FIFO Data Register 16" in hgroup.long 0xEC++0x03 hide.long 0x00 "RXFIFO17,RX-FIFO Data Register 17" in hgroup.long 0xF0++0x03 hide.long 0x00 "RXFIFO18,RX-FIFO Data Register 18" in hgroup.long 0xF4++0x03 hide.long 0x00 "RXFIFO19,RX-FIFO Data Register 19" in hgroup.long 0xF8++0x03 hide.long 0x00 "RXFIFO20,RX-FIFO Data Register 20" in hgroup.long 0xFC++0x03 hide.long 0x00 "RXFIFO21,RX-FIFO Data Register 21" in hgroup.long 0x100++0x03 hide.long 0x00 "RXFIFO22,RX-FIFO Data Register 22" in hgroup.long 0x104++0x03 hide.long 0x00 "RXFIFO23,RX-FIFO Data Register 23" in else hgroup.long 0xA8++0x03 hide.long 0x00 "RXFIFO0,RX-FIFO Data Register 0" hgroup.long 0xAC++0x03 hide.long 0x00 "RXFIFO1,RX-FIFO Data Register 1" hgroup.long 0xB0++0x03 hide.long 0x00 "RXFIFO2,RX-FIFO Data Register 2" hgroup.long 0xB4++0x03 hide.long 0x00 "RXFIFO3,RX-FIFO Data Register 3" hgroup.long 0xB8++0x03 hide.long 0x00 "RXFIFO4,RX-FIFO Data Register 4" hgroup.long 0xBC++0x03 hide.long 0x00 "RXFIFO5,RX-FIFO Data Register 5" hgroup.long 0xC0++0x03 hide.long 0x00 "RXFIFO6,RX-FIFO Data Register 6" hgroup.long 0xC4++0x03 hide.long 0x00 "RXFIFO7,RX-FIFO Data Register 7" hgroup.long 0xC8++0x03 hide.long 0x00 "RXFIFO8,RX-FIFO Data Register 8" hgroup.long 0xCC++0x03 hide.long 0x00 "RXFIFO9,RX-FIFO Data Register 9" hgroup.long 0xD0++0x03 hide.long 0x00 "RXFIFO10,RX-FIFO Data Register 10" hgroup.long 0xD4++0x03 hide.long 0x00 "RXFIFO11,RX-FIFO Data Register 11" hgroup.long 0xD8++0x03 hide.long 0x00 "RXFIFO12,RX-FIFO Data Register 12" hgroup.long 0xDC++0x03 hide.long 0x00 "RXFIFO13,RX-FIFO Data Register 13" hgroup.long 0xE0++0x03 hide.long 0x00 "RXFIFO14,RX-FIFO Data Register 14" hgroup.long 0xE4++0x03 hide.long 0x00 "RXFIFO15,RX-FIFO Data Register 15" hgroup.long 0xE8++0x03 hide.long 0x00 "RXFIFO16,RX-FIFO Data Register 16" hgroup.long 0xEC++0x03 hide.long 0x00 "RXFIFO17,RX-FIFO Data Register 17" hgroup.long 0xF0++0x03 hide.long 0x00 "RXFIFO18,RX-FIFO Data Register 18" hgroup.long 0xF4++0x03 hide.long 0x00 "RXFIFO19,RX-FIFO Data Register 19" hgroup.long 0xF8++0x03 hide.long 0x00 "RXFIFO20,RX-FIFO Data Register 20" hgroup.long 0xFC++0x03 hide.long 0x00 "RXFIFO21,RX-FIFO Data Register 21" hgroup.long 0x100++0x03 hide.long 0x00 "RXFIFO22,RX-FIFO Data Register 22" hgroup.long 0x104++0x03 hide.long 0x00 "RXFIFO23,RX-FIFO Data Register 23" endif if (((per.l(ad:0xB0101000))&0x02)==0x02) sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x108))&0x01)==0x00) group.word 0x108++0x01 line.word 0x00 "RDCSDC0,Read Command Sequencer Data/Control Register 0" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x108))&0x700)==0x400) group.word 0x108++0x01 line.word 0x00 "RDCSDC0,Read Command Sequencer Data/Control Register 0" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x108++0x01 line.word 0x00 "RDCSDC0,Read Command Sequencer Data/Control Register 0" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x108++0x01 line.word 0x00 "RDCSDC0,Read Command Sequencer Data/Control Register 0" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x10A))&0x01)==0x00) group.word 0x10A++0x01 line.word 0x00 "RDCSDC1,Read Command Sequencer Data/Control Register 1" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x10A))&0x700)==0x400) group.word 0x10A++0x01 line.word 0x00 "RDCSDC1,Read Command Sequencer Data/Control Register 1" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x10A++0x01 line.word 0x00 "RDCSDC1,Read Command Sequencer Data/Control Register 1" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x10A++0x01 line.word 0x00 "RDCSDC1,Read Command Sequencer Data/Control Register 1" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x10C))&0x01)==0x00) group.word 0x10C++0x01 line.word 0x00 "RDCSDC2,Read Command Sequencer Data/Control Register 2" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x10C))&0x700)==0x400) group.word 0x10C++0x01 line.word 0x00 "RDCSDC2,Read Command Sequencer Data/Control Register 2" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x10C++0x01 line.word 0x00 "RDCSDC2,Read Command Sequencer Data/Control Register 2" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x10C++0x01 line.word 0x00 "RDCSDC2,Read Command Sequencer Data/Control Register 2" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x10E))&0x01)==0x00) group.word 0x10E++0x01 line.word 0x00 "RDCSDC3,Read Command Sequencer Data/Control Register 3" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x10E))&0x700)==0x400) group.word 0x10E++0x01 line.word 0x00 "RDCSDC3,Read Command Sequencer Data/Control Register 3" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x10E++0x01 line.word 0x00 "RDCSDC3,Read Command Sequencer Data/Control Register 3" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x10E++0x01 line.word 0x00 "RDCSDC3,Read Command Sequencer Data/Control Register 3" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x110))&0x01)==0x00) group.word 0x110++0x01 line.word 0x00 "RDCSDC4,Read Command Sequencer Data/Control Register 4" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x110))&0x700)==0x400) group.word 0x110++0x01 line.word 0x00 "RDCSDC4,Read Command Sequencer Data/Control Register 4" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x110++0x01 line.word 0x00 "RDCSDC4,Read Command Sequencer Data/Control Register 4" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x110++0x01 line.word 0x00 "RDCSDC4,Read Command Sequencer Data/Control Register 4" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x112))&0x01)==0x00) group.word 0x112++0x01 line.word 0x00 "RDCSDC5,Read Command Sequencer Data/Control Register 5" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x112))&0x700)==0x400) group.word 0x112++0x01 line.word 0x00 "RDCSDC5,Read Command Sequencer Data/Control Register 5" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x112++0x01 line.word 0x00 "RDCSDC5,Read Command Sequencer Data/Control Register 5" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x112++0x01 line.word 0x00 "RDCSDC5,Read Command Sequencer Data/Control Register 5" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x114))&0x01)==0x00) group.word 0x114++0x01 line.word 0x00 "RDCSDC6,Read Command Sequencer Data/Control Register 6" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x114))&0x700)==0x400) group.word 0x114++0x01 line.word 0x00 "RDCSDC6,Read Command Sequencer Data/Control Register 6" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x114++0x01 line.word 0x00 "RDCSDC6,Read Command Sequencer Data/Control Register 6" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x114++0x01 line.word 0x00 "RDCSDC6,Read Command Sequencer Data/Control Register 6" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x116))&0x01)==0x00) group.word 0x116++0x01 line.word 0x00 "RDCSDC7,Read Command Sequencer Data/Control Register 7" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x116))&0x700)==0x400) group.word 0x116++0x01 line.word 0x00 "RDCSDC7,Read Command Sequencer Data/Control Register 7" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x116++0x01 line.word 0x00 "RDCSDC7,Read Command Sequencer Data/Control Register 7" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x116++0x01 line.word 0x00 "RDCSDC7,Read Command Sequencer Data/Control Register 7" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x118))&0x01)==0x00) group.word 0x118++0x01 line.word 0x00 "RDCSDC8,Read Command Sequencer Data/Control Register 8" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x118))&0x700)==0x400) group.word 0x118++0x01 line.word 0x00 "RDCSDC8,Read Command Sequencer Data/Control Register 8" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x118++0x01 line.word 0x00 "RDCSDC8,Read Command Sequencer Data/Control Register 8" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x118++0x01 line.word 0x00 "RDCSDC8,Read Command Sequencer Data/Control Register 8" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x11A))&0x01)==0x00) group.word 0x11A++0x01 line.word 0x00 "RDCSDC9,Read Command Sequencer Data/Control Register 9" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x11A))&0x700)==0x400) group.word 0x11A++0x01 line.word 0x00 "RDCSDC9,Read Command Sequencer Data/Control Register 9" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x11A++0x01 line.word 0x00 "RDCSDC9,Read Command Sequencer Data/Control Register 9" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x11A++0x01 line.word 0x00 "RDCSDC9,Read Command Sequencer Data/Control Register 9" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x11C))&0x01)==0x00) group.word 0x11C++0x01 line.word 0x00 "RDCSDC10,Read Command Sequencer Data/Control Register 10" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x11C))&0x700)==0x400) group.word 0x11C++0x01 line.word 0x00 "RDCSDC10,Read Command Sequencer Data/Control Register 10" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x11C++0x01 line.word 0x00 "RDCSDC10,Read Command Sequencer Data/Control Register 10" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x11C++0x01 line.word 0x00 "RDCSDC10,Read Command Sequencer Data/Control Register 10" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x11E))&0x01)==0x00) group.word 0x11E++0x01 line.word 0x00 "RDCSDC11,Read Command Sequencer Data/Control Register 11" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else if (((per.l(ad:0xB0101000+0x11E))&0x700)==0x400) group.word 0x11E++0x01 line.word 0x00 "RDCSDC11,Read Command Sequencer Data/Control Register 11" bitfld.word 0x00 11.--15. " RDCSDATA[7:3] ,Dummy cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" else group.word 0x11E++0x01 line.word 0x00 "RDCSDC11,Read Command Sequencer Data/Control Register 11" bitfld.word 0x00 8.--10. " RDCSDATA[2:0] ,Control byte for memory-read transactions[2:0]" "[7:0],[15:8],[23:16],[31:24],Dummy cycle,,,End of list" newline bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif endif else group.word 0x11E++0x01 line.word 0x00 "RDCSDC11,Read Command Sequencer Data/Control Register 11" hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions" bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded" endif else hgroup.word 0x108++0x01 hide.word 0x00 "RDCSDC0,Read Command Sequencer Data/Control Register 0" hgroup.word 0x10A++0x01 hide.word 0x00 "RDCSDC1,Read Command Sequencer Data/Control Register 1" hgroup.word 0x10C++0x01 hide.word 0x00 "RDCSDC2,Read Command Sequencer Data/Control Register 2" hgroup.word 0x10E++0x01 hide.word 0x00 "RDCSDC3,Read Command Sequencer Data/Control Register 3" hgroup.word 0x110++0x01 hide.word 0x00 "RDCSDC4,Read Command Sequencer Data/Control Register 4" hgroup.word 0x112++0x01 hide.word 0x00 "RDCSDC5,Read Command Sequencer Data/Control Register 5" hgroup.word 0x114++0x01 hide.word 0x00 "RDCSDC6,Read Command Sequencer Data/Control Register 6" hgroup.word 0x116++0x01 hide.word 0x00 "RDCSDC7,Read Command Sequencer Data/Control Register 7" hgroup.word 0x118++0x01 hide.word 0x00 "RDCSDC8,Read Command Sequencer Data/Control Register 8" hgroup.word 0x11A++0x01 hide.word 0x00 "RDCSDC9,Read Command Sequencer Data/Control Register 9" hgroup.word 0x11C++0x01 hide.word 0x00 "RDCSDC10,Read Command Sequencer Data/Control Register 10" hgroup.word 0x11E++0x01 hide.word 0x00 "RDCSDC11,Read Command Sequencer Data/Control Register 11" endif rgroup.long 0x120++0x03 line.long 0x00 "MID,Module ID Register" if (((per.l(ad:0xB0101000))&0x02)==0x02) hgroup.long 0x124++0x03 hide.long 0x00 "CSPREFETCHADDR,Command Sequencer Prefetch Address Register" in else hgroup.long 0x124++0x03 hide.long 0x00 "CSPREFETCHADDR,Command Sequencer Prefetch Address Register" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") if (((per.l(ad:0xB0101000+0x120)))==(0x00000100||0x00000300)) group.byte 0x128++0x00 line.byte 0x00 "SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x129++0x00 line.byte 0x00 "SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12A++0x00 line.byte 0x00 "SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12B++0x00 line.byte 0x00 "SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12C++0x00 line.byte 0x00 "SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12D++0x00 line.byte 0x00 "SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12E++0x00 line.byte 0x00 "SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12F++0x00 line.byte 0x00 "SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x130++0x00 line.byte 0x00 "SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x131++0x00 line.byte 0x00 "SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x132++0x00 line.byte 0x00 "SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x133++0x00 line.byte 0x00 "SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x134++0x00 line.byte 0x00 "SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x135++0x00 line.byte 0x00 "SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x136++0x00 line.byte 0x00 "SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x137++0x00 line.byte 0x00 "SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x138++0x00 line.byte 0x00 "SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x139++0x00 line.byte 0x00 "SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13A++0x00 line.byte 0x00 "SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13B++0x00 line.byte 0x00 "SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13C++0x00 line.byte 0x00 "SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13D++0x00 line.byte 0x00 "SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13E++0x00 line.byte 0x00 "SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13F++0x00 line.byte 0x00 "SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" else hgroup.byte 0x128++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0" hgroup.byte 0x129++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1" hgroup.byte 0x12A++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2" hgroup.byte 0x12B++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3" hgroup.byte 0x12C++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4" hgroup.byte 0x12D++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5" hgroup.byte 0x12E++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6" hgroup.byte 0x12F++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7" hgroup.byte 0x130++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0" hgroup.byte 0x131++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1" hgroup.byte 0x132++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2" hgroup.byte 0x133++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3" hgroup.byte 0x134++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4" hgroup.byte 0x135++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5" hgroup.byte 0x136++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6" hgroup.byte 0x137++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7" hgroup.byte 0x138++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0" hgroup.byte 0x139++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1" hgroup.byte 0x13A++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2" hgroup.byte 0x13B++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3" hgroup.byte 0x13C++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4" hgroup.byte 0x13D++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5" hgroup.byte 0x13E++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6" hgroup.byte 0x13F++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7" endif if (((per.l(ad:0xB0101000+0x120)))==(0x00000100||0x00000300)) group.long 0x144++0x03 line.long 0x00 "DLP,Data Learning Pattern Register" hexmask.long.byte 0x00 0.--7. 1. " DLP ,Data learning pattern" else hgroup.long 0x144++0x03 hide.long 0x00 "DLP,Data Learning Pattern Register" endif if (((per.l(ad:0xB0101000+0x120)))==(0x00000100||0x00000300)) rgroup.long 0x148++0x07 line.long 0x00 "DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register" bitfld.long 0x00 30. " DLPSMPLST7R ,Sampled data on the SDATA[7] port" "Match,Miss" bitfld.long 0x00 29. " DLPSMPLST7C ,Sampled data on the SDATA[7] port" "Match,Miss" bitfld.long 0x00 28. " DLPSMPLST7L ,Sampled data on the SDATA[7] port" "Match,Miss" newline bitfld.long 0x00 26. " DLPSMPLST6R ,Sampled data on the SDATA[6] port" "Match,Miss" bitfld.long 0x00 25. " DLPSMPLST6C ,Sampled data on the SDATA[6] port" "Match,Miss" bitfld.long 0x00 24. " DLPSMPLST6L ,Sampled data on the SDATA[6] port" "Match,Miss" newline bitfld.long 0x00 22. " DLPSMPLST5R ,Sampled data on the SDATA[5] port" "Match,Miss" bitfld.long 0x00 21. " DLPSMPLST5C ,Sampled data on the SDATA[5] port" "Match,Miss" bitfld.long 0x00 20. " DLPSMPLST5L ,Sampled data on the SDATA[5] port" "Match,Miss" newline bitfld.long 0x00 18. " DLPSMPLST4R ,Sampled data on the SDATA[4] port" "Match,Miss" bitfld.long 0x00 17. " DLPSMPLST4C ,Sampled data on the SDATA[4] port" "Match,Miss" bitfld.long 0x00 16. " DLPSMPLST4L ,Sampled data on the SDATA[4] port" "Match,Miss" newline bitfld.long 0x00 14. " DLPSMPLST3R ,Sampled data on the SDATA[3] port" "Match,Miss" bitfld.long 0x00 13. " DLPSMPLST3C ,Sampled data on the SDATA[3] port" "Match,Miss" bitfld.long 0x00 12. " DLPSMPLST3L ,Sampled data on the SDATA[3] port" "Match,Miss" newline bitfld.long 0x00 10. " DLPSMPLST2R ,Sampled data on the SDATA[2] port" "Match,Miss" bitfld.long 0x00 9. " DLPSMPLST2C ,Sampled data on the SDATA[2] port" "Match,Miss" bitfld.long 0x00 8. " DLPSMPLST2L ,Sampled data on the SDATA[2] port" "Match,Miss" newline bitfld.long 0x00 6. " DLPSMPLST1R ,Sampled data on the SDATA[1] port" "Match,Miss" bitfld.long 0x00 5. " DLPSMPLST1C ,Sampled data on the SDATA[1] port" "Match,Miss" bitfld.long 0x00 4. " DLPSMPLST1L ,Sampled data on the SDATA[1] port" "Match,Miss" newline bitfld.long 0x00 2. " DLPSMPLST0R ,Sampled data on the SDATA[0] port" "Match,Miss" bitfld.long 0x00 1. " DLPSMPLST0C ,Sampled data on the SDATA[0] port" "Match,Miss" bitfld.long 0x00 0. " DLPSMPLST0L ,Sampled data on the SDATA[0] port" "Match,Miss" line.long 0x04 "CSCFG,Command Sequencer Configuration Register" bitfld.long 0x04 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled" bitfld.long 0x04 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled" bitfld.long 0x04 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled" bitfld.long 0x04 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " DDRMODE ,DDR mode" "SDR,DDR" bitfld.long 0x04 1.--2. " MBM ,Multi bit mode" ",,Quad protocol,Dual Quad protocol" else hgroup.long 0x148++0x03 hide.long 0x00 "DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register" group.long 0x14C++0x03 line.long 0x00 "CSCFG,Command Sequencer Configuration Register" bitfld.long 0x00 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DDRMODE ,DDR mode" "SDR,DDR" bitfld.long 0x00 1.--2. " MBM ,Multi bit mode" ",,Quad protocol," endif elif cpuis("S6J336*")||cpuis("S6J337*") group.byte 0x128++0x00 line.byte 0x00 "SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x129++0x00 line.byte 0x00 "SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12A++0x00 line.byte 0x00 "SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12B++0x00 line.byte 0x00 "SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12C++0x00 line.byte 0x00 "SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12D++0x00 line.byte 0x00 "SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12E++0x00 line.byte 0x00 "SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x12F++0x00 line.byte 0x00 "SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7" hexmask.byte 0x00 0.--6. 1. " SDATASMPTCNT ,SDATA center clock sample point control" group.byte 0x130++0x00 line.byte 0x00 "SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x131++0x00 line.byte 0x00 "SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x132++0x00 line.byte 0x00 "SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x133++0x00 line.byte 0x00 "SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x134++0x00 line.byte 0x00 "SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x135++0x00 line.byte 0x00 "SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x136++0x00 line.byte 0x00 "SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x137++0x00 line.byte 0x00 "SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7" hexmask.byte 0x00 0.--6. 1. " SDATASMPTLFT ,SDATA left clock sample point control" group.byte 0x138++0x00 line.byte 0x00 "SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x139++0x00 line.byte 0x00 "SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13A++0x00 line.byte 0x00 "SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13B++0x00 line.byte 0x00 "SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13C++0x00 line.byte 0x00 "SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13D++0x00 line.byte 0x00 "SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13E++0x00 line.byte 0x00 "SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" group.byte 0x13F++0x00 line.byte 0x00 "SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7" hexmask.byte 0x00 0.--6. 1. " SDATASMPTRGH ,SDATA right clock sample point control" if (((per.l(ad:0xB0101000))&0x02)==0x02) group.long 0x144++0x03 line.long 0x00 "DLP,Data Learning Pattern Register" hexmask.long.byte 0x00 0.--7. 1. " DLP ,Data learning pattern" else hgroup.long 0x144++0x03 hide.long 0x00 "DLP,Data Learning Pattern Register" endif rgroup.long 0x148++0x07 line.long 0x00 "DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register" bitfld.long 0x00 30. " DLPSMPLST7R ,Sampled data on the SDATA[7] port" "Match,Miss" bitfld.long 0x00 29. " DLPSMPLST7C ,Sampled data on the SDATA[7] port" "Match,Miss" bitfld.long 0x00 28. " DLPSMPLST7L ,Sampled data on the SDATA[7] port" "Match,Miss" newline bitfld.long 0x00 26. " DLPSMPLST6R ,Sampled data on the SDATA[6] port" "Match,Miss" bitfld.long 0x00 25. " DLPSMPLST6C ,Sampled data on the SDATA[6] port" "Match,Miss" bitfld.long 0x00 24. " DLPSMPLST6L ,Sampled data on the SDATA[6] port" "Match,Miss" newline bitfld.long 0x00 22. " DLPSMPLST5R ,Sampled data on the SDATA[5] port" "Match,Miss" bitfld.long 0x00 21. " DLPSMPLST5C ,Sampled data on the SDATA[5] port" "Match,Miss" bitfld.long 0x00 20. " DLPSMPLST5L ,Sampled data on the SDATA[5] port" "Match,Miss" newline bitfld.long 0x00 18. " DLPSMPLST4R ,Sampled data on the SDATA[4] port" "Match,Miss" bitfld.long 0x00 17. " DLPSMPLST4C ,Sampled data on the SDATA[4] port" "Match,Miss" bitfld.long 0x00 16. " DLPSMPLST4L ,Sampled data on the SDATA[4] port" "Match,Miss" newline bitfld.long 0x00 14. " DLPSMPLST3R ,Sampled data on the SDATA[3] port" "Match,Miss" bitfld.long 0x00 13. " DLPSMPLST3C ,Sampled data on the SDATA[3] port" "Match,Miss" bitfld.long 0x00 12. " DLPSMPLST3L ,Sampled data on the SDATA[3] port" "Match,Miss" newline bitfld.long 0x00 10. " DLPSMPLST2R ,Sampled data on the SDATA[2] port" "Match,Miss" bitfld.long 0x00 9. " DLPSMPLST2C ,Sampled data on the SDATA[2] port" "Match,Miss" bitfld.long 0x00 8. " DLPSMPLST2L ,Sampled data on the SDATA[2] port" "Match,Miss" newline bitfld.long 0x00 6. " DLPSMPLST1R ,Sampled data on the SDATA[1] port" "Match,Miss" bitfld.long 0x00 5. " DLPSMPLST1C ,Sampled data on the SDATA[1] port" "Match,Miss" bitfld.long 0x00 4. " DLPSMPLST1L ,Sampled data on the SDATA[1] port" "Match,Miss" newline bitfld.long 0x00 2. " DLPSMPLST0R ,Sampled data on the SDATA[0] port" "Match,Miss" bitfld.long 0x00 1. " DLPSMPLST0C ,Sampled data on the SDATA[0] port" "Match,Miss" bitfld.long 0x00 0. " DLPSMPLST0L ,Sampled data on the SDATA[0] port" "Match,Miss" line.long 0x04 "CSCFG,Command Sequencer Configuration Register" bitfld.long 0x04 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled" bitfld.long 0x04 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled" bitfld.long 0x04 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled" bitfld.long 0x04 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " DDRMODE ,DDR mode" "SDR,DDR" bitfld.long 0x04 1.--2. " MBM ,Multi bit mode" ",,Quad protocol,Dual Quad protocol" else if (((per.l(ad:0xB0101000+0x120))&0x00000100)==0x00000100) group.byte 0x128++0x00 line.byte 0x00 "SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x129++0x00 line.byte 0x00 "SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x12A++0x00 line.byte 0x00 "SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x12B++0x00 line.byte 0x00 "SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x12C++0x00 line.byte 0x00 "SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x12D++0x00 line.byte 0x00 "SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x12E++0x00 line.byte 0x00 "SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x12F++0x00 line.byte 0x00 "SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7" bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x130++0x00 line.byte 0x00 "SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x131++0x00 line.byte 0x00 "SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x132++0x00 line.byte 0x00 "SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x133++0x00 line.byte 0x00 "SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x134++0x00 line.byte 0x00 "SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x135++0x00 line.byte 0x00 "SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x136++0x00 line.byte 0x00 "SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x137++0x00 line.byte 0x00 "SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7" bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x138++0x00 line.byte 0x00 "SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x139++0x00 line.byte 0x00 "SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x13A++0x00 line.byte 0x00 "SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x13B++0x00 line.byte 0x00 "SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x13C++0x00 line.byte 0x00 "SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x13D++0x00 line.byte 0x00 "SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x13E++0x00 line.byte 0x00 "SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x13F++0x00 line.byte 0x00 "SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7" bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x144++0x03 line.long 0x00 "DLP,Data Learning Pattern Register" hexmask.long.byte 0x00 0.--7. 1. " DLP ,Data learning pattern" rgroup.long 0x148++0x03 line.long 0x00 "DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register" bitfld.long 0x00 30. " DLPSMPLST7R ,Sampled data on the SDATA[7] port" "0,1" bitfld.long 0x00 29. " DLPSMPLST7C ,Sampled data on the SDATA[7] port" "0,1" bitfld.long 0x00 28. " DLPSMPLST7L ,Sampled data on the SDATA[7] port" "0,1" newline bitfld.long 0x00 26. " DLPSMPLST6R ,Sampled data on the SDATA[6] port" "0,1" bitfld.long 0x00 25. " DLPSMPLST6C ,Sampled data on the SDATA[6] port" "0,1" bitfld.long 0x00 24. " DLPSMPLST6L ,Sampled data on the SDATA[6] port" "0,1" newline bitfld.long 0x00 22. " DLPSMPLST5R ,Sampled data on the SDATA[5] port" "0,1" bitfld.long 0x00 21. " DLPSMPLST5C ,Sampled data on the SDATA[5] port" "0,1" bitfld.long 0x00 20. " DLPSMPLST5L ,Sampled data on the SDATA[5] port" "0,1" newline bitfld.long 0x00 18. " DLPSMPLST4R ,Sampled data on the SDATA[4] port" "0,1" bitfld.long 0x00 17. " DLPSMPLST4C ,Sampled data on the SDATA[4] port" "0,1" bitfld.long 0x00 16. " DLPSMPLST4L ,Sampled data on the SDATA[4] port" "0,1" newline bitfld.long 0x00 14. " DLPSMPLST3R ,Sampled data on the SDATA[3] port" "0,1" bitfld.long 0x00 13. " DLPSMPLST3C ,Sampled data on the SDATA[3] port" "0,1" bitfld.long 0x00 12. " DLPSMPLST3L ,Sampled data on the SDATA[3] port" "0,1" newline bitfld.long 0x00 10. " DLPSMPLST2R ,Sampled data on the SDATA[2] port" "0,1" bitfld.long 0x00 9. " DLPSMPLST2C ,Sampled data on the SDATA[2] port" "0,1" bitfld.long 0x00 8. " DLPSMPLST2L ,Sampled data on the SDATA[2] port" "0,1" newline bitfld.long 0x00 6. " DLPSMPLST1R ,Sampled data on the SDATA[1] port" "0,1" bitfld.long 0x00 5. " DLPSMPLST1C ,Sampled data on the SDATA[1] port" "0,1" bitfld.long 0x00 4. " DLPSMPLST1L ,Sampled data on the SDATA[1] port" "0,1" newline bitfld.long 0x00 2. " DLPSMPLST0R ,Sampled data on the SDATA[0] port" "0,1" bitfld.long 0x00 1. " DLPSMPLST0C ,Sampled data on the SDATA[0] port" "0,1" bitfld.long 0x00 0. " DLPSMPLST0L ,Sampled data on the SDATA[0] port" "0,1" group.long 0x14C++0x03 line.long 0x00 "CSCFG,Command Sequencer Configuration Register" bitfld.long 0x00 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DDRMODE ,DDR mode" "SDR,DDR" bitfld.long 0x00 1.--2. " MBM ,Multi bit mode" ",,Quad protocol,Dual Quad protocol" else hgroup.byte 0x128++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0" hgroup.byte 0x129++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1" hgroup.byte 0x12A++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2" hgroup.byte 0x12B++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3" hgroup.byte 0x12C++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4" hgroup.byte 0x12D++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5" hgroup.byte 0x12E++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6" hgroup.byte 0x12F++0x00 hide.byte 0x00 "SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7" hgroup.byte 0x130++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0" hgroup.byte 0x131++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1" hgroup.byte 0x132++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2" hgroup.byte 0x133++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3" hgroup.byte 0x134++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4" hgroup.byte 0x135++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5" hgroup.byte 0x136++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6" hgroup.byte 0x137++0x00 hide.byte 0x00 "SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7" hgroup.byte 0x138++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0" hgroup.byte 0x139++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1" hgroup.byte 0x13A++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2" hgroup.byte 0x13B++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3" hgroup.byte 0x13C++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4" hgroup.byte 0x13D++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5" hgroup.byte 0x13E++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6" hgroup.byte 0x13F++0x00 hide.byte 0x00 "SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7" hgroup.long 0x144++0x03 hide.long 0x00 "DLP,Data Learning Pattern Register" hgroup.long 0x148++0x03 hide.long 0x00 "DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register" group.long 0x14C++0x03 line.long 0x00 "CSCFG,Command Sequencer Configuration Register" bitfld.long 0x00 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DDRMODE ,DDR mode" "SDR,DDR" bitfld.long 0x00 1.--2. " MBM ,Multi bit mode" ",,Quad protocol," endif endif if (((per.l(ad:0xB0101000+0x00))&0x02)==0x02) group.long 0x150++0x03 line.long 0x00 "CSITIME,Command Sequencer Idle Time Register" hexmask.long.word 0x00 0.--15. 1. " ITIME ,Idle time" else hgroup.long 0x150++0x03 hide.long 0x00 "CSITIME,Command Sequencer Idle Time Register" endif sif cpuis("S6J336*")||cpuis("S6J337*") if (((per.l(ad:0xB0101000+0x00))&0x02)==0x02) group.long 0x154++0x03 line.long 0x00 "CSAEXT,Command Sequencer Address Extension Register" hexmask.long.tbyte 0x00 13.--31. 0x20 " AEXT ,Address extension bits" else hgroup.long 0x154++0x03 hide.long 0x00 "CSAEXT,Command Sequencer Address Extension Register" endif else group.long 0x154++0x03 line.long 0x00 "CSAEXT,Command Sequencer Address Extension Register" hexmask.long.tbyte 0x00 13.--31. 1. " AEXT ,Address extension bits" endif sif cpuis("S6J336*")||cpuis("S6J337*") group.long 0x158++0x03 line.long 0x00 "CSPBUFFERCFG,Command Sequencer Prefetch Buffer Configuration Register" bitfld.long 0x00 19. " PBFLSH ,Prefetch buffer flush" "No effect,Flush" else wgroup.long 0x158++0x03 line.long 0x00 "CSPBUFFERCFG,Command Sequencer Prefetch Buffer Configuration Register" bitfld.long 0x00 19. " PBFLSH ,Prefetch buffer flush" "No effect,Flush" endif if (((per.l(ad:0xB0101000+0x00))&0x02)==0x02) rgroup.long 0x15C++0x03 line.long 0x00 "CSPBUFFERSTATUS,Command Sequencer Prefetch Buffer Status Register" bitfld.long 0x00 16. " SSACTIVE ,Slave select active" "Inactive,Active" bitfld.long 0x00 0.--5. " PBLEVEL ,Current fill level of prefetch buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long 0x15C++0x03 hide.long 0x00 "CSPBUFFERSTATUS,Command Sequencer Prefetch Buffer Status Register" endif width 0x0B tree.end tree "EBI (External Bus Interface)" base ad:0xB0100000 width 10. wgroup.long 0x00++0x03 line.long 0x00 "UNLOCK,Unlock Register" rgroup.long 0x04++0x03 line.long 0x00 "LSTSR,Lock Status Register" bitfld.long 0x00 0. " LOCKSTATUS ,Lock status" "Unlocked,Locked" group.long 0x8++0x03 line.long 0x00 "SFMR0,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0xC++0x03 line.long 0x00 "SFMR1,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0x10++0x03 line.long 0x00 "SFMR2,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0x14++0x03 line.long 0x00 "SFMR3,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0x18++0x03 line.long 0x00 "SFMR4,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0x1C++0x03 line.long 0x00 "SFMR5,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0x20++0x03 line.long 0x00 "SFMR6,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." group.long 0x24++0x03 line.long 0x00 "SFMR7,SRAM/FLASH Mode Control Register" bitfld.long 0x00 7. " ENDIANESS ,Endianess control" "Little endian,Big endian" bitfld.long 0x00 6. " RDY ,Ready mode" "Disabled,Enabled" bitfld.long 0x00 5. " PAGE ,NOR FLASH page access mode" "Disabled,Enabled" bitfld.long 0x00 4. " NAND ,NAND FLASH mode" "Disabled,Enabled" bitfld.long 0x00 3. " WEOFF ,Write enable signal (MWEX) operation disable" "No,Yes" bitfld.long 0x00 2. " RBMON ,Byte mask signal (MDQM) at read access enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " WDTH ,Data bit width of a connected device" "8-bit,16-bit,32-bit,?..." newline group.long 0x28++0x03 line.long 0x00 "SFACCR0,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x2C++0x03 line.long 0x00 "SFACCR1,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x30++0x03 line.long 0x00 "SFACCR2,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x34++0x03 line.long 0x00 "SFACCR3,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x38++0x03 line.long 0x00 "SFACCR4,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x3C++0x03 line.long 0x00 "SFACCR5,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x40++0x03 line.long 0x00 "SFACCR6,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x44++0x03 line.long 0x00 "SFACCR7,SRAM/FLASH Access Configuration Register" bitfld.long 0x00 28.--31. " WIDLC ,Number of idle cycles after write access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Number of cycles for write enable assertion" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Number of setup cycles of the write address" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Number of cycles necessary for write access" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 12.--15. " RIDLC ,Number of idle cycles after the read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,Initial latency of the address in the read access of the NOR FLASH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Number of setup cycles of the read address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 0.--3. " RACC ,Number of necessary cycles for read access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x48++0x03 line.long 0x00 "SFADDCR0,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x4C++0x03 line.long 0x00 "SFADDCR1,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x50++0x03 line.long 0x00 "SFADDCR2,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x54++0x03 line.long 0x00 "SFADDCR3,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x58++0x03 line.long 0x00 "SFADDCR4,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x5C++0x03 line.long 0x00 "SFADDCR5,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x60++0x03 line.long 0x00 "SFADDCR6,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x64++0x03 line.long 0x00 "SFADDCR7,SRAM/FLASH Address Control Register" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" group.long 0x7C++0x03 line.long 0x00 "ERRR,Error Register" eventfld.long 0x00 0. " SFER ,SRAM/FLASH error flag" "No error,Error" width 0x0B tree.end tree "SRAM_IF (System SRAM Module)" base ad:0xB0108000 width 8. if (((per.l(ad:0xB0108000+0x18))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CFG0,SRAM_IF Configuration Register 0" bitfld.long 0x00 24.--25. " RDWAIT ,Read data wait state value" "0,1,2,3" bitfld.long 0x00 16.--17. " WRWAIT ,Write data wait state value" "0,1,2,3" rbitfld.long 0x00 8. " LOCK_STATUS ,SRAM_IF lock status" "Unlocked,Locked" hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC ERRBIT value" sif cpuis("S6J34*")||cpuis("S6J35*") group.long 0x04++0x03 line.long 0x00 "CFG1,SRAM_IF Configuration Register 1" bitfld.long 0x00 31. " ERRBIT[31] ,Emulated bit-flip 31 value" "Not flipped,Flipped" bitfld.long 0x00 30. " [30] ,Emulated bit-flip 30 value" "Not flipped,Flipped" bitfld.long 0x00 29. " [29] ,Emulated bit-flip 29 value" "Not flipped,Flipped" bitfld.long 0x00 28. " [28] ,Emulated bit-flip 28 value" "Not flipped,Flipped" newline bitfld.long 0x00 27. " [27] ,Emulated bit-flip 27 value" "Not flipped,Flipped" bitfld.long 0x00 26. " [26] ,Emulated bit-flip 26 value" "Not flipped,Flipped" bitfld.long 0x00 25. " [25] ,Emulated bit-flip 25 value" "Not flipped,Flipped" bitfld.long 0x00 24. " [24] ,Emulated bit-flip 24 value" "Not flipped,Flipped" newline bitfld.long 0x00 23. " [23] ,Emulated bit-flip 23 value" "Not flipped,Flipped" bitfld.long 0x00 22. " [22] ,Emulated bit-flip 22 value" "Not flipped,Flipped" bitfld.long 0x00 21. " [21] ,Emulated bit-flip 21 value" "Not flipped,Flipped" bitfld.long 0x00 20. " [20] ,Emulated bit-flip 20 value" "Not flipped,Flipped" newline bitfld.long 0x00 19. " [19] ,Emulated bit-flip 19 value" "Not flipped,Flipped" bitfld.long 0x00 18. " [18] ,Emulated bit-flip 18 value" "Not flipped,Flipped" bitfld.long 0x00 17. " [17] ,Emulated bit-flip 17 value" "Not flipped,Flipped" bitfld.long 0x00 16. " [16] ,Emulated bit-flip 16 value" "Not flipped,Flipped" newline bitfld.long 0x00 15. " [15] ,Emulated bit-flip 15 value" "Not flipped,Flipped" bitfld.long 0x00 14. " [14] ,Emulated bit-flip 14 value" "Not flipped,Flipped" bitfld.long 0x00 13. " [13] ,Emulated bit-flip 13 value" "Not flipped,Flipped" bitfld.long 0x00 12. " [12] ,Emulated bit-flip 12 value" "Not flipped,Flipped" newline bitfld.long 0x00 11. " [11] ,Emulated bit-flip 11 value" "Not flipped,Flipped" bitfld.long 0x00 10. " [10] ,Emulated bit-flip 10 value" "Not flipped,Flipped" bitfld.long 0x00 9. " [9] ,Emulated bit-flip 9 value" "Not flipped,Flipped" bitfld.long 0x00 8. " [8] ,Emulated bit-flip 8 value" "Not flipped,Flipped" newline bitfld.long 0x00 7. " [7] ,Emulated bit-flip 7 value" "Not flipped,Flipped" bitfld.long 0x00 6. " [6] ,Emulated bit-flip 6 value" "Not flipped,Flipped" bitfld.long 0x00 5. " [5] ,Emulated bit-flip 5 value" "Not flipped,Flipped" bitfld.long 0x00 4. " [4] ,Emulated bit-flip 4 value" "Not flipped,Flipped" newline bitfld.long 0x00 3. " [3] ,Emulated bit-flip 3 value" "Not flipped,Flipped" bitfld.long 0x00 2. " [2] ,Emulated bit-flip 2 value" "Not flipped,Flipped" bitfld.long 0x00 1. " [1] ,Emulated bit-flip 1 value" "Not flipped,Flipped" bitfld.long 0x00 0. " [0] ,Emulated bit-flip 0 value" "Not flipped,Flipped" else group.long 0x04++0x03 line.long 0x00 "CFG1,SRAM_IF Configuration Register 1" endif else group.long 0x00++0x03 line.long 0x00 "CFG0,SRAM_IF Configuration Register 0" bitfld.long 0x00 24.--25. " RDWAIT ,Read data wait state value" "0,1,2,3" bitfld.long 0x00 16.--17. " WRWAIT ,Write data wait state value" "0,1,2,3" rbitfld.long 0x00 8. " LOCK_STATUS ,SRAM_IF lock status" "Unlocked,Locked" hgroup.long 0x04++0x03 hide.long 0x00 "CFG1,SRAM_IF Configuration Register 1" endif group.long 0x08++0x13 line.long 0x00 "CFG2,SRAM_IF Configuration Register 2" bitfld.long 0x00 0. " BYPASSEN ,RDB bypass disable or enable" "Disabled,Enabled" line.long 0x04 "KEY,SRAM_IF Unlock/Lock Key Register" line.long 0x08 "ERRFLG,SRAM_IF Error Flag Register" bitfld.long 0x08 8. " SECCLR ,Single-bit error flag clear" "Not effect,Clear" rbitfld.long 0x08 0. " SECFLG ,Single-bit error detection flag" "No error,Error" line.long 0x0C "INTE,SRAM_IF Interrupt Enable Register" bitfld.long 0x0C 0. " SEC_INT_EN ,Single-bit error interrupt enable bit" "No interrupt,Interrupt" line.long 0x10 "ECCE,SRAM_IF ECC Enable Register" bitfld.long 0x10 0. " ECCEN ,ECCEN value" "Disabled,Enabled" rgroup.long 0x20++0x07 line.long 0x00 "ERRADR,SRAM_IF Error Address Register" line.long 0x04 "MID,SRAM_IF Module Identification Register" width 0x0B tree.end sif (cpuis("S6J335*")) tree "ADC12B (12/10/8-BIT ANALOG TO DIGITAL CONVERTER)" tree "ADC12B0" base ad:0xB48C0000 width 10. tree "CHCTRL 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x0++0x3 line.long 0x00 "CHCTRL0,A/D Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x4++0x3 line.long 0x00 "CHCTRL1,A/D Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x8++0x3 line.long 0x00 "CHCTRL2,A/D Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0xC++0x3 line.long 0x00 "CHCTRL3,A/D Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x10++0x3 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x10++0x3 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x14++0x3 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x14++0x3 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x18++0x3 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x18++0x3 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x1C++0x3 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x1C++0x3 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x28++0x3 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x28++0x3 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x2C++0x3 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x2C++0x3 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x38++0x3 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x38++0x3 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x3C++0x3 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x3C++0x3 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x4C++0x3 line.long 0x00 "CHCTRL19,A/D Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x50++0x3 line.long 0x00 "CHCTRL20,A/D Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x58++0x3 line.long 0x00 "CHCTRL22,A/D Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x5C++0x3 line.long 0x00 "CHCTRL23,A/D Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x64++0x3 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x64++0x3 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x68++0x3 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x68++0x3 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x6C++0x3 line.long 0x00 "CHCTRL27,A/D Channel Control Register 27" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x70++0x3 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x70++0x3 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x74++0x3 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x74++0x3 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x78++0x3 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x78++0x3 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x84++0x3 line.long 0x00 "CHCTRL33,A/D Channel Control Register 33" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x88++0x3 line.long 0x00 "CHCTRL34,A/D Channel Control Register 34" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x8C++0x3 line.long 0x00 "CHCTRL35,A/D Channel Control Register 35" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x90++0x3 line.long 0x00 "CHCTRL36,A/D Channel Control Register 36" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x94++0x3 line.long 0x00 "CHCTRL37,A/D Channel Control Register 37" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x98++0x3 line.long 0x00 "CHCTRL38,A/D Channel Control Register 38" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0xC0++0x3 line.long 0x00 "CHCTRL48,A/D Channel Control Register 48" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif tree.end tree "CHSTAT 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x100++0x1 line.word 0x00 "CHSTAT0,A/D Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x102++0x1 line.word 0x00 "CHSTAT1,A/D Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x104++0x1 line.word 0x00 "CHSTAT2,A/D Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x106++0x1 line.word 0x00 "CHSTAT3,A/D Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x108++0x1 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x108++0x1 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x10A++0x1 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x10A++0x1 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x10C++0x1 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x10C++0x1 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x10E++0x1 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x10E++0x1 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x114++0x1 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x114++0x1 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x116++0x1 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x116++0x1 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x11C++0x1 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11C++0x1 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x11E++0x1 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11E++0x1 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x126++0x1 line.word 0x00 "CHSTAT19,A/D Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x128++0x1 line.word 0x00 "CHSTAT20,A/D Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x12C++0x1 line.word 0x00 "CHSTAT22,A/D Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x12E++0x1 line.word 0x00 "CHSTAT23,A/D Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x132++0x1 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x132++0x1 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x134++0x1 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x134++0x1 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x136++0x1 line.word 0x00 "CHSTAT27,A/D Channel Status Register 27" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x138++0x1 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x138++0x1 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x13A++0x1 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13A++0x1 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x13C++0x1 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13C++0x1 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x142++0x1 line.word 0x00 "CHSTAT33,A/D Channel Status Register 33" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x144++0x1 line.word 0x00 "CHSTAT34,A/D Channel Status Register 34" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x146++0x1 line.word 0x00 "CHSTAT35,A/D Channel Status Register 35" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x148++0x1 line.word 0x00 "CHSTAT36,A/D Channel Status Register 36" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x14A++0x1 line.word 0x00 "CHSTAT37,A/D Channel Status Register 37" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x14C++0x1 line.word 0x00 "CHSTAT38,A/D Channel Status Register 38" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x160++0x1 line.word 0x00 "CHSTAT48,A/D Channel Status Register 48" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif tree.end width 6. tree "CD 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x180++0x1 line.word 0x00 "CD0,A/D Conversion Data Register 0" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x182++0x1 line.word 0x00 "CD1,A/D Conversion Data Register 1" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x184++0x1 line.word 0x00 "CD2,A/D Conversion Data Register 2" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x186++0x1 line.word 0x00 "CD3,A/D Conversion Data Register 3" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x188++0x1 line.word 0x00 "CD4,A/D Conversion Data Register 4" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x188++0x1 line.word 0x00 "CD4,A/D Conversion Data Register 4" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x18A++0x1 line.word 0x00 "CD5,A/D Conversion Data Register 5" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x18A++0x1 line.word 0x00 "CD5,A/D Conversion Data Register 5" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x18C++0x1 line.word 0x00 "CD6,A/D Conversion Data Register 6" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x18C++0x1 line.word 0x00 "CD6,A/D Conversion Data Register 6" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x18E++0x1 line.word 0x00 "CD7,A/D Conversion Data Register 7" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x18E++0x1 line.word 0x00 "CD7,A/D Conversion Data Register 7" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x194++0x1 line.word 0x00 "CD10,A/D Conversion Data Register 10" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x194++0x1 line.word 0x00 "CD10,A/D Conversion Data Register 10" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x196++0x1 line.word 0x00 "CD11,A/D Conversion Data Register 11" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x196++0x1 line.word 0x00 "CD11,A/D Conversion Data Register 11" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x19C++0x1 line.word 0x00 "CD14,A/D Conversion Data Register 14" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19C++0x1 line.word 0x00 "CD14,A/D Conversion Data Register 14" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x19E++0x1 line.word 0x00 "CD15,A/D Conversion Data Register 15" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19E++0x1 line.word 0x00 "CD15,A/D Conversion Data Register 15" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1A6++0x1 line.word 0x00 "CD19,A/D Conversion Data Register 19" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1A8++0x1 line.word 0x00 "CD20,A/D Conversion Data Register 20" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1AC++0x1 line.word 0x00 "CD22,A/D Conversion Data Register 22" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1AE++0x1 line.word 0x00 "CD23,A/D Conversion Data Register 23" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1B2++0x1 line.word 0x00 "CD25,A/D Conversion Data Register 25" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B2++0x1 line.word 0x00 "CD25,A/D Conversion Data Register 25" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1B4++0x1 line.word 0x00 "CD26,A/D Conversion Data Register 26" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B4++0x1 line.word 0x00 "CD26,A/D Conversion Data Register 26" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1B6++0x1 line.word 0x00 "CD27,A/D Conversion Data Register 27" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1B8++0x1 line.word 0x00 "CD28,A/D Conversion Data Register 28" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B8++0x1 line.word 0x00 "CD28,A/D Conversion Data Register 28" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1BA++0x1 line.word 0x00 "CD29,A/D Conversion Data Register 29" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BA++0x1 line.word 0x00 "CD29,A/D Conversion Data Register 29" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1BC++0x1 line.word 0x00 "CD30,A/D Conversion Data Register 30" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BC++0x1 line.word 0x00 "CD30,A/D Conversion Data Register 30" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C2++0x1 line.word 0x00 "CD33,A/D Conversion Data Register 33" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C4++0x1 line.word 0x00 "CD34,A/D Conversion Data Register 34" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C6++0x1 line.word 0x00 "CD35,A/D Conversion Data Register 35" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C8++0x1 line.word 0x00 "CD36,A/D Conversion Data Register 36" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1CA++0x1 line.word 0x00 "CD37,A/D Conversion Data Register 37" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1CC++0x1 line.word 0x00 "CD38,A/D Conversion Data Register 38" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1E0++0x1 line.word 0x00 "CD48,A/D Conversion Data Register 48" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif tree.end width 10. tree "PCCTRL 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x200++0x3 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x204++0x3 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x208++0x3 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x20C++0x3 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x210++0x3 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x210++0x3 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x214++0x3 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x214++0x3 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x218++0x3 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x218++0x3 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x21C++0x3 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x21C++0x3 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x228++0x3 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x228++0x3 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x22C++0x3 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x22C++0x3 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x238++0x3 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x238++0x3 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x23C++0x3 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x23C++0x3 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x24C++0x3 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x250++0x3 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x258++0x3 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x25C++0x3 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x264++0x3 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x264++0x3 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x268++0x3 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x268++0x3 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x26C++0x3 line.long 0x00 "PCCTRL27,Pulse Counter Control Register 27" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x270++0x3 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x270++0x3 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x274++0x3 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x274++0x3 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x278++0x3 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x278++0x3 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x284++0x3 line.long 0x00 "PCCTRL33,Pulse Counter Control Register 33" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x288++0x3 line.long 0x00 "PCCTRL34,Pulse Counter Control Register 34" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x28C++0x3 line.long 0x00 "PCCTRL35,Pulse Counter Control Register 35" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x290++0x3 line.long 0x00 "PCCTRL36,Pulse Counter Control Register 36" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x294++0x3 line.long 0x00 "PCCTRL37,Pulse Counter Control Register 37" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x298++0x3 line.long 0x00 "PCCTRL38,Pulse Counter Control Register 38" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x2C0++0x3 line.long 0x00 "PCCTRL48,Pulse Counter Control Register 48" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif tree.end textline "" width 19. sif cpuis("S6J335?H?") group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif cpuis("S6J335?J?") group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag 28" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag 26" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag 7" "Not requested,Requested" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag 4" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger overrun clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger overrun clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger overrun clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger overrun clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger overrun clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger overrun clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger overrun clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger overrun clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger overrun clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger overrun clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger overrun clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger overrun clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger overrun clear bit 4" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" textline " " bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" textline " " bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" textline " " bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" textline " " bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Conversion done interrupt flag 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Conversion done interrupt flag 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Conversion done interrupt flag 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Conversion done interrupt flag 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Conversion done interrupt flag 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Conversion done interrupt flag 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Conversion done interrupt flag 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Conversion done interrupt flag 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Conversion done interrupt flag 0" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Conversion done interrupt flag 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Conversion done interrupt flag 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Conversion done interrupt flag 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Conversion done interrupt flag 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Conversion done interrupt flag 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Conversion done interrupt flag 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Conversion done interrupt flag 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Group interrupted interrupt 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Group interrupted interrupt 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Group interrupted interrupt 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Group interrupted interrupt 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Group interrupted interrupt 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Group interrupted interrupt 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Group interrupted interrupt 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Group interrupted interrupt 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Group interrupted interrupt 0" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Group interrupted interrupt 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Group interrupted interrupt 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Group interrupted interrupt 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Group interrupted interrupt 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Group interrupted interrupt 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Group interrupted interrupt 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Group interrupted interrupt 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Range comparator interrupt flag 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Range comparator interrupt flag 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Range comparator interrupt flag 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Range comparator interrupt flag 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Range comparator interrupt flag 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Range comparator interrupt flag 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Range comparator interrupt flag 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Range comparator interrupt flag 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Range comparator interrupt flag 0" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Range comparator interrupt flag 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Range comparator interrupt flag 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Range comparator interrupt flag 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Range comparator interrupt flag 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Range comparator interrupt flag 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Range comparator interrupt flag 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Range comparator interrupt flag 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Pulse counter interrupt bit 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Pulse counter interrupt bit 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Pulse counter interrupt bit 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Pulse counter interrupt bit 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Pulse counter interrupt bit 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Pulse counter interrupt bit 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Pulse counter interrupt bit 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Pulse counter interrupt bit 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Pulse counter interrupt bit 0" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Pulse counter interrupt bit 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Pulse counter interrupt bit 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Pulse counter interrupt bit 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Pulse counter interrupt bit 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Pulse counter interrupt bit 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Pulse counter interrupt bit 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Pulse counter interrupt bit 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag 28" "Not requested,Requested" bitfld.long 0x00 27. " [27] ,A/D channel trigger status flag 27" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag 26" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 23. " [23] ,A/D channel trigger status flag 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag 20" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag 19" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag 14" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag 7" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag 4" "Not requested,Requested" bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag 3" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag 2" "Not requested,Requested" textline " " bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag 1" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag 0" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 16. " [48] ,A/D channel trigger status flag 48" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 6. " [38] ,A/D channel trigger status flag 38" "Not requested,Requested" bitfld.long 0x00 5. " [37] ,A/D channel trigger status flag 37" "Not requested,Requested" bitfld.long 0x00 4. " [36] ,A/D channel trigger status flag 36" "Not requested,Requested" bitfld.long 0x00 3. " [35] ,A/D channel trigger status flag 35" "Not requested,Requested" bitfld.long 0x00 2. " [34] ,A/D channel trigger status flag 34" "Not requested,Requested" textline " " bitfld.long 0x00 1. " [33] ,A/D channel trigger status flag 33" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 27. " [27] ,Trigger status clear bit 27" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 23. " [23] ,Trigger status clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,Trigger status clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,Trigger status clear bit 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " [19] ,Trigger status clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" bitfld.long 0x00 3. " [3] ,Trigger status clear bit 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Trigger status clear bit 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " [1] ,Trigger status clear bit 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Trigger status clear bit 0" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 16. " [48] ,Trigger status clear bit 48" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 6. " [38] ,Trigger status clear bit 38" "No effect,Clear" bitfld.long 0x00 5. " [37] ,Trigger status clear bit 37" "No effect,Clear" bitfld.long 0x00 4. " [36] ,Trigger status clear bit 36" "No effect,Clear" bitfld.long 0x00 3. " [35] ,Trigger status clear bit 35" "No effect,Clear" bitfld.long 0x00 2. " [34] ,Trigger status clear bit 34" "No effect,Clear" textline " " bitfld.long 0x00 1. " [33] ,Trigger status clear bit 33" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun flag 27" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun flag 23" "Not occurred,Occurred" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 16. " [48] ,A/D channel trigger overrun flag 48" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 6. " [38] ,A/D channel trigger overrun flag 38" "Not occurred,Occurred" bitfld.long 0x00 5. " [37] ,A/D channel trigger overrun flag 37" "Not occurred,Occurred" bitfld.long 0x00 4. " [36] ,A/D channel trigger overrun flag 36" "Not occurred,Occurred" bitfld.long 0x00 3. " [35] ,A/D channel trigger overrun flag 35" "Not occurred,Occurred" bitfld.long 0x00 2. " [34] ,A/D channel trigger overrun flag 34" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " [33] ,A/D channel trigger overrun flag 33" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger overrun clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger overrun clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger overrun clear bit 28" "No effect,Clear" bitfld.long 0x00 27. " [27] ,Trigger overrun clear bit 27" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger overrun clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger overrun clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 23. " [23] ,Trigger overrun clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,Trigger overrun clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,Trigger overrun clear bit 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " [19] ,Trigger overrun clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger overrun clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger overrun clear bit 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" bitfld.long 0x00 11. " [11] ,Trigger overrun clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger overrun clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " [7] ,Trigger overrun clear bit 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Trigger overrun clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger overrun clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger overrun clear bit 4" "No effect,Clear" bitfld.long 0x00 3. " [3] ,Trigger overrun clear bit 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Trigger overrun clear bit 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " [1] ,Trigger overrun clear bit 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Trigger overrun clear bit 0" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 16. " [48] ,Trigger overrun clear bit 48" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 6. " [38] ,Trigger overrun clear bit 38" "No effect,Clear" bitfld.long 0x00 5. " [37] ,Trigger overrun clear bit 37" "No effect,Clear" bitfld.long 0x00 4. " [36] ,Trigger overrun clear bit 36" "No effect,Clear" bitfld.long 0x00 3. " [35] ,Trigger overrun clear bit 35" "No effect,Clear" bitfld.long 0x00 2. " [34] ,Trigger overrun clear bit 34" "No effect,Clear" textline " " bitfld.long 0x00 1. " [33] ,Trigger overrun clear bit 33" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 27. " [27] ,Range comparator over threshold flag 27" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 23. " [23] ,Range comparator over threshold flag 23" "Less or equal,Above" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less or equal,Above" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less or equal,Above" textline " " bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less or equal,Above" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 16. " [48] ,Range comparator over threshold flag 48" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 6. " [38] ,Range comparator over threshold flag 38" "Less or equal,Above" bitfld.long 0x00 5. " [37] ,Range comparator over threshold flag 37" "Less or equal,Above" bitfld.long 0x00 4. " [36] ,Range comparator over threshold flag 36" "Less or equal,Above" bitfld.long 0x00 3. " [35] ,Range comparator over threshold flag 35" "Less or equal,Above" bitfld.long 0x00 2. " [34] ,Range comparator over threshold flag 34" "Less or equal,Above" textline " " bitfld.long 0x00 1. " [33] ,Range comparator over threshold flag 33" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.word 0x390++0xF line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,A/D converter resumption time setting bits" line.word 0x04 "ST0,A/D converter sampling time setting register" line.word 0x06 "ST1,A/D converter sampling time setting register" line.word 0x08 "ST2,A/D converter sampling time setting register" line.word 0x0A "ST3,A/D converter sampling time setting register" line.word 0x0C "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x0C 0.--7. 1. " OCV ,Offset compensation value" line.word 0x0E "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x0E 0.--4. " GCV ,Gain Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0000+0x3A0)&0x10)==0x00) group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,10-bit,12-bit,8-bit" else group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 6. " FSTP ,Forced stop" "No effect,Forced" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,12-bit,10-bit,8-bit" endif sif cpuis("S6J335?H?") rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif cpuis("S6J335?J?") rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B0++0x00 hide.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3BA++0x00 hide.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3BC++0x00 hide.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3BE++0x00 hide.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B1++0x00 hide.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" else group.byte 0x3B1++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B3++0x00 hide.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" else group.byte 0x3B3++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B5++0x00 hide.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" else group.byte 0x3B5++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B7++0x00 hide.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" else group.byte 0x3B7++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F0++0x00 hide.byte 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F2++0x00 hide.byte 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F4++0x00 hide.byte 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F6++0x00 hide.byte 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F8++0x00 hide.byte 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FA++0x00 hide.byte 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FC++0x00 hide.byte 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FE++0x00 hide.byte 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D0++0x01 hide.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D2++0x01 hide.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D4++0x01 hide.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D6++0x01 hide.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D8++0x01 hide.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DA++0x01 hide.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DC++0x01 hide.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DE++0x01 hide.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" endif group.byte 0x3C0++0x0 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C1++0x0 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C2++0x0 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C3++0x0 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x0 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E1++0x0 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E2++0x0 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E3++0x0 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0xB tree.end tree "ADC12B1" base ad:0xB48C0400 width 10. tree "CHCTRL 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x0++0x3 line.long 0x00 "CHCTRL0,A/D Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x4++0x3 line.long 0x00 "CHCTRL1,A/D Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x8++0x3 line.long 0x00 "CHCTRL2,A/D Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0xC++0x3 line.long 0x00 "CHCTRL3,A/D Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x10++0x3 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x10++0x3 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x14++0x3 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x14++0x3 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x18++0x3 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x18++0x3 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x1C++0x3 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x1C++0x3 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x28++0x3 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x28++0x3 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x2C++0x3 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x2C++0x3 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x38++0x3 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x38++0x3 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x3C++0x3 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x3C++0x3 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x4C++0x3 line.long 0x00 "CHCTRL19,A/D Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x50++0x3 line.long 0x00 "CHCTRL20,A/D Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x58++0x3 line.long 0x00 "CHCTRL22,A/D Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x5C++0x3 line.long 0x00 "CHCTRL23,A/D Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x64++0x3 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x64++0x3 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x68++0x3 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x68++0x3 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x6C++0x3 line.long 0x00 "CHCTRL27,A/D Channel Control Register 27" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x70++0x3 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x70++0x3 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x74++0x3 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x74++0x3 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x78++0x3 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x78++0x3 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x84++0x3 line.long 0x00 "CHCTRL33,A/D Channel Control Register 33" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x88++0x3 line.long 0x00 "CHCTRL34,A/D Channel Control Register 34" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x8C++0x3 line.long 0x00 "CHCTRL35,A/D Channel Control Register 35" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x90++0x3 line.long 0x00 "CHCTRL36,A/D Channel Control Register 36" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x94++0x3 line.long 0x00 "CHCTRL37,A/D Channel Control Register 37" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x98++0x3 line.long 0x00 "CHCTRL38,A/D Channel Control Register 38" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0xC0++0x3 line.long 0x00 "CHCTRL48,A/D Channel Control Register 48" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif cpuis("S6J335?H?") group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" elif cpuis("S6J335?J?") group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,AN48,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif tree.end tree "CHSTAT 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x100++0x1 line.word 0x00 "CHSTAT0,A/D Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x102++0x1 line.word 0x00 "CHSTAT1,A/D Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x104++0x1 line.word 0x00 "CHSTAT2,A/D Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x106++0x1 line.word 0x00 "CHSTAT3,A/D Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x108++0x1 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x108++0x1 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x10A++0x1 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x10A++0x1 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x10C++0x1 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x10C++0x1 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x10E++0x1 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x10E++0x1 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x114++0x1 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x114++0x1 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x116++0x1 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x116++0x1 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x11C++0x1 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11C++0x1 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x11E++0x1 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11E++0x1 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x126++0x1 line.word 0x00 "CHSTAT19,A/D Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x128++0x1 line.word 0x00 "CHSTAT20,A/D Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x12C++0x1 line.word 0x00 "CHSTAT22,A/D Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x12E++0x1 line.word 0x00 "CHSTAT23,A/D Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x132++0x1 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x132++0x1 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x134++0x1 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x134++0x1 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x136++0x1 line.word 0x00 "CHSTAT27,A/D Channel Status Register 27" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x138++0x1 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x138++0x1 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x13A++0x1 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13A++0x1 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x13C++0x1 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13C++0x1 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x142++0x1 line.word 0x00 "CHSTAT33,A/D Channel Status Register 33" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x144++0x1 line.word 0x00 "CHSTAT34,A/D Channel Status Register 34" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x146++0x1 line.word 0x00 "CHSTAT35,A/D Channel Status Register 35" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x148++0x1 line.word 0x00 "CHSTAT36,A/D Channel Status Register 36" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x14A++0x1 line.word 0x00 "CHSTAT37,A/D Channel Status Register 37" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x14C++0x1 line.word 0x00 "CHSTAT38,A/D Channel Status Register 38" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x160++0x1 line.word 0x00 "CHSTAT48,A/D Channel Status Register 48" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif cpuis("S6J335?H?") rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" elif cpuis("S6J335?J?") rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif tree.end width 6. tree "CD 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x180++0x1 line.word 0x00 "CD0,A/D Conversion Data Register 0" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x182++0x1 line.word 0x00 "CD1,A/D Conversion Data Register 1" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x184++0x1 line.word 0x00 "CD2,A/D Conversion Data Register 2" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x186++0x1 line.word 0x00 "CD3,A/D Conversion Data Register 3" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x188++0x1 line.word 0x00 "CD4,A/D Conversion Data Register 4" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x188++0x1 line.word 0x00 "CD4,A/D Conversion Data Register 4" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x18A++0x1 line.word 0x00 "CD5,A/D Conversion Data Register 5" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x18A++0x1 line.word 0x00 "CD5,A/D Conversion Data Register 5" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x18C++0x1 line.word 0x00 "CD6,A/D Conversion Data Register 6" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x18C++0x1 line.word 0x00 "CD6,A/D Conversion Data Register 6" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x18E++0x1 line.word 0x00 "CD7,A/D Conversion Data Register 7" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x18E++0x1 line.word 0x00 "CD7,A/D Conversion Data Register 7" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x194++0x1 line.word 0x00 "CD10,A/D Conversion Data Register 10" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x194++0x1 line.word 0x00 "CD10,A/D Conversion Data Register 10" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x196++0x1 line.word 0x00 "CD11,A/D Conversion Data Register 11" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x196++0x1 line.word 0x00 "CD11,A/D Conversion Data Register 11" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x19C++0x1 line.word 0x00 "CD14,A/D Conversion Data Register 14" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19C++0x1 line.word 0x00 "CD14,A/D Conversion Data Register 14" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x19E++0x1 line.word 0x00 "CD15,A/D Conversion Data Register 15" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19E++0x1 line.word 0x00 "CD15,A/D Conversion Data Register 15" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1A6++0x1 line.word 0x00 "CD19,A/D Conversion Data Register 19" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1A8++0x1 line.word 0x00 "CD20,A/D Conversion Data Register 20" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1AC++0x1 line.word 0x00 "CD22,A/D Conversion Data Register 22" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1AE++0x1 line.word 0x00 "CD23,A/D Conversion Data Register 23" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1B2++0x1 line.word 0x00 "CD25,A/D Conversion Data Register 25" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B2++0x1 line.word 0x00 "CD25,A/D Conversion Data Register 25" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1B4++0x1 line.word 0x00 "CD26,A/D Conversion Data Register 26" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B4++0x1 line.word 0x00 "CD26,A/D Conversion Data Register 26" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1B6++0x1 line.word 0x00 "CD27,A/D Conversion Data Register 27" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1B8++0x1 line.word 0x00 "CD28,A/D Conversion Data Register 28" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B8++0x1 line.word 0x00 "CD28,A/D Conversion Data Register 28" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1BA++0x1 line.word 0x00 "CD29,A/D Conversion Data Register 29" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BA++0x1 line.word 0x00 "CD29,A/D Conversion Data Register 29" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") rgroup.word 0x1BC++0x1 line.word 0x00 "CD30,A/D Conversion Data Register 30" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BC++0x1 line.word 0x00 "CD30,A/D Conversion Data Register 30" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C2++0x1 line.word 0x00 "CD33,A/D Conversion Data Register 33" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C4++0x1 line.word 0x00 "CD34,A/D Conversion Data Register 34" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C6++0x1 line.word 0x00 "CD35,A/D Conversion Data Register 35" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1C8++0x1 line.word 0x00 "CD36,A/D Conversion Data Register 36" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1CA++0x1 line.word 0x00 "CD37,A/D Conversion Data Register 37" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1CC++0x1 line.word 0x00 "CD38,A/D Conversion Data Register 38" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else rgroup.word 0x1E0++0x1 line.word 0x00 "CD48,A/D Conversion Data Register 48" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif cpuis("S6J335?H?") rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" elif cpuis("S6J335?J?") rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif tree.end width 10. tree "PCCTRL 0-63" sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x200++0x3 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x204++0x3 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x208++0x3 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x20C++0x3 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x210++0x3 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x210++0x3 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x214++0x3 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x214++0x3 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x218++0x3 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x218++0x3 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x21C++0x3 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x21C++0x3 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x228++0x3 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x228++0x3 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x22C++0x3 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x22C++0x3 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x238++0x3 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x238++0x3 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x23C++0x3 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x23C++0x3 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x24C++0x3 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x250++0x3 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x258++0x3 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x25C++0x3 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x264++0x3 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x264++0x3 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x268++0x3 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x268++0x3 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x26C++0x3 line.long 0x00 "PCCTRL27,Pulse Counter Control Register 27" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x270++0x3 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x270++0x3 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x274++0x3 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x274++0x3 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") group.long 0x278++0x3 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x278++0x3 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x284++0x3 line.long 0x00 "PCCTRL33,Pulse Counter Control Register 33" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x288++0x3 line.long 0x00 "PCCTRL34,Pulse Counter Control Register 34" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x28C++0x3 line.long 0x00 "PCCTRL35,Pulse Counter Control Register 35" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x290++0x3 line.long 0x00 "PCCTRL36,Pulse Counter Control Register 36" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x294++0x3 line.long 0x00 "PCCTRL37,Pulse Counter Control Register 37" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x298++0x3 line.long 0x00 "PCCTRL38,Pulse Counter Control Register 38" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") elif cpuis("S6J335?J?") else group.long 0x2C0++0x3 line.long 0x00 "PCCTRL48,Pulse Counter Control Register 48" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif cpuis("S6J335?H?") group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" elif cpuis("S6J335?J?") group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif tree.end textline "" width 19. sif cpuis("S6J335?H?") group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif cpuis("S6J335?J?") group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag 28" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag 26" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag 7" "Not requested,Requested" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag 4" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger overrun clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger overrun clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger overrun clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger overrun clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger overrun clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger overrun clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger overrun clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger overrun clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger overrun clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger overrun clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger overrun clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger overrun clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger overrun clear bit 4" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" textline " " bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" textline " " bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" textline " " bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" textline " " bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Conversion done interrupt flag 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Conversion done interrupt flag 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Conversion done interrupt flag 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Conversion done interrupt flag 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Conversion done interrupt flag 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Conversion done interrupt flag 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Conversion done interrupt flag 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Conversion done interrupt flag 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Conversion done interrupt flag 0" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Conversion done interrupt flag 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Conversion done interrupt flag 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Conversion done interrupt flag 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Conversion done interrupt flag 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Conversion done interrupt flag 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Conversion done interrupt flag 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Conversion done interrupt flag 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Group interrupted interrupt 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Group interrupted interrupt 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Group interrupted interrupt 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Group interrupted interrupt 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Group interrupted interrupt 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Group interrupted interrupt 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Group interrupted interrupt 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Group interrupted interrupt 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Group interrupted interrupt 0" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Group interrupted interrupt 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Group interrupted interrupt 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Group interrupted interrupt 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Group interrupted interrupt 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Group interrupted interrupt 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Group interrupted interrupt 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Group interrupted interrupt 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Range comparator interrupt flag 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Range comparator interrupt flag 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Range comparator interrupt flag 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Range comparator interrupt flag 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Range comparator interrupt flag 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Range comparator interrupt flag 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Range comparator interrupt flag 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Range comparator interrupt flag 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Range comparator interrupt flag 0" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Range comparator interrupt flag 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Range comparator interrupt flag 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Range comparator interrupt flag 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Range comparator interrupt flag 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Range comparator interrupt flag 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Range comparator interrupt flag 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Range comparator interrupt flag 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Pulse counter interrupt bit 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Pulse counter interrupt bit 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Pulse counter interrupt bit 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Pulse counter interrupt bit 20" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Pulse counter interrupt bit 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Pulse counter interrupt bit 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Pulse counter interrupt bit 2" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Pulse counter interrupt bit 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Pulse counter interrupt bit 0" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [48] ,Pulse counter interrupt bit 48" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [38] ,Pulse counter interrupt bit 38" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [37] ,Pulse counter interrupt bit 37" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [36] ,Pulse counter interrupt bit 36" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [35] ,Pulse counter interrupt bit 35" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [34] ,Pulse counter interrupt bit 34" "Not detected,Detected" textline " " setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [33] ,Pulse counter interrupt bit 33" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag 28" "Not requested,Requested" bitfld.long 0x00 27. " [27] ,A/D channel trigger status flag 27" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag 26" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 23. " [23] ,A/D channel trigger status flag 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag 20" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag 19" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag 14" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag 7" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag 4" "Not requested,Requested" bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag 3" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag 2" "Not requested,Requested" textline " " bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag 1" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag 0" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 16. " [48] ,A/D channel trigger status flag 48" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 6. " [38] ,A/D channel trigger status flag 38" "Not requested,Requested" bitfld.long 0x00 5. " [37] ,A/D channel trigger status flag 37" "Not requested,Requested" bitfld.long 0x00 4. " [36] ,A/D channel trigger status flag 36" "Not requested,Requested" bitfld.long 0x00 3. " [35] ,A/D channel trigger status flag 35" "Not requested,Requested" bitfld.long 0x00 2. " [34] ,A/D channel trigger status flag 34" "Not requested,Requested" textline " " bitfld.long 0x00 1. " [33] ,A/D channel trigger status flag 33" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 27. " [27] ,Trigger status clear bit 27" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 23. " [23] ,Trigger status clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,Trigger status clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,Trigger status clear bit 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " [19] ,Trigger status clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" bitfld.long 0x00 3. " [3] ,Trigger status clear bit 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Trigger status clear bit 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " [1] ,Trigger status clear bit 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Trigger status clear bit 0" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 16. " [48] ,Trigger status clear bit 48" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 6. " [38] ,Trigger status clear bit 38" "No effect,Clear" bitfld.long 0x00 5. " [37] ,Trigger status clear bit 37" "No effect,Clear" bitfld.long 0x00 4. " [36] ,Trigger status clear bit 36" "No effect,Clear" bitfld.long 0x00 3. " [35] ,Trigger status clear bit 35" "No effect,Clear" bitfld.long 0x00 2. " [34] ,Trigger status clear bit 34" "No effect,Clear" textline " " bitfld.long 0x00 1. " [33] ,Trigger status clear bit 33" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun flag 27" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun flag 23" "Not occurred,Occurred" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 16. " [48] ,A/D channel trigger overrun flag 48" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 6. " [38] ,A/D channel trigger overrun flag 38" "Not occurred,Occurred" bitfld.long 0x00 5. " [37] ,A/D channel trigger overrun flag 37" "Not occurred,Occurred" bitfld.long 0x00 4. " [36] ,A/D channel trigger overrun flag 36" "Not occurred,Occurred" bitfld.long 0x00 3. " [35] ,A/D channel trigger overrun flag 35" "Not occurred,Occurred" bitfld.long 0x00 2. " [34] ,A/D channel trigger overrun flag 34" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " [33] ,A/D channel trigger overrun flag 33" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger overrun clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger overrun clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger overrun clear bit 28" "No effect,Clear" bitfld.long 0x00 27. " [27] ,Trigger overrun clear bit 27" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger overrun clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger overrun clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 23. " [23] ,Trigger overrun clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,Trigger overrun clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,Trigger overrun clear bit 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " [19] ,Trigger overrun clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger overrun clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger overrun clear bit 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" bitfld.long 0x00 11. " [11] ,Trigger overrun clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger overrun clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " [7] ,Trigger overrun clear bit 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Trigger overrun clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger overrun clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger overrun clear bit 4" "No effect,Clear" bitfld.long 0x00 3. " [3] ,Trigger overrun clear bit 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Trigger overrun clear bit 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " [1] ,Trigger overrun clear bit 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Trigger overrun clear bit 0" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 16. " [48] ,Trigger overrun clear bit 48" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 6. " [38] ,Trigger overrun clear bit 38" "No effect,Clear" bitfld.long 0x00 5. " [37] ,Trigger overrun clear bit 37" "No effect,Clear" bitfld.long 0x00 4. " [36] ,Trigger overrun clear bit 36" "No effect,Clear" bitfld.long 0x00 3. " [35] ,Trigger overrun clear bit 35" "No effect,Clear" bitfld.long 0x00 2. " [34] ,Trigger overrun clear bit 34" "No effect,Clear" textline " " bitfld.long 0x00 1. " [33] ,Trigger overrun clear bit 33" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 27. " [27] ,Range comparator over threshold flag 27" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 23. " [23] ,Range comparator over threshold flag 23" "Less or equal,Above" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less or equal,Above" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less or equal,Above" textline " " bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less or equal,Above" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 16. " [48] ,Range comparator over threshold flag 48" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 6. " [38] ,Range comparator over threshold flag 38" "Less or equal,Above" bitfld.long 0x00 5. " [37] ,Range comparator over threshold flag 37" "Less or equal,Above" bitfld.long 0x00 4. " [36] ,Range comparator over threshold flag 36" "Less or equal,Above" bitfld.long 0x00 3. " [35] ,Range comparator over threshold flag 35" "Less or equal,Above" bitfld.long 0x00 2. " [34] ,Range comparator over threshold flag 34" "Less or equal,Above" textline " " bitfld.long 0x00 1. " [33] ,Range comparator over threshold flag 33" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.word 0x390++0xF line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,A/D converter resumption time setting bits" line.word 0x04 "ST0,A/D converter sampling time setting register" line.word 0x06 "ST1,A/D converter sampling time setting register" line.word 0x08 "ST2,A/D converter sampling time setting register" line.word 0x0A "ST3,A/D converter sampling time setting register" line.word 0x0C "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x0C 0.--7. 1. " OCV ,Offset compensation value" line.word 0x0E "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x0E 0.--4. " GCV ,Gain Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0400+0x3A0)&0x10)==0x00) group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,10-bit,12-bit,8-bit" else group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 6. " FSTP ,Forced stop" "No effect,Forced" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,12-bit,10-bit,8-bit" endif sif cpuis("S6J335?H?") rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif cpuis("S6J335?J?") rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B0++0x00 hide.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BA++0x00 hide.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BC++0x00 hide.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BE++0x00 hide.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B1++0x00 hide.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" else group.byte 0x3B1++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B3++0x00 hide.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" else group.byte 0x3B3++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B5++0x00 hide.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" else group.byte 0x3B5++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B7++0x00 hide.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" else group.byte 0x3B7++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F0++0x00 hide.byte 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F2++0x00 hide.byte 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F4++0x00 hide.byte 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F6++0x00 hide.byte 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F8++0x00 hide.byte 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FA++0x00 hide.byte 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FC++0x00 hide.byte 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FE++0x00 hide.byte 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D0++0x01 hide.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D2++0x01 hide.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D4++0x01 hide.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D6++0x01 hide.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D8++0x01 hide.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DA++0x01 hide.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DC++0x01 hide.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DE++0x01 hide.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" endif group.byte 0x3C0++0x0 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C1++0x0 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C2++0x0 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C3++0x0 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" textline " " bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x0 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E1++0x0 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E2++0x0 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E3++0x0 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0xB tree.end tree.end elif (cpuis("S6J336*")||cpuis("S6J337*")) tree "ADC12B (12/10/8-BIT ANALOG TO DIGITAL CONVERTER)" base ad:0xB48C0400 width 10. tree "A/D Channel Control Registers" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,A/D Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x4++0x03 line.long 0x00 "CHCTRL1,A/D Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x8++0x03 line.long 0x00 "CHCTRL2,A/D Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xC++0x03 line.long 0x00 "CHCTRL3,A/D Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x10++0x03 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x14++0x03 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x18++0x03 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x20++0x03 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x24++0x03 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x28++0x03 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x30++0x03 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x34++0x03 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x38++0x03 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x3C++0x03 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x40++0x03 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x44++0x03 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x48++0x03 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x4C++0x03 line.long 0x00 "CHCTRL19,A/D Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x50++0x03 line.long 0x00 "CHCTRL20,A/D Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x54++0x03 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x58++0x03 line.long 0x00 "CHCTRL22,A/D Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x5C++0x03 line.long 0x00 "CHCTRL23,A/D Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x60++0x03 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x64++0x03 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x68++0x03 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x6C++0x03 line.long 0x00 "CHCTRL27,A/D Channel Control Register 27" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x70++0x03 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x74++0x03 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x78++0x03 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x7C++0x03 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x80++0x03 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x84++0x03 line.long 0x00 "CHCTRL33,A/D Channel Control Register 33" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x88++0x03 line.long 0x00 "CHCTRL34,A/D Channel Control Register 34" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x8C++0x03 line.long 0x00 "CHCTRL35,A/D Channel Control Register 35" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x90++0x03 line.long 0x00 "CHCTRL36,A/D Channel Control Register 36" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x94++0x03 line.long 0x00 "CHCTRL37,A/D Channel Control Register 37" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x98++0x03 line.long 0x00 "CHCTRL38,A/D Channel Control Register 38" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0x9C++0x03 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xA0++0x03 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xA4++0x03 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xA8++0x03 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xAC++0x03 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xB0++0x03 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xB4++0x03 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xB8++0x03 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xBC++0x03 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xC0++0x03 line.long 0x00 "CHCTRL48,A/D Channel Control Register 48" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xC4++0x03 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xC8++0x03 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xCC++0x03 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xD0++0x03 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xD4++0x03 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xD8++0x03 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xDC++0x03 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xE0++0x03 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xE4++0x03 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xE8++0x03 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xEC++0x03 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xF0++0x03 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xF4++0x03 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xF8++0x03 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif group.long 0xFC++0x03 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" newline bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset,?..." bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" newline bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" sif cpuis("S6J336?H?")||cpuis("S6J337?H?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,,,,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,,,,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." elif cpuis("S6J336?J?")||cpuis("S6J337?J?") bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" "AN0,AN1,AN2,AN3,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,AN19,AN20,AN21,AN22,AN23,AN24,AN25,AN26,AN27,AN28,AN29,AN30,AN31,AN32,AN33,AN34,AN35,AN36,AN37,AN38,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,?..." endif tree.end tree "A/D Channel Status Registers" rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,A/D Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,A/D Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,A/D Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,A/D Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x11E++0x01 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x120++0x01 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x122++0x01 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x124++0x01 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x126++0x01 line.word 0x00 "CHSTAT19,A/D Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x128++0x01 line.word 0x00 "CHSTAT20,A/D Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x12A++0x01 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x12C++0x01 line.word 0x00 "CHSTAT22,A/D Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x12E++0x01 line.word 0x00 "CHSTAT23,A/D Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x130++0x01 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x132++0x01 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x134++0x01 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x136++0x01 line.word 0x00 "CHSTAT27,A/D Channel Status Register 27" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x138++0x01 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x13A++0x01 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x13C++0x01 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x13E++0x01 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x140++0x01 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x142++0x01 line.word 0x00 "CHSTAT33,A/D Channel Status Register 33" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x144++0x01 line.word 0x00 "CHSTAT34,A/D Channel Status Register 34" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x146++0x01 line.word 0x00 "CHSTAT35,A/D Channel Status Register 35" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x148++0x01 line.word 0x00 "CHSTAT36,A/D Channel Status Register 36" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x14A++0x01 line.word 0x00 "CHSTAT37,A/D Channel Status Register 37" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x14C++0x01 line.word 0x00 "CHSTAT38,A/D Channel Status Register 38" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x14E++0x01 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x150++0x01 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x152++0x01 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x154++0x01 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x156++0x01 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x158++0x01 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x15A++0x01 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x15C++0x01 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x15E++0x01 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x160++0x01 line.word 0x00 "CHSTAT48,A/D Channel Status Register 48" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x162++0x01 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x164++0x01 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x166++0x01 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x168++0x01 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x16A++0x01 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x16C++0x01 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x16E++0x01 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x170++0x01 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x172++0x01 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x174++0x01 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x176++0x01 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x178++0x01 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x17A++0x01 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x17C++0x01 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" rgroup.word 0x17E++0x01 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" tree.end width 6. tree "A/D Conversion Data Registers" hgroup.word 0x180++0x01 hide.word 0x00 "CD0,A/D Conversion Data Register 0" in hgroup.word 0x182++0x01 hide.word 0x00 "CD1,A/D Conversion Data Register 1" in hgroup.word 0x184++0x01 hide.word 0x00 "CD2,A/D Conversion Data Register 2" in hgroup.word 0x186++0x01 hide.word 0x00 "CD3,A/D Conversion Data Register 3" in hgroup.word 0x188++0x01 hide.word 0x00 "CD4,A/D Conversion Data Register 4" in hgroup.word 0x18A++0x01 hide.word 0x00 "CD5,A/D Conversion Data Register 5" in hgroup.word 0x18C++0x01 hide.word 0x00 "CD6,A/D Conversion Data Register 6" in hgroup.word 0x18E++0x01 hide.word 0x00 "CD7,A/D Conversion Data Register 7" in hgroup.word 0x190++0x01 hide.word 0x00 "CD8,A/D Conversion Data Register 8" in hgroup.word 0x192++0x01 hide.word 0x00 "CD9,A/D Conversion Data Register 9" in hgroup.word 0x194++0x01 hide.word 0x00 "CD10,A/D Conversion Data Register 10" in hgroup.word 0x196++0x01 hide.word 0x00 "CD11,A/D Conversion Data Register 11" in hgroup.word 0x198++0x01 hide.word 0x00 "CD12,A/D Conversion Data Register 12" in hgroup.word 0x19A++0x01 hide.word 0x00 "CD13,A/D Conversion Data Register 13" in hgroup.word 0x19C++0x01 hide.word 0x00 "CD14,A/D Conversion Data Register 14" in hgroup.word 0x19E++0x01 hide.word 0x00 "CD15,A/D Conversion Data Register 15" in hgroup.word 0x1A0++0x01 hide.word 0x00 "CD16,A/D Conversion Data Register 16" in hgroup.word 0x1A2++0x01 hide.word 0x00 "CD17,A/D Conversion Data Register 17" in hgroup.word 0x1A4++0x01 hide.word 0x00 "CD18,A/D Conversion Data Register 18" in hgroup.word 0x1A6++0x01 hide.word 0x00 "CD19,A/D Conversion Data Register 19" in hgroup.word 0x1A8++0x01 hide.word 0x00 "CD20,A/D Conversion Data Register 20" in hgroup.word 0x1AA++0x01 hide.word 0x00 "CD21,A/D Conversion Data Register 21" in hgroup.word 0x1AC++0x01 hide.word 0x00 "CD22,A/D Conversion Data Register 22" in hgroup.word 0x1AE++0x01 hide.word 0x00 "CD23,A/D Conversion Data Register 23" in hgroup.word 0x1B0++0x01 hide.word 0x00 "CD24,A/D Conversion Data Register 24" in hgroup.word 0x1B2++0x01 hide.word 0x00 "CD25,A/D Conversion Data Register 25" in hgroup.word 0x1B4++0x01 hide.word 0x00 "CD26,A/D Conversion Data Register 26" in hgroup.word 0x1B6++0x01 hide.word 0x00 "CD27,A/D Conversion Data Register 27" in hgroup.word 0x1B8++0x01 hide.word 0x00 "CD28,A/D Conversion Data Register 28" in hgroup.word 0x1BA++0x01 hide.word 0x00 "CD29,A/D Conversion Data Register 29" in hgroup.word 0x1BC++0x01 hide.word 0x00 "CD30,A/D Conversion Data Register 30" in hgroup.word 0x1BE++0x01 hide.word 0x00 "CD31,A/D Conversion Data Register 31" in hgroup.word 0x1C0++0x01 hide.word 0x00 "CD32,A/D Conversion Data Register 32" in hgroup.word 0x1C2++0x01 hide.word 0x00 "CD33,A/D Conversion Data Register 33" in hgroup.word 0x1C4++0x01 hide.word 0x00 "CD34,A/D Conversion Data Register 34" in hgroup.word 0x1C6++0x01 hide.word 0x00 "CD35,A/D Conversion Data Register 35" in hgroup.word 0x1C8++0x01 hide.word 0x00 "CD36,A/D Conversion Data Register 36" in hgroup.word 0x1CA++0x01 hide.word 0x00 "CD37,A/D Conversion Data Register 37" in hgroup.word 0x1CC++0x01 hide.word 0x00 "CD38,A/D Conversion Data Register 38" in hgroup.word 0x1CE++0x01 hide.word 0x00 "CD39,A/D Conversion Data Register 39" in hgroup.word 0x1D0++0x01 hide.word 0x00 "CD40,A/D Conversion Data Register 40" in hgroup.word 0x1D2++0x01 hide.word 0x00 "CD41,A/D Conversion Data Register 41" in hgroup.word 0x1D4++0x01 hide.word 0x00 "CD42,A/D Conversion Data Register 42" in hgroup.word 0x1D6++0x01 hide.word 0x00 "CD43,A/D Conversion Data Register 43" in hgroup.word 0x1D8++0x01 hide.word 0x00 "CD44,A/D Conversion Data Register 44" in hgroup.word 0x1DA++0x01 hide.word 0x00 "CD45,A/D Conversion Data Register 45" in hgroup.word 0x1DC++0x01 hide.word 0x00 "CD46,A/D Conversion Data Register 46" in hgroup.word 0x1DE++0x01 hide.word 0x00 "CD47,A/D Conversion Data Register 47" in hgroup.word 0x1E0++0x01 hide.word 0x00 "CD48,A/D Conversion Data Register 48" in hgroup.word 0x1E2++0x01 hide.word 0x00 "CD49,A/D Conversion Data Register 49" in hgroup.word 0x1E4++0x01 hide.word 0x00 "CD50,A/D Conversion Data Register 50" in hgroup.word 0x1E6++0x01 hide.word 0x00 "CD51,A/D Conversion Data Register 51" in hgroup.word 0x1E8++0x01 hide.word 0x00 "CD52,A/D Conversion Data Register 52" in hgroup.word 0x1EA++0x01 hide.word 0x00 "CD53,A/D Conversion Data Register 53" in hgroup.word 0x1EC++0x01 hide.word 0x00 "CD54,A/D Conversion Data Register 54" in hgroup.word 0x1EE++0x01 hide.word 0x00 "CD55,A/D Conversion Data Register 55" in hgroup.word 0x1F0++0x01 hide.word 0x00 "CD56,A/D Conversion Data Register 56" in hgroup.word 0x1F2++0x01 hide.word 0x00 "CD57,A/D Conversion Data Register 57" in hgroup.word 0x1F4++0x01 hide.word 0x00 "CD58,A/D Conversion Data Register 58" in hgroup.word 0x1F6++0x01 hide.word 0x00 "CD59,A/D Conversion Data Register 59" in hgroup.word 0x1F8++0x01 hide.word 0x00 "CD60,A/D Conversion Data Register 60" in hgroup.word 0x1FA++0x01 hide.word 0x00 "CD61,A/D Conversion Data Register 61" in hgroup.word 0x1FC++0x01 hide.word 0x00 "CD62,A/D Conversion Data Register 62" in hgroup.word 0x1FE++0x01 hide.word 0x00 "CD63,A/D Conversion Data Register 63" in tree.end width 10. tree "Pulse Counter Control Registers" group.long 0x200++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x204++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x208++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x20C++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x210++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x214++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x218++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x21C++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x220++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x224++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x228++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x22C++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x230++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x234++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x238++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x23C++0x03 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x240++0x03 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x244++0x03 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x248++0x03 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x24C++0x03 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x250++0x03 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x254++0x03 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x258++0x03 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x25C++0x03 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x260++0x03 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x264++0x03 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x268++0x03 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x26C++0x03 line.long 0x00 "PCCTRL27,Pulse Counter Control Register 27" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x270++0x03 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x274++0x03 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x278++0x03 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x27C++0x03 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x280++0x03 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x284++0x03 line.long 0x00 "PCCTRL33,Pulse Counter Control Register 33" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x288++0x03 line.long 0x00 "PCCTRL34,Pulse Counter Control Register 34" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x28C++0x03 line.long 0x00 "PCCTRL35,Pulse Counter Control Register 35" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x290++0x03 line.long 0x00 "PCCTRL36,Pulse Counter Control Register 36" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x294++0x03 line.long 0x00 "PCCTRL37,Pulse Counter Control Register 37" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x298++0x03 line.long 0x00 "PCCTRL38,Pulse Counter Control Register 38" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x29C++0x03 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2A0++0x03 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2A4++0x03 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2A8++0x03 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2AC++0x03 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2B0++0x03 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2B4++0x03 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2B8++0x03 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2BC++0x03 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2C0++0x03 line.long 0x00 "PCCTRL48,Pulse Counter Control Register 48" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2C4++0x03 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2C8++0x03 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2CC++0x03 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2D0++0x03 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2D4++0x03 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2D8++0x03 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2DC++0x03 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2E0++0x03 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2E4++0x03 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2E8++0x03 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2EC++0x03 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2F0++0x03 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2F4++0x03 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2F8++0x03 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" group.long 0x2FC++0x03 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" tree.end newline width 19. group.long 0x300++0x07 line.long 0x00 "CDONEIRQ0_SET/CLR,A/D Conversion Done Interrupt Flag Register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Conversion done interrupt flag 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" newline setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Conversion done interrupt flag 15" "Not detected,Detected" newline setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Conversion done interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" newline setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" newline setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Conversion done interrupt flag 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Conversion done interrupt flag 2" "Not detected,Detected" newline setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Conversion done interrupt flag 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Conversion done interrupt flag 0" "Not detected,Detected" line.long 0x04 "CDONEIRQ1_SET/CLR,A/D Conversion Done Interrupt Flag Register 1" setclrfld.long 0x04 31. 0x0C 31. 0x14 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x04 30. 0x0C 30. 0x14 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x04 29. 0x0C 29. 0x14 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x04 28. 0x0C 28. 0x14 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x04 27. 0x0C 27. 0x14 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x04 26. 0x0C 26. 0x14 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" newline setclrfld.long 0x04 25. 0x0C 25. 0x14 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x04 24. 0x0C 24. 0x14 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x04 23. 0x0C 23. 0x14 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x04 22. 0x0C 22. 0x14 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x04 21. 0x0C 21. 0x14 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x04 20. 0x0C 20. 0x14 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" newline setclrfld.long 0x04 19. 0x0C 19. 0x14 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x04 18. 0x0C 18. 0x14 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x04 17. 0x0C 17. 0x14 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x04 16. 0x0C 16. 0x14 16. " [48] ,Conversion done interrupt flag 48" "Not detected,Detected" setclrfld.long 0x04 15. 0x0C 15. 0x14 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x04 14. 0x0C 14. 0x14 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" newline setclrfld.long 0x04 13. 0x0C 13. 0x14 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x04 12. 0x0C 12. 0x14 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x04 11. 0x0C 11. 0x14 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x04 10. 0x0C 10. 0x14 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x04 9. 0x0C 9. 0x14 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x04 8. 0x0C 8. 0x14 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" newline setclrfld.long 0x04 7. 0x0C 7. 0x14 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x04 6. 0x0C 6. 0x14 6. " [38] ,Conversion done interrupt flag 38" "Not detected,Detected" setclrfld.long 0x04 5. 0x0C 5. 0x14 5. " [37] ,Conversion done interrupt flag 37" "Not detected,Detected" setclrfld.long 0x04 4. 0x0C 4. 0x14 4. " [36] ,Conversion done interrupt flag 36" "Not detected,Detected" setclrfld.long 0x04 3. 0x0C 3. 0x14 3. " [35] ,Conversion done interrupt flag 35" "Not detected,Detected" setclrfld.long 0x04 2. 0x0C 2. 0x14 2. " [34] ,Conversion done interrupt flag 34" "Not detected,Detected" newline setclrfld.long 0x04 1. 0x0C 1. 0x14 1. " [33] ,Conversion done interrupt flag 33" "Not detected,Detected" setclrfld.long 0x04 0. 0x0C 0. 0x14 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x07 line.long 0x00 "GRPIRQ0_SET/CLR,Group Interrupted Interrupt Flag Register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Group interrupted interrupt 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" newline setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Group interrupted interrupt 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Group interrupted interrupt 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Group interrupted interrupt 20" "Not detected,Detected" newline setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Group interrupted interrupt 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" newline setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" newline setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Group interrupted interrupt 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Group interrupted interrupt 2" "Not detected,Detected" newline setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Group interrupted interrupt 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Group interrupted interrupt 0" "Not detected,Detected" line.long 0x04 "GRPIRQ1_SET/CLR,Group Interrupted Interrupt Flag Register 1" setclrfld.long 0x04 31. 0x0C 31. 0x14 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x04 30. 0x0C 30. 0x14 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x04 29. 0x0C 29. 0x14 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x04 28. 0x0C 28. 0x14 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x04 27. 0x0C 27. 0x14 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x04 26. 0x0C 26. 0x14 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" newline setclrfld.long 0x04 25. 0x0C 25. 0x14 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x04 24. 0x0C 24. 0x14 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x04 23. 0x0C 23. 0x14 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x04 22. 0x0C 22. 0x14 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x04 21. 0x0C 21. 0x14 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x04 20. 0x0C 20. 0x14 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" newline setclrfld.long 0x04 19. 0x0C 19. 0x14 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x04 18. 0x0C 18. 0x14 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x04 17. 0x0C 17. 0x14 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x04 16. 0x0C 16. 0x14 16. " [48] ,Group interrupted interrupt 48" "Not detected,Detected" setclrfld.long 0x04 15. 0x0C 15. 0x14 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x04 14. 0x0C 14. 0x14 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" newline setclrfld.long 0x04 13. 0x0C 13. 0x14 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x04 12. 0x0C 12. 0x14 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x04 11. 0x0C 11. 0x14 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x04 10. 0x0C 10. 0x14 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x04 9. 0x0C 9. 0x14 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x04 8. 0x0C 8. 0x14 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" newline setclrfld.long 0x04 7. 0x0C 7. 0x14 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x04 6. 0x0C 6. 0x14 6. " [38] ,Group interrupted interrupt 38" "Not detected,Detected" setclrfld.long 0x04 5. 0x0C 5. 0x14 5. " [37] ,Group interrupted interrupt 37" "Not detected,Detected" setclrfld.long 0x04 4. 0x0C 4. 0x14 4. " [36] ,Group interrupted interrupt 36" "Not detected,Detected" setclrfld.long 0x04 3. 0x0C 3. 0x14 3. " [35] ,Group interrupted interrupt 35" "Not detected,Detected" setclrfld.long 0x04 2. 0x0C 2. 0x14 2. " [34] ,Group interrupted interrupt 34" "Not detected,Detected" newline setclrfld.long 0x04 1. 0x0C 1. 0x14 1. " [33] ,Group interrupted interrupt 33" "Not detected,Detected" setclrfld.long 0x04 0. 0x0C 0. 0x14 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x07 line.long 0x00 "RCIRQ0_SET/CLR,Range Comparator Interrupt Flag Register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Range comparator interrupt flag 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" newline setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Range comparator interrupt flag 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Range comparator interrupt flag 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Range comparator interrupt flag 20" "Not detected,Detected" newline setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Range comparator interrupt flag 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" newline setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" newline setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Range comparator interrupt flag 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Range comparator interrupt flag 2" "Not detected,Detected" newline setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Range comparator interrupt flag 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Range comparator interrupt flag 0" "Not detected,Detected" line.long 0x04 "RCIRQ1_SET/CLR,Range Comparator Interrupt Flag Register 1" setclrfld.long 0x04 31. 0x0C 31. 0x14 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x04 30. 0x0C 30. 0x14 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x04 29. 0x0C 29. 0x14 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x04 28. 0x0C 28. 0x14 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x04 27. 0x0C 27. 0x14 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x04 26. 0x0C 26. 0x14 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" newline setclrfld.long 0x04 25. 0x0C 25. 0x14 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x04 24. 0x0C 24. 0x14 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x04 23. 0x0C 23. 0x14 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x04 22. 0x0C 22. 0x14 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x04 21. 0x0C 21. 0x14 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x04 20. 0x0C 20. 0x14 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" newline setclrfld.long 0x04 19. 0x0C 19. 0x14 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x04 18. 0x0C 18. 0x14 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x04 17. 0x0C 17. 0x14 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x04 16. 0x0C 16. 0x14 16. " [48] ,Range comparator interrupt flag 48" "Not detected,Detected" setclrfld.long 0x04 15. 0x0C 15. 0x14 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x04 14. 0x0C 14. 0x14 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" newline setclrfld.long 0x04 13. 0x0C 13. 0x14 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x04 12. 0x0C 12. 0x14 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x04 11. 0x0C 11. 0x14 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x04 10. 0x0C 10. 0x14 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x04 9. 0x0C 9. 0x14 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x04 8. 0x0C 8. 0x14 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" newline setclrfld.long 0x04 7. 0x0C 7. 0x14 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x04 6. 0x0C 6. 0x14 6. " [38] ,Range comparator interrupt flag 38" "Not detected,Detected" setclrfld.long 0x04 5. 0x0C 5. 0x14 5. " [37] ,Range comparator interrupt flag 37" "Not detected,Detected" setclrfld.long 0x04 4. 0x0C 4. 0x14 4. " [36] ,Range comparator interrupt flag 36" "Not detected,Detected" setclrfld.long 0x04 3. 0x0C 3. 0x14 3. " [35] ,Range comparator interrupt flag 35" "Not detected,Detected" setclrfld.long 0x04 2. 0x0C 2. 0x14 2. " [34] ,Range comparator interrupt flag 34" "Not detected,Detected" newline setclrfld.long 0x04 1. 0x0C 1. 0x14 1. " [33] ,Range comparator interrupt flag 33" "Not detected,Detected" setclrfld.long 0x04 0. 0x0C 0. 0x14 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x07 line.long 0x00 "PCIRQ0_SET/CLR,Pulse Counter Interrupt Flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [27] ,Pulse counter interrupt bit 27" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" newline setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [23] ,Pulse counter interrupt bit 23" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [22] ,Pulse counter interrupt bit 22" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [20] ,Pulse counter interrupt bit 20" "Not detected,Detected" newline setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [19] ,Pulse counter interrupt bit 19" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" newline setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" newline setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" setclrfld.long 0x00 3. 0x08 3. 0x10 3. " [3] ,Pulse counter interrupt bit 3" "Not detected,Detected" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " [2] ,Pulse counter interrupt bit 2" "Not detected,Detected" newline setclrfld.long 0x00 1. 0x08 1. 0x10 1. " [1] ,Pulse counter interrupt bit 1" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [0] ,Pulse counter interrupt bit 0" "Not detected,Detected" line.long 0x04 "PCIRQ1_SET/CLR,Pulse Counter Interrupt Flag register 1" setclrfld.long 0x04 31. 0x0C 31. 0x14 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x04 30. 0x0C 30. 0x14 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x04 29. 0x0C 29. 0x14 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x04 28. 0x0C 28. 0x14 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x04 27. 0x0C 27. 0x14 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x04 26. 0x0C 26. 0x14 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" newline setclrfld.long 0x04 25. 0x0C 25. 0x14 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x04 24. 0x0C 24. 0x14 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x04 23. 0x0C 23. 0x14 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x04 22. 0x0C 22. 0x14 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x04 21. 0x0C 21. 0x14 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x04 20. 0x0C 20. 0x14 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" newline setclrfld.long 0x04 19. 0x0C 19. 0x14 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x04 18. 0x0C 18. 0x14 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x04 17. 0x0C 17. 0x14 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x04 16. 0x0C 16. 0x14 16. " [48] ,Pulse counter interrupt bit 48" "Not detected,Detected" setclrfld.long 0x04 15. 0x0C 15. 0x14 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x04 14. 0x0C 14. 0x14 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" newline setclrfld.long 0x04 13. 0x0C 13. 0x14 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x04 12. 0x0C 12. 0x14 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x04 11. 0x0C 11. 0x14 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x04 10. 0x0C 10. 0x14 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x04 9. 0x0C 9. 0x14 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x04 8. 0x0C 8. 0x14 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" newline setclrfld.long 0x04 7. 0x0C 7. 0x14 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x04 6. 0x0C 6. 0x14 6. " [38] ,Pulse counter interrupt bit 38" "Not detected,Detected" setclrfld.long 0x04 5. 0x0C 5. 0x14 5. " [37] ,Pulse counter interrupt bit 37" "Not detected,Detected" setclrfld.long 0x04 4. 0x0C 4. 0x14 4. " [36] ,Pulse counter interrupt bit 36" "Not detected,Detected" setclrfld.long 0x04 3. 0x0C 3. 0x14 3. " [35] ,Pulse counter interrupt bit 35" "Not detected,Detected" setclrfld.long 0x04 2. 0x0C 2. 0x14 2. " [34] ,Pulse counter interrupt bit 34" "Not detected,Detected" newline setclrfld.long 0x04 1. 0x0C 1. 0x14 1. " [33] ,Pulse counter interrupt bit 33" "Not detected,Detected" setclrfld.long 0x04 0. 0x0C 0. 0x14 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x07 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag bit 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag bit 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag bit 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag bit 28" "Not requested,Requested" bitfld.long 0x00 27. " [27] ,A/D channel trigger status flag bit 27" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag bit 26" "Not requested,Requested" newline bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag bit 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag bit 24" "Not requested,Requested" bitfld.long 0x00 23. " [23] ,A/D channel trigger status flag bit 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag bit 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag bit 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag bit 20" "Not requested,Requested" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag bit 19" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag bit 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag bit 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag bit 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag bit 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag bit 14" "Not requested,Requested" newline bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag bit 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag bit 12" "Not requested,Requested" bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag bit 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag bit 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag bit 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag bit 8" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag bit 7" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag bit 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag bit 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag bit 4" "Not requested,Requested" bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag bit 3" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag bit 2" "Not requested,Requested" newline bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag bit 1" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag bit 0" "Not requested,Requested" line.long 0x04 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x04 31. " TRGST_[63] ,A/D channel trigger status flag bit 63" "Not requested,Requested" bitfld.long 0x04 30. " [62] ,A/D channel trigger status flag bit 62" "Not requested,Requested" bitfld.long 0x04 29. " [61] ,A/D channel trigger status flag bit 61" "Not requested,Requested" bitfld.long 0x04 28. " [60] ,A/D channel trigger status flag bit 60" "Not requested,Requested" bitfld.long 0x04 27. " [59] ,A/D channel trigger status flag bit 59" "Not requested,Requested" bitfld.long 0x04 26. " [58] ,A/D channel trigger status flag bit 58" "Not requested,Requested" newline bitfld.long 0x04 25. " [57] ,A/D channel trigger status flag bit 57" "Not requested,Requested" bitfld.long 0x04 24. " [56] ,A/D channel trigger status flag bit 56" "Not requested,Requested" bitfld.long 0x04 23. " [55] ,A/D channel trigger status flag bit 55" "Not requested,Requested" bitfld.long 0x04 22. " [54] ,A/D channel trigger status flag bit 54" "Not requested,Requested" bitfld.long 0x04 21. " [53] ,A/D channel trigger status flag bit 53" "Not requested,Requested" bitfld.long 0x04 20. " [52] ,A/D channel trigger status flag bit 52" "Not requested,Requested" newline bitfld.long 0x04 19. " [51] ,A/D channel trigger status flag bit 51" "Not requested,Requested" bitfld.long 0x04 18. " [50] ,A/D channel trigger status flag bit 50" "Not requested,Requested" bitfld.long 0x04 17. " [49] ,A/D channel trigger status flag bit 49" "Not requested,Requested" bitfld.long 0x04 16. " [48] ,A/D channel trigger status flag bit 48" "Not requested,Requested" bitfld.long 0x04 15. " [47] ,A/D channel trigger status flag bit 47" "Not requested,Requested" bitfld.long 0x04 14. " [46] ,A/D channel trigger status flag bit 46" "Not requested,Requested" newline bitfld.long 0x04 13. " [45] ,A/D channel trigger status flag bit 45" "Not requested,Requested" bitfld.long 0x04 12. " [44] ,A/D channel trigger status flag bit 44" "Not requested,Requested" bitfld.long 0x04 11. " [43] ,A/D channel trigger status flag bit 43" "Not requested,Requested" bitfld.long 0x04 10. " [42] ,A/D channel trigger status flag bit 42" "Not requested,Requested" bitfld.long 0x04 9. " [41] ,A/D channel trigger status flag bit 41" "Not requested,Requested" bitfld.long 0x04 8. " [40] ,A/D channel trigger status flag bit 40" "Not requested,Requested" newline bitfld.long 0x04 7. " [39] ,A/D channel trigger status flag bit 39" "Not requested,Requested" bitfld.long 0x04 6. " [38] ,A/D channel trigger status flag bit 38" "Not requested,Requested" bitfld.long 0x04 5. " [37] ,A/D channel trigger status flag bit 37" "Not requested,Requested" bitfld.long 0x04 4. " [36] ,A/D channel trigger status flag bit 36" "Not requested,Requested" bitfld.long 0x04 3. " [35] ,A/D channel trigger status flag bit 35" "Not requested,Requested" bitfld.long 0x04 2. " [34] ,A/D channel trigger status flag bit 34" "Not requested,Requested" newline bitfld.long 0x04 1. " [33] ,A/D channel trigger status flag bit 33" "Not requested,Requested" bitfld.long 0x04 0. " [32] ,A/D channel trigger status flag bit 32" "Not requested,Requested" wgroup.long 0x368++0x07 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 27. " [27] ,Trigger status clear bit 27" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" newline bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 23. " [23] ,Trigger status clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,Trigger status clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,Trigger status clear bit 20" "No effect,Clear" newline bitfld.long 0x00 19. " [19] ,Trigger status clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" newline bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" newline bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" bitfld.long 0x00 3. " [3] ,Trigger status clear bit 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Trigger status clear bit 2" "No effect,Clear" newline bitfld.long 0x00 1. " [1] ,Trigger status clear bit 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Trigger status clear bit 0" "No effect,Clear" line.long 0x04 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x04 31. " TRGCT_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x04 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x04 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x04 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x04 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x04 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" newline bitfld.long 0x04 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x04 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x04 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x04 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x04 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x04 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" newline bitfld.long 0x04 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x04 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x04 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x04 16. " [48] ,Trigger status clear bit 48" "No effect,Clear" bitfld.long 0x04 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x04 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" newline bitfld.long 0x04 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x04 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x04 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x04 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x04 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x04 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" newline bitfld.long 0x04 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x04 6. " [38] ,Trigger status clear bit 38" "No effect,Clear" bitfld.long 0x04 5. " [37] ,Trigger status clear bit 37" "No effect,Clear" bitfld.long 0x04 4. " [36] ,Trigger status clear bit 36" "No effect,Clear" bitfld.long 0x04 3. " [35] ,Trigger status clear bit 35" "No effect,Clear" bitfld.long 0x04 2. " [34] ,Trigger status clear bit 34" "No effect,Clear" newline bitfld.long 0x04 1. " [33] ,Trigger status clear bit 33" "No effect,Clear" bitfld.long 0x04 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x07 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun flag 27" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun flag 23" "Not occurred,Occurred" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "Not occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "Not occurred,Occurred" line.long 0x04 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x04 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x04 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x04 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x04 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x04 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x04 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" newline bitfld.long 0x04 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x04 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x04 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x04 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x04 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x04 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" newline bitfld.long 0x04 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x04 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x04 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x04 16. " [48] ,A/D channel trigger overrun flag 48" "Not occurred,Occurred" bitfld.long 0x04 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x04 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" newline bitfld.long 0x04 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x04 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x04 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x04 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x04 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x04 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" newline bitfld.long 0x04 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x04 6. " [38] ,A/D channel trigger overrun flag 38" "Not occurred,Occurred" bitfld.long 0x04 5. " [37] ,A/D channel trigger overrun flag 37" "Not occurred,Occurred" bitfld.long 0x04 4. " [36] ,A/D channel trigger overrun flag 36" "Not occurred,Occurred" bitfld.long 0x04 3. " [35] ,A/D channel trigger overrun flag 35" "Not occurred,Occurred" bitfld.long 0x04 2. " [34] ,A/D channel trigger overrun flag 34" "Not occurred,Occurred" newline bitfld.long 0x04 1. " [33] ,A/D channel trigger overrun flag 33" "Not occurred,Occurred" bitfld.long 0x04 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x07 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 27. " [27] ,Trigger status clear bit 27" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" newline bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 23. " [23] ,Trigger status clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,Trigger status clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,Trigger status clear bit 20" "No effect,Clear" newline bitfld.long 0x00 19. " [19] ,Trigger status clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" newline bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" newline bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" bitfld.long 0x00 3. " [3] ,Trigger status clear bit 3" "No effect,Clear" bitfld.long 0x00 2. " [2] ,Trigger status clear bit 2" "No effect,Clear" newline bitfld.long 0x00 1. " [1] ,Trigger status clear bit 1" "No effect,Clear" bitfld.long 0x00 0. " [0] ,Trigger status clear bit 0" "No effect,Clear" line.long 0x04 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x04 31. " TRGORC_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x04 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x04 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x04 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x04 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x04 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" newline bitfld.long 0x04 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x04 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x04 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x04 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x04 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x04 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" newline bitfld.long 0x04 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x04 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x04 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x04 16. " [48] ,Trigger status clear bit 48" "No effect,Clear" bitfld.long 0x04 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x04 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" newline bitfld.long 0x04 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x04 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x04 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x04 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x04 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x04 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" newline bitfld.long 0x04 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x04 6. " [38] ,Trigger status clear bit 38" "No effect,Clear" bitfld.long 0x04 5. " [37] ,Trigger status clear bit 37" "No effect,Clear" bitfld.long 0x04 4. " [36] ,Trigger status clear bit 36" "No effect,Clear" bitfld.long 0x04 3. " [35] ,Trigger status clear bit 35" "No effect,Clear" bitfld.long 0x04 2. " [34] ,Trigger status clear bit 34" "No effect,Clear" newline bitfld.long 0x04 1. " [33] ,Trigger status clear bit 33" "No effect,Clear" bitfld.long 0x04 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x370++0x07 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 27. " [27] ,Range comparator over threshold flag 27" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" newline bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 23. " [23] ,Range comparator over threshold flag 23" "Less or equal,Above" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less or equal,Above" newline bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" newline bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" newline bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less or equal,Above" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less or equal,Above" newline bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less or equal,Above" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less or equal,Above" line.long 0x04 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x04 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x04 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x04 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x04 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x04 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x04 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" newline bitfld.long 0x04 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x04 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x04 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x04 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x04 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x04 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" newline bitfld.long 0x04 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x04 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x04 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x04 16. " [48] ,Range comparator over threshold flag 48" "Less or equal,Above" bitfld.long 0x04 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x04 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" newline bitfld.long 0x04 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x04 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x04 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x04 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x04 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x04 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" newline bitfld.long 0x04 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x04 6. " [38] ,Range comparator over threshold flag 38" "Less or equal,Above" bitfld.long 0x04 5. " [37] ,Range comparator over threshold flag 37" "Less or equal,Above" bitfld.long 0x04 4. " [36] ,Range comparator over threshold flag 36" "Less or equal,Above" bitfld.long 0x04 3. " [35] ,Range comparator over threshold flag 35" "Less or equal,Above" bitfld.long 0x04 2. " [34] ,Range comparator over threshold flag 34" "Less or equal,Above" newline bitfld.long 0x04 1. " [33] ,Range comparator over threshold flag 33" "Less or equal,Above" bitfld.long 0x04 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x390++0x0F line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,A/D converter resumption time setting bits" line.word 0x04 "ST0,A/D converter sampling time setting register" line.word 0x06 "ST1,A/D converter sampling time setting register" line.word 0x08 "ST2,A/D converter sampling time setting register" line.word 0x0A "ST3,A/D converter sampling time setting register" line.word 0x0C "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x0C 0.--7. 1. " OCV ,Offset compensation value" line.word 0x0E "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x0E 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0400+0x3A0)&0x10)==0x00) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" newline bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" newline bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,10-bit,12-bit,8-bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 6. " FSTP ,Forced stop" "No effect,Forced" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" newline bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" newline bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,12-bit,10-bit,8-bit" endif rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B1++0x00 hide.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" else group.byte 0x3B1++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B3++0x00 hide.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" else group.byte 0x3B3++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B5++0x00 hide.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" else group.byte 0x3B5++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B7++0x00 hide.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" else group.byte 0x3B7++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B0++0x00 hide.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BA++0x00 hide.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BC++0x00 hide.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BE++0x00 hide.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F0++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F0++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F0++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F0++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F0++0x00 hide.byte 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F2++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F2++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F2++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F2++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F2++0x00 hide.byte 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F4++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F4++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F4++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F4++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F4++0x00 hide.byte 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F6++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F6++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F6++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F6++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F6++0x00 hide.byte 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F8++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F8++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F8++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F8++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F8++0x00 hide.byte 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FA++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FA++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FA++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FA++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FA++0x00 hide.byte 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FC++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FC++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FC++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FC++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FC++0x00 hide.byte 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FE++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FE++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FE++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FE++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FE++0x00 hide.byte 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D0++0x01 hide.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D2++0x01 hide.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D4++0x01 hide.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D6++0x01 hide.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D8++0x01 hide.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DA++0x01 hide.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DC++0x01 hide.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DE++0x01 hide.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" newline bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" newline bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" newline bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH selection bit" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL selection bit" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra-channel interruptibility for the multiple conversion logical channel" "Able,Not able" newline bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversions for the multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x0 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E1++0x0 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E2++0x0 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." rgroup.byte 0x3E3++0x0 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion" "No conversion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B tree.end else tree "ADC12B (12/10/8-BIT ANALOG TO DIGITAL CONVERTER)" tree "ADC12B0" base ad:0xB48C0000 width 10. tree "CHCTRL 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x10++0x3 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x14++0x3 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x18++0x3 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x1C++0x3 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x28++0x3 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x2C++0x3 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x38++0x3 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x3C++0x3 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x64++0x3 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x68++0x3 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x70++0x3 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x74++0x3 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x78++0x3 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif tree.end tree "CHSTAT 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x108++0x1 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x10A++0x1 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x10C++0x1 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x10E++0x1 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x114++0x1 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x116++0x1 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x11C++0x1 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x11E++0x1 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x132++0x1 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x134++0x1 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x138++0x1 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x13A++0x1 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x13C++0x1 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif tree.end width 6. tree "CD 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x188++0x1 line.word 0x00 "CD4,A/D Conversion Data Register 4" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x18A++0x1 line.word 0x00 "CD5,A/D Conversion Data Register 5" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x18C++0x1 line.word 0x00 "CD6,A/D Conversion Data Register 6" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x18E++0x1 line.word 0x00 "CD7,A/D Conversion Data Register 7" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x194++0x1 line.word 0x00 "CD10,A/D Conversion Data Register 10" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x196++0x1 line.word 0x00 "CD11,A/D Conversion Data Register 11" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x19C++0x1 line.word 0x00 "CD14,A/D Conversion Data Register 14" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x19E++0x1 line.word 0x00 "CD15,A/D Conversion Data Register 15" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1B2++0x1 line.word 0x00 "CD25,A/D Conversion Data Register 25" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1B4++0x1 line.word 0x00 "CD26,A/D Conversion Data Register 26" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1B8++0x1 line.word 0x00 "CD28,A/D Conversion Data Register 28" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1BA++0x1 line.word 0x00 "CD29,A/D Conversion Data Register 29" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1BC++0x1 line.word 0x00 "CD30,A/D Conversion Data Register 30" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif tree.end width 10. tree "PCCTRL 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x210++0x3 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x214++0x3 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x218++0x3 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x21C++0x3 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x228++0x3 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x22C++0x3 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x238++0x3 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x23C++0x3 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x264++0x3 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x268++0x3 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x270++0x3 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x274++0x3 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x278++0x3 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif tree.end textline "" width 19. sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag 28" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag 26" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag 7" "Not requested,Requested" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag 4" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger overrun clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger overrun clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger overrun clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger overrun clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger overrun clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger overrun clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger overrun clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger overrun clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger overrun clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger overrun clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger overrun clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger overrun clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger overrun clear bit 4" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" textline " " bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" textline " " bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" textline " " bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" textline " " bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.word 0x390++0xF line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,A/D converter resumption time setting bits" line.word 0x04 "ST0,A/D converter sampling time setting register" line.word 0x06 "ST1,A/D converter sampling time setting register" line.word 0x08 "ST2,A/D converter sampling time setting register" line.word 0x0A "ST3,A/D converter sampling time setting register" line.word 0x0C "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x0C 0.--7. 1. " OCV ,Offset compensation value" line.word 0x0E "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x0E 0.--4. " GCV ,Gain Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0000+0x3A0)&0x10)==0x00) group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,10-bit,12-bit,8-bit" else group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 6. " FSTP ,Forced stop" "No effect,Forced" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,12-bit,10-bit,8-bit" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B0++0x00 hide.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3BA++0x00 hide.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3BC++0x00 hide.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3BE++0x00 hide.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B1++0x00 hide.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" else group.byte 0x3B1++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B3++0x00 hide.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" else group.byte 0x3B3++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B5++0x00 hide.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" else group.byte 0x3B5++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B7++0x00 hide.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" else group.byte 0x3B7++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F0++0x00 hide.byte 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F2++0x00 hide.byte 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F4++0x00 hide.byte 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F6++0x00 hide.byte 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F8++0x00 hide.byte 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FA++0x00 hide.byte 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FC++0x00 hide.byte 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FE++0x00 hide.byte 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D0++0x01 hide.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D2++0x01 hide.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D4++0x01 hide.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D6++0x01 hide.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D8++0x01 hide.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DA++0x01 hide.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DC++0x01 hide.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" endif if ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x20) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x21) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x22) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x23)==0x23) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DE++0x01 hide.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" endif width 0xB tree.end tree "ADC12B1" base ad:0xB48C0400 width 10. tree "CHCTRL 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x10++0x3 line.long 0x00 "CHCTRL4,A/D Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x14++0x3 line.long 0x00 "CHCTRL5,A/D Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x18++0x3 line.long 0x00 "CHCTRL6,A/D Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x1C++0x3 line.long 0x00 "CHCTRL7,A/D Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x20++0x3 line.long 0x00 "CHCTRL8,A/D Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x24++0x3 line.long 0x00 "CHCTRL9,A/D Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x28++0x3 line.long 0x00 "CHCTRL10,A/D Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x2C++0x3 line.long 0x00 "CHCTRL11,A/D Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x30++0x3 line.long 0x00 "CHCTRL12,A/D Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x34++0x3 line.long 0x00 "CHCTRL13,A/D Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x38++0x3 line.long 0x00 "CHCTRL14,A/D Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x3C++0x3 line.long 0x00 "CHCTRL15,A/D Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x40++0x3 line.long 0x00 "CHCTRL16,A/D Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x44++0x3 line.long 0x00 "CHCTRL17,A/D Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x48++0x3 line.long 0x00 "CHCTRL18,A/D Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x54++0x3 line.long 0x00 "CHCTRL21,A/D Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x60++0x3 line.long 0x00 "CHCTRL24,A/D Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x64++0x3 line.long 0x00 "CHCTRL25,A/D Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x68++0x3 line.long 0x00 "CHCTRL26,A/D Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x70++0x3 line.long 0x00 "CHCTRL28,A/D Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x74++0x3 line.long 0x00 "CHCTRL29,A/D Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x78++0x3 line.long 0x00 "CHCTRL30,A/D Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x7C++0x3 line.long 0x00 "CHCTRL31,A/D Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x80++0x3 line.long 0x00 "CHCTRL32,A/D Channel Control Register 32" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0x9C++0x3 line.long 0x00 "CHCTRL39,A/D Channel Control Register 39" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA0++0x3 line.long 0x00 "CHCTRL40,A/D Channel Control Register 40" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA4++0x3 line.long 0x00 "CHCTRL41,A/D Channel Control Register 41" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xA8++0x3 line.long 0x00 "CHCTRL42,A/D Channel Control Register 42" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xAC++0x3 line.long 0x00 "CHCTRL43,A/D Channel Control Register 43" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB0++0x3 line.long 0x00 "CHCTRL44,A/D Channel Control Register 44" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB4++0x3 line.long 0x00 "CHCTRL45,A/D Channel Control Register 45" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xB8++0x3 line.long 0x00 "CHCTRL46,A/D Channel Control Register 46" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xBC++0x3 line.long 0x00 "CHCTRL47,A/D Channel Control Register 47" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC4++0x3 line.long 0x00 "CHCTRL49,A/D Channel Control Register 49" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xC8++0x3 line.long 0x00 "CHCTRL50,A/D Channel Control Register 50" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xCC++0x3 line.long 0x00 "CHCTRL51,A/D Channel Control Register 51" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD0++0x3 line.long 0x00 "CHCTRL52,A/D Channel Control Register 52" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD4++0x3 line.long 0x00 "CHCTRL53,A/D Channel Control Register 53" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xD8++0x3 line.long 0x00 "CHCTRL54,A/D Channel Control Register 54" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xDC++0x3 line.long 0x00 "CHCTRL55,A/D Channel Control Register 55" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE0++0x3 line.long 0x00 "CHCTRL56,A/D Channel Control Register 56" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE4++0x3 line.long 0x00 "CHCTRL57,A/D Channel Control Register 57" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xE8++0x3 line.long 0x00 "CHCTRL58,A/D Channel Control Register 58" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xEC++0x3 line.long 0x00 "CHCTRL59,A/D Channel Control Register 59" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF0++0x3 line.long 0x00 "CHCTRL60,A/D Channel Control Register 60" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF4++0x3 line.long 0x00 "CHCTRL61,A/D Channel Control Register 61" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xF8++0x3 line.long 0x00 "CHCTRL62,A/D Channel Control Register 62" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,,,,,AN8,AN9,,,AN12,AN13,,,AN16,AN17,AN18,,,AN21,,,AN24,,,,,,,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" else group.long 0xFC++0x3 line.long 0x00 "CHCTRL63,A/D Channel Control Register 63" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No effect,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "No effect,Set" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bit" "0,1,2,3" textline " " bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/Restart/Stop select bit" "Stop,Resume,Reset," bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" textline " " bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "Software,Software/Hardware,By conversion,Idle trigger" bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bit" ",,,,AN4,AN5,AN6,AN7,AN8,AN9,AN10,AN11,AN12,AN13,AN14,AN15,AN16,AN17,AN18,,,AN21,,,AN24,AN25,AN26,,AN28,AN29,AN30,AN31,AN32,,,,,,,AN39,AN40,AN41,AN42,AN43,AN44,AN45,AN46,AN47,,AN49,AN50,AN51,AN52,AN53,AN54,AN55,AN56,AN57,AN58,AN59,AN60,AN61,AN62,AN63" endif tree.end tree "CHSTAT 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x108++0x1 line.word 0x00 "CHSTAT4,A/D Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x10A++0x1 line.word 0x00 "CHSTAT5,A/D Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x10C++0x1 line.word 0x00 "CHSTAT6,A/D Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x10E++0x1 line.word 0x00 "CHSTAT7,A/D Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x110++0x1 line.word 0x00 "CHSTAT8,A/D Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x112++0x1 line.word 0x00 "CHSTAT9,A/D Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x114++0x1 line.word 0x00 "CHSTAT10,A/D Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x116++0x1 line.word 0x00 "CHSTAT11,A/D Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x118++0x1 line.word 0x00 "CHSTAT12,A/D Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x11A++0x1 line.word 0x00 "CHSTAT13,A/D Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x11C++0x1 line.word 0x00 "CHSTAT14,A/D Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x11E++0x1 line.word 0x00 "CHSTAT15,A/D Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x120++0x1 line.word 0x00 "CHSTAT16,A/D Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x122++0x1 line.word 0x00 "CHSTAT17,A/D Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x124++0x1 line.word 0x00 "CHSTAT18,A/D Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x12A++0x1 line.word 0x00 "CHSTAT21,A/D Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x130++0x1 line.word 0x00 "CHSTAT24,A/D Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x132++0x1 line.word 0x00 "CHSTAT25,A/D Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x134++0x1 line.word 0x00 "CHSTAT26,A/D Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x138++0x1 line.word 0x00 "CHSTAT28,A/D Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x13A++0x1 line.word 0x00 "CHSTAT29,A/D Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x13C++0x1 line.word 0x00 "CHSTAT30,A/D Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x13E++0x1 line.word 0x00 "CHSTAT31,A/D Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x140++0x1 line.word 0x00 "CHSTAT32,A/D Channel Status Register 32" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x14E++0x1 line.word 0x00 "CHSTAT39,A/D Channel Status Register 39" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x150++0x1 line.word 0x00 "CHSTAT40,A/D Channel Status Register 40" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x152++0x1 line.word 0x00 "CHSTAT41,A/D Channel Status Register 41" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x154++0x1 line.word 0x00 "CHSTAT42,A/D Channel Status Register 42" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x156++0x1 line.word 0x00 "CHSTAT43,A/D Channel Status Register 43" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x158++0x1 line.word 0x00 "CHSTAT44,A/D Channel Status Register 44" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15A++0x1 line.word 0x00 "CHSTAT45,A/D Channel Status Register 45" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15C++0x1 line.word 0x00 "CHSTAT46,A/D Channel Status Register 46" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x15E++0x1 line.word 0x00 "CHSTAT47,A/D Channel Status Register 47" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x162++0x1 line.word 0x00 "CHSTAT49,A/D Channel Status Register 49" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x164++0x1 line.word 0x00 "CHSTAT50,A/D Channel Status Register 50" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x166++0x1 line.word 0x00 "CHSTAT51,A/D Channel Status Register 51" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x168++0x1 line.word 0x00 "CHSTAT52,A/D Channel Status Register 52" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16A++0x1 line.word 0x00 "CHSTAT53,A/D Channel Status Register 53" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16C++0x1 line.word 0x00 "CHSTAT54,A/D Channel Status Register 54" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x16E++0x1 line.word 0x00 "CHSTAT55,A/D Channel Status Register 55" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x170++0x1 line.word 0x00 "CHSTAT56,A/D Channel Status Register 56" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x172++0x1 line.word 0x00 "CHSTAT57,A/D Channel Status Register 57" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x174++0x1 line.word 0x00 "CHSTAT58,A/D Channel Status Register 58" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x176++0x1 line.word 0x00 "CHSTAT59,A/D Channel Status Register 59" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x178++0x1 line.word 0x00 "CHSTAT60,A/D Channel Status Register 60" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17A++0x1 line.word 0x00 "CHSTAT61,A/D Channel Status Register 61" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17C++0x1 line.word 0x00 "CHSTAT62,A/D Channel Status Register 62" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" else rgroup.word 0x17E++0x1 line.word 0x00 "CHSTAT63,A/D Channel Status Register 63" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Not detected,Detected" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "Not detected,Detected" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "Not detected,Detected" textline " " bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "Not detected,Detected" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "Not detected,Detected" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not detected,Detected" endif tree.end width 6. tree "CD 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x188++0x1 line.word 0x00 "CD4,A/D Conversion Data Register 4" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x18A++0x1 line.word 0x00 "CD5,A/D Conversion Data Register 5" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x18C++0x1 line.word 0x00 "CD6,A/D Conversion Data Register 6" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x18E++0x1 line.word 0x00 "CD7,A/D Conversion Data Register 7" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x190++0x1 line.word 0x00 "CD8,A/D Conversion Data Register 8" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x192++0x1 line.word 0x00 "CD9,A/D Conversion Data Register 9" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x194++0x1 line.word 0x00 "CD10,A/D Conversion Data Register 10" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x196++0x1 line.word 0x00 "CD11,A/D Conversion Data Register 11" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x198++0x1 line.word 0x00 "CD12,A/D Conversion Data Register 12" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x19A++0x1 line.word 0x00 "CD13,A/D Conversion Data Register 13" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x19C++0x1 line.word 0x00 "CD14,A/D Conversion Data Register 14" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x19E++0x1 line.word 0x00 "CD15,A/D Conversion Data Register 15" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A0++0x1 line.word 0x00 "CD16,A/D Conversion Data Register 16" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A2++0x1 line.word 0x00 "CD17,A/D Conversion Data Register 17" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1A4++0x1 line.word 0x00 "CD18,A/D Conversion Data Register 18" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1AA++0x1 line.word 0x00 "CD21,A/D Conversion Data Register 21" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1B0++0x1 line.word 0x00 "CD24,A/D Conversion Data Register 24" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1B2++0x1 line.word 0x00 "CD25,A/D Conversion Data Register 25" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1B4++0x1 line.word 0x00 "CD26,A/D Conversion Data Register 26" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1B8++0x1 line.word 0x00 "CD28,A/D Conversion Data Register 28" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1BA++0x1 line.word 0x00 "CD29,A/D Conversion Data Register 29" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else rgroup.word 0x1BC++0x1 line.word 0x00 "CD30,A/D Conversion Data Register 30" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1BE++0x1 line.word 0x00 "CD31,A/D Conversion Data Register 31" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1C0++0x1 line.word 0x00 "CD32,A/D Conversion Data Register 32" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1CE++0x1 line.word 0x00 "CD39,A/D Conversion Data Register 39" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D0++0x1 line.word 0x00 "CD40,A/D Conversion Data Register 40" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D2++0x1 line.word 0x00 "CD41,A/D Conversion Data Register 41" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D4++0x1 line.word 0x00 "CD42,A/D Conversion Data Register 42" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D6++0x1 line.word 0x00 "CD43,A/D Conversion Data Register 43" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1D8++0x1 line.word 0x00 "CD44,A/D Conversion Data Register 44" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DA++0x1 line.word 0x00 "CD45,A/D Conversion Data Register 45" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DC++0x1 line.word 0x00 "CD46,A/D Conversion Data Register 46" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1DE++0x1 line.word 0x00 "CD47,A/D Conversion Data Register 47" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E2++0x1 line.word 0x00 "CD49,A/D Conversion Data Register 49" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E4++0x1 line.word 0x00 "CD50,A/D Conversion Data Register 50" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E6++0x1 line.word 0x00 "CD51,A/D Conversion Data Register 51" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1E8++0x1 line.word 0x00 "CD52,A/D Conversion Data Register 52" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EA++0x1 line.word 0x00 "CD53,A/D Conversion Data Register 53" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EC++0x1 line.word 0x00 "CD54,A/D Conversion Data Register 54" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1EE++0x1 line.word 0x00 "CD55,A/D Conversion Data Register 55" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F0++0x1 line.word 0x00 "CD56,A/D Conversion Data Register 56" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F2++0x1 line.word 0x00 "CD57,A/D Conversion Data Register 57" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F4++0x1 line.word 0x00 "CD58,A/D Conversion Data Register 58" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F6++0x1 line.word 0x00 "CD59,A/D Conversion Data Register 59" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1F8++0x1 line.word 0x00 "CD60,A/D Conversion Data Register 60" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FA++0x1 line.word 0x00 "CD61,A/D Conversion Data Register 61" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FC++0x1 line.word 0x00 "CD62,A/D Conversion Data Register 62" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" else rgroup.word 0x1FE++0x1 line.word 0x00 "CD63,A/D Conversion Data Register 63" hexmask.word 0x00 0.--11. 1. " D ,A/D Conversion Data bits" endif tree.end width 10. tree "PCCTRL 0-63" sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x210++0x3 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x214++0x3 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x218++0x3 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x21C++0x3 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x220++0x3 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x224++0x3 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x228++0x3 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x22C++0x3 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x230++0x3 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x234++0x3 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x238++0x3 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x23C++0x3 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x240++0x3 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x244++0x3 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x248++0x3 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x254++0x3 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x260++0x3 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x264++0x3 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x268++0x3 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x270++0x3 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x274++0x3 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else group.long 0x278++0x3 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x27C++0x3 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x280++0x3 line.long 0x00 "PCCTRL32,Pulse Counter Control Register 32" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x29C++0x3 line.long 0x00 "PCCTRL39,Pulse Counter Control Register 39" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A0++0x3 line.long 0x00 "PCCTRL40,Pulse Counter Control Register 40" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A4++0x3 line.long 0x00 "PCCTRL41,Pulse Counter Control Register 41" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2A8++0x3 line.long 0x00 "PCCTRL42,Pulse Counter Control Register 42" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2AC++0x3 line.long 0x00 "PCCTRL43,Pulse Counter Control Register 43" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B0++0x3 line.long 0x00 "PCCTRL44,Pulse Counter Control Register 44" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B4++0x3 line.long 0x00 "PCCTRL45,Pulse Counter Control Register 45" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2B8++0x3 line.long 0x00 "PCCTRL46,Pulse Counter Control Register 46" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2BC++0x3 line.long 0x00 "PCCTRL47,Pulse Counter Control Register 47" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) else endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C4++0x3 line.long 0x00 "PCCTRL49,Pulse Counter Control Register 49" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2C8++0x3 line.long 0x00 "PCCTRL50,Pulse Counter Control Register 50" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2CC++0x3 line.long 0x00 "PCCTRL51,Pulse Counter Control Register 51" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D0++0x3 line.long 0x00 "PCCTRL52,Pulse Counter Control Register 52" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D4++0x3 line.long 0x00 "PCCTRL53,Pulse Counter Control Register 53" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2D8++0x3 line.long 0x00 "PCCTRL54,Pulse Counter Control Register 54" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2DC++0x3 line.long 0x00 "PCCTRL55,Pulse Counter Control Register 55" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E0++0x3 line.long 0x00 "PCCTRL56,Pulse Counter Control Register 56" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E4++0x3 line.long 0x00 "PCCTRL57,Pulse Counter Control Register 57" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2E8++0x3 line.long 0x00 "PCCTRL58,Pulse Counter Control Register 58" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2EC++0x3 line.long 0x00 "PCCTRL59,Pulse Counter Control Register 59" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F0++0x3 line.long 0x00 "PCCTRL60,Pulse Counter Control Register 60" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F4++0x3 line.long 0x00 "PCCTRL61,Pulse Counter Control Register 61" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2F8++0x3 line.long 0x00 "PCCTRL62,Pulse Counter Control Register 62" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" else group.long 0x2FC++0x3 line.long 0x00 "PCCTRL63,Pulse Counter Control Register 63" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload register" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter register" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload register" endif tree.end textline "" width 19. sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" textline " " setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" textline " " bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" textline " " bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" textline " " bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x300++0x3 line.long 0x00 "CDONEIRQ0_set/clr,A/D Conversion done interrupt flag register 0" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[31] ,Conversion done interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Conversion done interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Conversion done interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Conversion done interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Conversion done interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Conversion done interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Conversion done interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Conversion done interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Conversion done interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Conversion done interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Conversion done interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Conversion done interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Conversion done interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Conversion done interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Conversion done interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Conversion done interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Conversion done interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Conversion done interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Conversion done interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Conversion done interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Conversion done interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Conversion done interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Conversion done interrupt flag 4" "Not detected,Detected" group.long 0x304++0x3 line.long 0x00 "CDONEIRQ1_set/clr,A/D Conversion done interrupt flag register 1" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " CDONEIRQ_[63] ,Conversion done interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Conversion done interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Conversion done interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Conversion done interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Conversion done interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Conversion done interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Conversion done interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Conversion done interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Conversion done interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Conversion done interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Conversion done interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Conversion done interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Conversion done interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Conversion done interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Conversion done interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Conversion done interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Conversion done interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Conversion done interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Conversion done interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Conversion done interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Conversion done interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Conversion done interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Conversion done interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Conversion done interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Conversion done interrupt flag 32" "Not detected,Detected" group.long 0x318++0x3 line.long 0x00 "GRPIRQ0_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[31] ,Group interrupted interrupt 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Group interrupted interrupt 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Group interrupted interrupt 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Group interrupted interrupt 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Group interrupted interrupt 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Group interrupted interrupt 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Group interrupted interrupt 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Group interrupted interrupt 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Group interrupted interrupt 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Group interrupted interrupt 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Group interrupted interrupt 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Group interrupted interrupt 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Group interrupted interrupt 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Group interrupted interrupt 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Group interrupted interrupt 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Group interrupted interrupt 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Group interrupted interrupt 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Group interrupted interrupt 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Group interrupted interrupt 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Group interrupted interrupt 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Group interrupted interrupt 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Group interrupted interrupt 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Group interrupted interrupt 4" "Not detected,Detected" group.long 0x31C++0x3 line.long 0x00 "GRPIRQ1_set/clr,Group interrupted interrupt flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " GRPIRQ_[63] ,Group interrupted interrupt 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Group interrupted interrupt 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Group interrupted interrupt 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Group interrupted interrupt 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Group interrupted interrupt 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Group interrupted interrupt 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Group interrupted interrupt 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Group interrupted interrupt 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Group interrupted interrupt 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Group interrupted interrupt 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Group interrupted interrupt 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Group interrupted interrupt 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Group interrupted interrupt 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Group interrupted interrupt 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Group interrupted interrupt 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Group interrupted interrupt 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Group interrupted interrupt 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Group interrupted interrupt 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Group interrupted interrupt 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Group interrupted interrupt 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Group interrupted interrupt 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Group interrupted interrupt 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Group interrupted interrupt 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Group interrupted interrupt 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Group interrupted interrupt 32" "Not detected,Detected" group.long 0x330++0x3 line.long 0x00 "RCIRQ0_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[31] ,Range comparator interrupt flag 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Range comparator interrupt flag 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Range comparator interrupt flag 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Range comparator interrupt flag 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Range comparator interrupt flag 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Range comparator interrupt flag 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Range comparator interrupt flag 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Range comparator interrupt flag 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Range comparator interrupt flag 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Range comparator interrupt flag 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Range comparator interrupt flag 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Range comparator interrupt flag 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Range comparator interrupt flag 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Range comparator interrupt flag 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Range comparator interrupt flag 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Range comparator interrupt flag 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Range comparator interrupt flag 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Range comparator interrupt flag 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Range comparator interrupt flag 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Range comparator interrupt flag 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Range comparator interrupt flag 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Range comparator interrupt flag 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Range comparator interrupt flag 4" "Not detected,Detected" group.long 0x334++0x3 line.long 0x00 "RCIRQ1_set/clr,Range Comparator Interrupt Flag Register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " RCIRQ_[63] ,Range comparator interrupt flag 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Range comparator interrupt flag 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Range comparator interrupt flag 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Range comparator interrupt flag 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Range comparator interrupt flag 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Range comparator interrupt flag 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Range comparator interrupt flag 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Range comparator interrupt flag 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Range comparator interrupt flag 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Range comparator interrupt flag 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Range comparator interrupt flag 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Range comparator interrupt flag 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Range comparator interrupt flag 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Range comparator interrupt flag 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Range comparator interrupt flag 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Range comparator interrupt flag 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Range comparator interrupt flag 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Range comparator interrupt flag 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Range comparator interrupt flag 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Range comparator interrupt flag 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Range comparator interrupt flag 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Range comparator interrupt flag 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Range comparator interrupt flag 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Range comparator interrupt flag 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Range comparator interrupt flag 32" "Not detected,Detected" group.long 0x348++0x3 line.long 0x00 "PCIRQ0_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[31] ,Pulse counter interrupt bit 31" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [30] ,Pulse counter interrupt bit 30" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [29] ,Pulse counter interrupt bit 29" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [28] ,Pulse counter interrupt bit 28" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [26] ,Pulse counter interrupt bit 26" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [25] ,Pulse counter interrupt bit 25" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [24] ,Pulse counter interrupt bit 24" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [21] ,Pulse counter interrupt bit 21" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [18] ,Pulse counter interrupt bit 18" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [17] ,Pulse counter interrupt bit 17" "Not detected,Detected" textline " " setclrfld.long 0x00 16. 0x08 16. 0x10 16. " [16] ,Pulse counter interrupt bit 16" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [15] ,Pulse counter interrupt bit 15" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [14] ,Pulse counter interrupt bit 14" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [13] ,Pulse counter interrupt bit 13" "Not detected,Detected" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [12] ,Pulse counter interrupt bit 12" "Not detected,Detected" textline " " setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [11] ,Pulse counter interrupt bit 11" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [10] ,Pulse counter interrupt bit 10" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [9] ,Pulse counter interrupt bit 9" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [8] ,Pulse counter interrupt bit 8" "Not detected,Detected" setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [7] ,Pulse counter interrupt bit 7" "Not detected,Detected" textline " " setclrfld.long 0x00 6. 0x08 6. 0x10 6. " [6] ,Pulse counter interrupt bit 6" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x10 5. " [5] ,Pulse counter interrupt bit 5" "Not detected,Detected" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " [4] ,Pulse counter interrupt bit 4" "Not detected,Detected" group.long 0x34C++0x3 line.long 0x00 "PCIRQ1_set/clr,Pulse Counter Interrupt Flag register" setclrfld.long 0x00 31. 0x08 31. 0x10 31. " PCIRQ_[63] ,Pulse counter interrupt bit 63" "Not detected,Detected" setclrfld.long 0x00 30. 0x08 30. 0x10 30. " [62] ,Pulse counter interrupt bit 62" "Not detected,Detected" setclrfld.long 0x00 29. 0x08 29. 0x10 29. " [61] ,Pulse counter interrupt bit 61" "Not detected,Detected" setclrfld.long 0x00 28. 0x08 28. 0x10 28. " [60] ,Pulse counter interrupt bit 60" "Not detected,Detected" setclrfld.long 0x00 27. 0x08 27. 0x10 27. " [59] ,Pulse counter interrupt bit 59" "Not detected,Detected" setclrfld.long 0x00 26. 0x08 26. 0x10 26. " [58] ,Pulse counter interrupt bit 58" "Not detected,Detected" textline " " setclrfld.long 0x00 25. 0x08 25. 0x10 25. " [57] ,Pulse counter interrupt bit 57" "Not detected,Detected" setclrfld.long 0x00 24. 0x08 24. 0x10 24. " [56] ,Pulse counter interrupt bit 56" "Not detected,Detected" setclrfld.long 0x00 23. 0x08 23. 0x10 23. " [55] ,Pulse counter interrupt bit 55" "Not detected,Detected" setclrfld.long 0x00 22. 0x08 22. 0x10 22. " [54] ,Pulse counter interrupt bit 54" "Not detected,Detected" setclrfld.long 0x00 21. 0x08 21. 0x10 21. " [53] ,Pulse counter interrupt bit 53" "Not detected,Detected" setclrfld.long 0x00 20. 0x08 20. 0x10 20. " [52] ,Pulse counter interrupt bit 52" "Not detected,Detected" textline " " setclrfld.long 0x00 19. 0x08 19. 0x10 19. " [51] ,Pulse counter interrupt bit 51" "Not detected,Detected" setclrfld.long 0x00 18. 0x08 18. 0x10 18. " [50] ,Pulse counter interrupt bit 50" "Not detected,Detected" setclrfld.long 0x00 17. 0x08 17. 0x10 17. " [49] ,Pulse counter interrupt bit 49" "Not detected,Detected" setclrfld.long 0x00 15. 0x08 15. 0x10 15. " [47] ,Pulse counter interrupt bit 47" "Not detected,Detected" setclrfld.long 0x00 14. 0x08 14. 0x10 14. " [46] ,Pulse counter interrupt bit 46" "Not detected,Detected" setclrfld.long 0x00 13. 0x08 13. 0x10 13. " [45] ,Pulse counter interrupt bit 45" "Not detected,Detected" textline " " setclrfld.long 0x00 12. 0x08 12. 0x10 12. " [44] ,Pulse counter interrupt bit 44" "Not detected,Detected" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " [43] ,Pulse counter interrupt bit 43" "Not detected,Detected" setclrfld.long 0x00 10. 0x08 10. 0x10 10. " [42] ,Pulse counter interrupt bit 42" "Not detected,Detected" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " [41] ,Pulse counter interrupt bit 41" "Not detected,Detected" setclrfld.long 0x00 8. 0x08 8. 0x10 8. " [40] ,Pulse counter interrupt bit 40" "Not detected,Detected" textline " " setclrfld.long 0x00 7. 0x08 7. 0x10 7. " [39] ,Pulse counter interrupt bit 39" "Not detected,Detected" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " [32] ,Pulse counter interrupt bit 32" "Not detected,Detected" rgroup.long 0x360++0x3 line.long 0x00 "TRGST0,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[31] ,A/D channel trigger status flag 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag 28" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag 26" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag 24" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag 21" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag 17" "Not requested,Requested" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag 16" "Not requested,Requested" bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag 9" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag 8" "Not requested,Requested" bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag 7" "Not requested,Requested" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag 6" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag 5" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag 4" "Not requested,Requested" rgroup.long 0x364++0x3 line.long 0x00 "TRGST1,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST_[63] ,A/D channel trigger status flag 63" "Not requested,Requested" bitfld.long 0x00 30. " [62] ,A/D channel trigger status flag 62" "Not requested,Requested" bitfld.long 0x00 29. " [61] ,A/D channel trigger status flag 61" "Not requested,Requested" bitfld.long 0x00 28. " [60] ,A/D channel trigger status flag 60" "Not requested,Requested" bitfld.long 0x00 27. " [59] ,A/D channel trigger status flag 59" "Not requested,Requested" bitfld.long 0x00 26. " [58] ,A/D channel trigger status flag 58" "Not requested,Requested" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger status flag 57" "Not requested,Requested" bitfld.long 0x00 24. " [56] ,A/D channel trigger status flag 56" "Not requested,Requested" bitfld.long 0x00 23. " [55] ,A/D channel trigger status flag 55" "Not requested,Requested" bitfld.long 0x00 22. " [54] ,A/D channel trigger status flag 54" "Not requested,Requested" bitfld.long 0x00 21. " [53] ,A/D channel trigger status flag 53" "Not requested,Requested" bitfld.long 0x00 20. " [52] ,A/D channel trigger status flag 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger status flag 51" "Not requested,Requested" bitfld.long 0x00 18. " [50] ,A/D channel trigger status flag 50" "Not requested,Requested" bitfld.long 0x00 17. " [49] ,A/D channel trigger status flag 49" "Not requested,Requested" bitfld.long 0x00 15. " [47] ,A/D channel trigger status flag 47" "Not requested,Requested" bitfld.long 0x00 14. " [46] ,A/D channel trigger status flag 46" "Not requested,Requested" bitfld.long 0x00 13. " [45] ,A/D channel trigger status flag 45" "Not requested,Requested" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger status flag 44" "Not requested,Requested" bitfld.long 0x00 11. " [43] ,A/D channel trigger status flag 43" "Not requested,Requested" bitfld.long 0x00 10. " [42] ,A/D channel trigger status flag 42" "Not requested,Requested" bitfld.long 0x00 9. " [41] ,A/D channel trigger status flag 41" "Not requested,Requested" bitfld.long 0x00 8. " [40] ,A/D channel trigger status flag 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger status flag 39" "Not requested,Requested" bitfld.long 0x00 0. " [32] ,A/D channel trigger status flag 32" "Not requested,Requested" wgroup.long 0x368++0x3 line.long 0x00 "TRGCL0,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[31] ,Trigger status clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger status clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger status clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger status clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger status clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger status clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger status clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger status clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger status clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger status clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger status clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger status clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger status clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger status clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger status clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger status clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger status clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger status clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger status clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger status clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger status clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger status clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger status clear bit 4" "No effect,Clear" wgroup.long 0x36C++0x3 line.long 0x00 "TRGCL1,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL_[63] ,Trigger status clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger status clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger status clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger status clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger status clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger status clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger status clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger status clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger status clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger status clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger status clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger status clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger status clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger status clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger status clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger status clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger status clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger status clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger status clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger status clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger status clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger status clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger status clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger status clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger status clear bit 32" "No effect,Clear" rgroup.long 0x378++0x3 line.long 0x00 "TRGOR0,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[31] ,A/D channel trigger overrun flag 31" "Not occurred,Occurred" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "Not occurred,Occurred" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "Not occurred,Occurred" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "Not occurred,Occurred" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "Not occurred,Occurred" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "Not occurred,Occurred" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "Not occurred,Occurred" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "Not occurred,Occurred" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "Not occurred,Occurred" bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "Not occurred,Occurred" bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "Not occurred,Occurred" rgroup.long 0x37C++0x3 line.long 0x00 "TRGOR1,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR_[63] ,A/D channel trigger overrun flag 63" "Not occurred,Occurred" bitfld.long 0x00 30. " [62] ,A/D channel trigger overrun flag 62" "Not occurred,Occurred" bitfld.long 0x00 29. " [61] ,A/D channel trigger overrun flag 61" "Not occurred,Occurred" bitfld.long 0x00 28. " [60] ,A/D channel trigger overrun flag 60" "Not occurred,Occurred" bitfld.long 0x00 27. " [59] ,A/D channel trigger overrun flag 59" "Not occurred,Occurred" bitfld.long 0x00 26. " [58] ,A/D channel trigger overrun flag 58" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [57] ,A/D channel trigger overrun flag 57" "Not occurred,Occurred" bitfld.long 0x00 24. " [56] ,A/D channel trigger overrun flag 56" "Not occurred,Occurred" bitfld.long 0x00 23. " [55] ,A/D channel trigger overrun flag 55" "Not occurred,Occurred" bitfld.long 0x00 22. " [54] ,A/D channel trigger overrun flag 54" "Not occurred,Occurred" bitfld.long 0x00 21. " [53] ,A/D channel trigger overrun flag 53" "Not occurred,Occurred" bitfld.long 0x00 20. " [52] ,A/D channel trigger overrun flag 52" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " [51] ,A/D channel trigger overrun flag 51" "Not occurred,Occurred" bitfld.long 0x00 18. " [50] ,A/D channel trigger overrun flag 50" "Not occurred,Occurred" bitfld.long 0x00 17. " [49] ,A/D channel trigger overrun flag 49" "Not occurred,Occurred" bitfld.long 0x00 15. " [47] ,A/D channel trigger overrun flag 47" "Not occurred,Occurred" bitfld.long 0x00 14. " [46] ,A/D channel trigger overrun flag 46" "Not occurred,Occurred" bitfld.long 0x00 13. " [45] ,A/D channel trigger overrun flag 45" "Not occurred,Occurred" textline " " bitfld.long 0x00 12. " [44] ,A/D channel trigger overrun flag 44" "Not occurred,Occurred" bitfld.long 0x00 11. " [43] ,A/D channel trigger overrun flag 43" "Not occurred,Occurred" bitfld.long 0x00 10. " [42] ,A/D channel trigger overrun flag 42" "Not occurred,Occurred" bitfld.long 0x00 9. " [41] ,A/D channel trigger overrun flag 41" "Not occurred,Occurred" bitfld.long 0x00 8. " [40] ,A/D channel trigger overrun flag 40" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " [39] ,A/D channel trigger overrun flag 39" "Not occurred,Occurred" bitfld.long 0x00 0. " [32] ,A/D channel trigger overrun flag 32" "Not occurred,Occurred" wgroup.long 0x380++0x3 line.long 0x00 "TRGORC0,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[31] ,Trigger overrun clear bit 31" "No effect,Clear" bitfld.long 0x00 30. " [30] ,Trigger overrun clear bit 30" "No effect,Clear" bitfld.long 0x00 29. " [29] ,Trigger overrun clear bit 29" "No effect,Clear" bitfld.long 0x00 28. " [28] ,Trigger overrun clear bit 28" "No effect,Clear" bitfld.long 0x00 26. " [26] ,Trigger overrun clear bit 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " [25] ,Trigger overrun clear bit 25" "No effect,Clear" bitfld.long 0x00 24. " [24] ,Trigger overrun clear bit 24" "No effect,Clear" bitfld.long 0x00 21. " [21] ,Trigger overrun clear bit 21" "No effect,Clear" bitfld.long 0x00 18. " [18] ,Trigger overrun clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,Trigger overrun clear bit 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " [16] ,Trigger overrun clear bit 16" "No effect,Clear" bitfld.long 0x00 15. " [15] ,Trigger overrun clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,Trigger overrun clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,Trigger overrun clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,Trigger overrun clear bit 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " [11] ,Trigger overrun clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,Trigger overrun clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,Trigger overrun clear bit 9" "No effect,Clear" bitfld.long 0x00 8. " [8] ,Trigger overrun clear bit 8" "No effect,Clear" bitfld.long 0x00 7. " [7] ,Trigger overrun clear bit 7" "No effect,Clear" textline " " bitfld.long 0x00 6. " [6] ,Trigger overrun clear bit 6" "No effect,Clear" bitfld.long 0x00 5. " [5] ,Trigger overrun clear bit 5" "No effect,Clear" bitfld.long 0x00 4. " [4] ,Trigger overrun clear bit 4" "No effect,Clear" wgroup.long 0x384++0x3 line.long 0x00 "TRGORC1,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC_[63] ,Trigger overrun clear bit 63" "No effect,Clear" bitfld.long 0x00 30. " [62] ,Trigger overrun clear bit 62" "No effect,Clear" bitfld.long 0x00 29. " [61] ,Trigger overrun clear bit 61" "No effect,Clear" bitfld.long 0x00 28. " [60] ,Trigger overrun clear bit 60" "No effect,Clear" bitfld.long 0x00 27. " [59] ,Trigger overrun clear bit 59" "No effect,Clear" bitfld.long 0x00 26. " [58] ,Trigger overrun clear bit 58" "No effect,Clear" textline " " bitfld.long 0x00 25. " [57] ,Trigger overrun clear bit 57" "No effect,Clear" bitfld.long 0x00 24. " [56] ,Trigger overrun clear bit 56" "No effect,Clear" bitfld.long 0x00 23. " [55] ,Trigger overrun clear bit 55" "No effect,Clear" bitfld.long 0x00 22. " [54] ,Trigger overrun clear bit 54" "No effect,Clear" bitfld.long 0x00 21. " [53] ,Trigger overrun clear bit 53" "No effect,Clear" bitfld.long 0x00 20. " [52] ,Trigger overrun clear bit 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " [51] ,Trigger overrun clear bit 51" "No effect,Clear" bitfld.long 0x00 18. " [50] ,Trigger overrun clear bit 50" "No effect,Clear" bitfld.long 0x00 17. " [49] ,Trigger overrun clear bit 49" "No effect,Clear" bitfld.long 0x00 15. " [47] ,Trigger overrun clear bit 47" "No effect,Clear" bitfld.long 0x00 14. " [46] ,Trigger overrun clear bit 46" "No effect,Clear" bitfld.long 0x00 13. " [45] ,Trigger overrun clear bit 45" "No effect,Clear" textline " " bitfld.long 0x00 12. " [44] ,Trigger overrun clear bit 44" "No effect,Clear" bitfld.long 0x00 11. " [43] ,Trigger overrun clear bit 43" "No effect,Clear" bitfld.long 0x00 10. " [42] ,Trigger overrun clear bit 42" "No effect,Clear" bitfld.long 0x00 9. " [41] ,Trigger overrun clear bit 41" "No effect,Clear" bitfld.long 0x00 8. " [40] ,Trigger overrun clear bit 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " [39] ,Trigger overrun clear bit 39" "No effect,Clear" bitfld.long 0x00 0. " [32] ,Trigger overrun clear bit 32" "No effect,Clear" rgroup.long 0x370++0x3 line.long 0x00 "RCOTF0,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[31] ,Range comparator over threshold flag 31" "Less or equal,Above" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less or equal,Above" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less or equal,Above" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less or equal,Above" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less or equal,Above" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less or equal,Above" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less or equal,Above" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less or equal,Above" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less or equal,Above" textline " " bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less or equal,Above" bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less or equal,Above" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less or equal,Above" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less or equal,Above" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less or equal,Above" textline " " bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less or equal,Above" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less or equal,Above" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less or equal,Above" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less or equal,Above" bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less or equal,Above" textline " " bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less or equal,Above" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less or equal,Above" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less or equal,Above" rgroup.long 0x374++0x3 line.long 0x00 "RCOTF1,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF_[63] ,Range comparator over threshold flag 63" "Less or equal,Above" bitfld.long 0x00 30. " [62] ,Range comparator over threshold flag 62" "Less or equal,Above" bitfld.long 0x00 29. " [61] ,Range comparator over threshold flag 61" "Less or equal,Above" bitfld.long 0x00 28. " [60] ,Range comparator over threshold flag 60" "Less or equal,Above" bitfld.long 0x00 27. " [59] ,Range comparator over threshold flag 59" "Less or equal,Above" bitfld.long 0x00 26. " [58] ,Range comparator over threshold flag 58" "Less or equal,Above" textline " " bitfld.long 0x00 25. " [57] ,Range comparator over threshold flag 57" "Less or equal,Above" bitfld.long 0x00 24. " [56] ,Range comparator over threshold flag 56" "Less or equal,Above" bitfld.long 0x00 23. " [55] ,Range comparator over threshold flag 55" "Less or equal,Above" bitfld.long 0x00 22. " [54] ,Range comparator over threshold flag 54" "Less or equal,Above" bitfld.long 0x00 21. " [53] ,Range comparator over threshold flag 53" "Less or equal,Above" bitfld.long 0x00 20. " [52] ,Range comparator over threshold flag 52" "Less or equal,Above" textline " " bitfld.long 0x00 19. " [51] ,Range comparator over threshold flag 51" "Less or equal,Above" bitfld.long 0x00 18. " [50] ,Range comparator over threshold flag 50" "Less or equal,Above" bitfld.long 0x00 17. " [49] ,Range comparator over threshold flag 49" "Less or equal,Above" bitfld.long 0x00 15. " [47] ,Range comparator over threshold flag 47" "Less or equal,Above" bitfld.long 0x00 14. " [46] ,Range comparator over threshold flag 46" "Less or equal,Above" bitfld.long 0x00 13. " [45] ,Range comparator over threshold flag 45" "Less or equal,Above" textline " " bitfld.long 0x00 12. " [44] ,Range comparator over threshold flag 44" "Less or equal,Above" bitfld.long 0x00 11. " [43] ,Range comparator over threshold flag 43" "Less or equal,Above" bitfld.long 0x00 10. " [42] ,Range comparator over threshold flag 42" "Less or equal,Above" bitfld.long 0x00 9. " [41] ,Range comparator over threshold flag 41" "Less or equal,Above" bitfld.long 0x00 8. " [40] ,Range comparator over threshold flag 40" "Less or equal,Above" textline " " bitfld.long 0x00 7. " [39] ,Range comparator over threshold flag 39" "Less or equal,Above" bitfld.long 0x00 0. " [32] ,Range comparator over threshold flag 32" "Less or equal,Above" group.word 0x388++0x1 line.word 0x00 "CDDS0,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38A++0x1 line.word 0x00 "CDDS1,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38C++0x1 line.word 0x00 "CDDS2,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x38E++0x1 line.word 0x00 "CDDS3,Conversion Done DMA Select Register" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of the logical channel selected for conversion" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.word 0x390++0xF line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,A/D converter resumption time setting bits" line.word 0x04 "ST0,A/D converter sampling time setting register" line.word 0x06 "ST1,A/D converter sampling time setting register" line.word 0x08 "ST2,A/D converter sampling time setting register" line.word 0x0A "ST3,A/D converter sampling time setting register" line.word 0x0C "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x0C 0.--7. 1. " OCV ,Offset compensation value" line.word 0x0E "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x0E 0.--4. " GCV ,Gain Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0400+0x3A0)&0x10)==0x00) group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,10-bit,12-bit,8-bit" else group.word 0x3A0++0x1 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "Idle,Not idle" bitfld.word 0x00 6. " FSTP ,Forced stop" "No effect,Forced" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8-bit,12-bit" textline " " bitfld.word 0x00 4. " FSMD ,Forced stop mode" "Disabled,Enabled" bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " RES ,Resolution of A/D conversion" "12-bit,12-bit,10-bit,8-bit" endif sif (cpuis("S6J331?H?")||cpuis("S6J332?H?")||cpuis("S6J333?H?")||cpuis("S6J334?H?")) rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,,,,,8,9,,,12,13,,,16,17,18,,,21,,,24,,,,,,,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.word 0x3A2++0x1 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not active,Active" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" ",,,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,,,21,,,24,25,26,,28,29,30,31,32,,,,,,,39,40,41,42,43,44,45,46,47,,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B0++0x00 hide.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BA++0x00 hide.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BC++0x00 hide.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3BE++0x00 hide.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOL ,Range comparator lower threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B1++0x00 hide.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" else group.byte 0x3B1++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B2++0x00 hide.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" else group.byte 0x3B2++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B3++0x00 hide.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" else group.byte 0x3B3++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B4++0x00 hide.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" else group.byte 0x3B4++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B5++0x00 hide.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" else group.byte 0x3B5++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B6++0x00 hide.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" else group.byte 0x3B6++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B7++0x00 hide.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" else group.byte 0x3B7++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) hgroup.byte 0x3B8++0x00 hide.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" else group.byte 0x3B8++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" hexmask.byte 0x00 0.--7. 1. " RCOH ,Range comparator upper threshold value" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F0++0x1 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F0++0x00 hide.byte 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F2++0x1 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F2++0x00 hide.byte 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F4++0x1 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F4++0x00 hide.byte 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F6++0x1 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F6++0x00 hide.byte 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3F8++0x1 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3F8++0x00 hide.byte 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FA++0x1 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FA++0x00 hide.byte 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FC++0x1 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FC++0x00 hide.byte 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3FE++0x1 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" else hgroup.byte 0x3FE++0x00 hide.byte 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D0++0x1 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D0++0x01 hide.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D2++0x1 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D2++0x01 hide.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D4++0x1 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D4++0x01 hide.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D6++0x1 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D6++0x01 hide.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3D8++0x1 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3D8++0x01 hide.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DA++0x1 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DA++0x01 hide.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DC++0x1 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DC++0x01 hide.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" endif if ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x20) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x21) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x22) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x23)==0x23) group.word 0x3DE++0x1 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" else hgroup.word 0x3DE++0x01 hide.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" endif width 0xB tree.end tree.end endif sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "PWU (PARTIAL WAKEUP CONTROL)" base ad:0xB48C0800 width 6. group.byte 0x00++0x01 line.byte 0x00 "PWUC,PWU Control Register" bitfld.byte 0x00 7. " PWUE ,PWU mode enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " ADSTS ,A/D conversion start time setting bits" line.byte 0x01 "ADTC,A/D Conversion Request Trigger Control Register" bitfld.byte 0x01 7. " ADHWTS ,A/D conversion Hardware Trigger Select bit" "Other,PWU_ADT" bitfld.byte 0x01 0.--4. " ADSTCH ,A/D conversion start channel setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end endif sif (!cpuis("S6J335*")) tree.open "SMC (STEPPER MOTOR CONTROLER)" tree "SMC0" base ad:0xB48C4000 width 13. sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") if (((per.w(ad:0xB48C4000))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC0_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC0_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif elif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x00++0x01 line.word 0x00 "SMC0_PWC,PWM Control Register" bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else if (((per.w(ad:0xB48C4000))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC0_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC0_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4000))&0x04)==0x04) if (((per.w(ad:0xB48C4000+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC0_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC0_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC0_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC0_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" endif else if (((per.w(ad:0xB48C4000+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC0_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC0_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC0_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC0_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif else if (((per.w(ad:0xB48C4000))&0x04)==0x04) group.word 0x02++0x03 line.word 0x00 "SMC0_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC0_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC0_PWC1,PWM1 Compare Register" hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC0_PWC2,PWM2 Compare Register" hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.word 0x06++0x01 line.word 0x00 "SMC0_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" elif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4000+0x06))&0x4000)==0x4000) group.word 0x06++0x01 line.word 0x00 "SMC0_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" else group.word 0x06++0x01 line.word 0x00 "SMC0_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" endif else group.word 0x06++0x01 line.word 0x00 "SMC0_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7" endif group.word 0x08++0x03 line.word 0x00 "SMC0_PWSS,PWM Selection Set Register" bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set" line.word 0x02 "SMC0_PTRGDL,SMC Trigger Delay Register" hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits" sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB48C4000))&0x180)==0x00) group.word 0x0C++0x01 line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4000))&0x180)==0x80) group.word 0x0C++0x01 line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4000))&0x180)==0x100) group.word 0x0C++0x01 line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4000))&0x180)==0x180) group.word 0x0C++0x01 line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" endif endif width 0x0B tree.end tree "SMC1" base ad:0xB48C4400 width 13. sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") if (((per.w(ad:0xB48C4400))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC1_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC1_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif elif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x00++0x01 line.word 0x00 "SMC1_PWC,PWM Control Register" bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else if (((per.w(ad:0xB48C4400))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC1_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC1_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4400))&0x04)==0x04) if (((per.w(ad:0xB48C4400+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC1_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC1_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC1_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC1_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" endif else if (((per.w(ad:0xB48C4400+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC1_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC1_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC1_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC1_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif else if (((per.w(ad:0xB48C4400))&0x04)==0x04) group.word 0x02++0x03 line.word 0x00 "SMC1_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC1_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC1_PWC1,PWM1 Compare Register" hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC1_PWC2,PWM2 Compare Register" hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.word 0x06++0x01 line.word 0x00 "SMC1_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" elif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4400+0x06))&0x4000)==0x4000) group.word 0x06++0x01 line.word 0x00 "SMC1_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" else group.word 0x06++0x01 line.word 0x00 "SMC1_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" endif else group.word 0x06++0x01 line.word 0x00 "SMC1_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7" endif group.word 0x08++0x03 line.word 0x00 "SMC1_PWSS,PWM Selection Set Register" bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set" line.word 0x02 "SMC1_PTRGDL,SMC Trigger Delay Register" hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits" sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB48C4400))&0x180)==0x00) group.word 0x0C++0x01 line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4400))&0x180)==0x80) group.word 0x0C++0x01 line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4400))&0x180)==0x100) group.word 0x0C++0x01 line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4400))&0x180)==0x180) group.word 0x0C++0x01 line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" endif endif width 0x0B tree.end tree "SMC2" base ad:0xB48C4800 width 13. sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") if (((per.w(ad:0xB48C4800))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC2_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC2_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif elif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x00++0x01 line.word 0x00 "SMC2_PWC,PWM Control Register" bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else if (((per.w(ad:0xB48C4800))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC2_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC2_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4800))&0x04)==0x04) if (((per.w(ad:0xB48C4800+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC2_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC2_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC2_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC2_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" endif else if (((per.w(ad:0xB48C4800+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC2_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC2_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC2_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC2_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif else if (((per.w(ad:0xB48C4800))&0x04)==0x04) group.word 0x02++0x03 line.word 0x00 "SMC2_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC2_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC2_PWC1,PWM1 Compare Register" hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC2_PWC2,PWM2 Compare Register" hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.word 0x06++0x01 line.word 0x00 "SMC2_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" elif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4800+0x06))&0x4000)==0x4000) group.word 0x06++0x01 line.word 0x00 "SMC2_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" else group.word 0x06++0x01 line.word 0x00 "SMC2_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" endif else group.word 0x06++0x01 line.word 0x00 "SMC2_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7" endif group.word 0x08++0x03 line.word 0x00 "SMC2_PWSS,PWM Selection Set Register" bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set" line.word 0x02 "SMC2_PTRGDL,SMC Trigger Delay Register" hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits" sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB48C4800))&0x180)==0x00) group.word 0x0C++0x01 line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4800))&0x180)==0x80) group.word 0x0C++0x01 line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4800))&0x180)==0x100) group.word 0x0C++0x01 line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4800))&0x180)==0x180) group.word 0x0C++0x01 line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" endif endif width 0x0B tree.end tree "SMC3" base ad:0xB48C4C00 width 13. sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") if (((per.w(ad:0xB48C4C00))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC3_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC3_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif elif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x00++0x01 line.word 0x00 "SMC3_PWC,PWM Control Register" bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else if (((per.w(ad:0xB48C4C00))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC3_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC3_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4C00))&0x04)==0x04) if (((per.w(ad:0xB48C4C00+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC3_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC3_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC3_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC3_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" endif else if (((per.w(ad:0xB48C4C00+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC3_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC3_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC3_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC3_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif else if (((per.w(ad:0xB48C4C00))&0x04)==0x04) group.word 0x02++0x03 line.word 0x00 "SMC3_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC3_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC3_PWC1,PWM1 Compare Register" hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC3_PWC2,PWM2 Compare Register" hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.word 0x06++0x01 line.word 0x00 "SMC3_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" elif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C4C00+0x06))&0x4000)==0x4000) group.word 0x06++0x01 line.word 0x00 "SMC3_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" else group.word 0x06++0x01 line.word 0x00 "SMC3_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" endif else group.word 0x06++0x01 line.word 0x00 "SMC3_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7" endif group.word 0x08++0x03 line.word 0x00 "SMC3_PWSS,PWM Selection Set Register" bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set" line.word 0x02 "SMC3_PTRGDL,SMC Trigger Delay Register" hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits" sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB48C4C00))&0x180)==0x00) group.word 0x0C++0x01 line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4C00))&0x180)==0x80) group.word 0x0C++0x01 line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4C00))&0x180)==0x100) group.word 0x0C++0x01 line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C4C00))&0x180)==0x180) group.word 0x0C++0x01 line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" endif endif width 0x0B tree.end tree "SMC4" base ad:0xB48C5000 width 13. sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") if (((per.w(ad:0xB48C5000))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC4_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC4_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif elif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x00++0x01 line.word 0x00 "SMC4_PWC,PWM Control Register" bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else if (((per.w(ad:0xB48C5000))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC4_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC4_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C5000))&0x04)==0x04) if (((per.w(ad:0xB48C5000+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC4_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC4_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC4_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC4_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" endif else if (((per.w(ad:0xB48C5000+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC4_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC4_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC4_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC4_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif else if (((per.w(ad:0xB48C5000))&0x04)==0x04) group.word 0x02++0x03 line.word 0x00 "SMC4_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC4_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC4_PWC1,PWM1 Compare Register" hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC4_PWC2,PWM2 Compare Register" hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.word 0x06++0x01 line.word 0x00 "SMC4_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" elif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C5000+0x06))&0x4000)==0x4000) group.word 0x06++0x01 line.word 0x00 "SMC4_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" else group.word 0x06++0x01 line.word 0x00 "SMC4_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" endif else group.word 0x06++0x01 line.word 0x00 "SMC4_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7" endif group.word 0x08++0x03 line.word 0x00 "SMC4_PWSS,PWM Selection Set Register" bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set" line.word 0x02 "SMC4_PTRGDL,SMC Trigger Delay Register" hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits" sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB48C5000))&0x180)==0x00) group.word 0x0C++0x01 line.word 0x00 "SMC4_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C5000))&0x180)==0x80) group.word 0x0C++0x01 line.word 0x00 "SMC4_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C5000))&0x180)==0x100) group.word 0x0C++0x01 line.word 0x00 "SMC4_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C5000))&0x180)==0x180) group.word 0x0C++0x01 line.word 0x00 "SMC4_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" endif endif width 0x0B tree.end tree "SMC5" base ad:0xB48C5400 width 13. sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") if (((per.w(ad:0xB48C5400))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC5_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC5_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif elif cpuis("s6j336*")||cpuis("s6j337*") group.word 0x00++0x01 line.word 0x00 "SMC5_PWC,PWM Control Register" bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else if (((per.w(ad:0xB48C5400))&0x200)==0x200) group.word 0x00++0x01 line.word 0x00 "SMC5_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" else group.word 0x00++0x01 line.word 0x00 "SMC5_PWC,PWM Control Register" bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1" bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3" bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16" newline bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit" endif endif sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C5400))&0x04)==0x04) if (((per.w(ad:0xB48C5400+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC5_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC5_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC5_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC5_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" endif else if (((per.w(ad:0xB48C5400+0x06))&0x4000)==0x4000) rgroup.word 0x02++0x03 line.word 0x00 "SMC5_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC5_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC5_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC5_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif else if (((per.w(ad:0xB48C5400))&0x04)==0x04) group.word 0x02++0x03 line.word 0x00 "SMC5_PWC1,PWM1 Compare Register" hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC5_PWC2,PWM2 Compare Register" hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value" else group.word 0x02++0x03 line.word 0x00 "SMC5_PWC1,PWM1 Compare Register" hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value" line.word 0x02 "SMC5_PWC2,PWM2 Compare Register" hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value" endif endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.word 0x06++0x01 line.word 0x00 "SMC5_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" elif cpuis("s6j336*")||cpuis("s6j337*") if (((per.w(ad:0xB48C5400+0x06))&0x4000)==0x4000) group.word 0x06++0x01 line.word 0x00 "SMC5_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" else group.word 0x06++0x01 line.word 0x00 "SMC5_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z" endif else group.word 0x06++0x01 line.word 0x00 "SMC5_PWS,PWM Selection Register" bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled" bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7" newline bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7" endif group.word 0x08++0x03 line.word 0x00 "SMC5_PWSS,PWM Selection Set Register" bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set" line.word 0x02 "SMC5_PTRGDL,SMC Trigger Delay Register" hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits" sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB48C5400))&0x180)==0x00) group.word 0x0C++0x01 line.word 0x00 "SMC5_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C5400))&0x180)==0x80) group.word 0x0C++0x01 line.word 0x00 "SMC5_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C5400))&0x180)==0x100) group.word 0x0C++0x01 line.word 0x00 "SMC5_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" elif (((per.w(ad:0xB48C5400))&0x180)==0x180) group.word 0x0C++0x01 line.word 0x00 "SMC5_ZPD,Zero_Position Detection Register" bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32" bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8" newline bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode" bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded" endif endif width 0x0B tree.end tree.end endif sif (!cpuis("S6J335*")) tree "SMCTG (TRIGGER CONFIGURATION OF STEPPER MOTOR CONTROLER)" base ad:0xB48C5800 width 14. group.word 0x00++0x01 line.word 0x00 "SMCTG0_PTRGS,SMC Trigger Selection Register" bitfld.word 0x00 13. " S25 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled" bitfld.word 0x00 12. " S24 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled" bitfld.word 0x00 11. " S23 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled" newline bitfld.word 0x00 10. " S22 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled" bitfld.word 0x00 9. " S21 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled" bitfld.word 0x00 8. " S20 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled" newline bitfld.word 0x00 5. " S15 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled" bitfld.word 0x00 4. " S14 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled" bitfld.word 0x00 3. " S13 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled" newline bitfld.word 0x00 2. " S12 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled" bitfld.word 0x00 1. " S11 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled" bitfld.word 0x00 0. " S10 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled" wgroup.word 0x02++0x01 line.word 0x00 "SMCTG0_PTRG,SMC Trigger Register" bitfld.word 0x00 1. " TR2 ,SMC trigger 2" "No effect,Select" bitfld.word 0x00 0. " TR1 ,SMC trigger 1" "No effect,Select" width 0x0B tree.end endif sif (!cpuis("S6J335*")) tree.open "SG (SOUND GENERATOR)" tree "SG0" base ad:0xB4840000 width 12. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.word 0x02++0x01 line.word 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" else group.byte 0x02++0x00 line.byte 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" endif sif !cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840000))&0x800)==0x000)&&(((per.w(ad:0xB4840000+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x01)==0x01) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif else if (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840000))&0x800)==0x000)&&(((per.w(ad:0xB4840000+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x201)==(0x01||0x200)) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif endif group.word 0x06++0x01 line.word 0x00 "SGAR,Amplitude Data Register" group.byte 0x05++0x00 line.byte 0x00 "SGFR,Frequency Data Register" group.byte 0x04++0x00 line.byte 0x00 "SGNR,Tone Output Number Register" group.byte 0x0B++0x00 line.byte 0x00 "SGTCR,Time Cycle Register" group.byte 0x0A++0x00 line.byte 0x00 "SSGIDR,Increase And Decrease Data Register" group.word 0x08++0x01 line.word 0x00 "SGPCR,PWM Cycle Data Register" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x0C++0x00 line.byte 0x00 "SGEFR,Extended Frequency Data Register" wgroup.long 0x10++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x14++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x10++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" endif width 0x0B tree.end tree "SG1" base ad:0xB4840400 width 12. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.word 0x02++0x01 line.word 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" else group.byte 0x02++0x00 line.byte 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" endif sif !cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840400))&0x800)==0x000)&&(((per.w(ad:0xB4840400+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x01)==0x01) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif else if (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840400))&0x800)==0x000)&&(((per.w(ad:0xB4840400+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x201)==(0x01||0x200)) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif endif group.word 0x06++0x01 line.word 0x00 "SGAR,Amplitude Data Register" group.byte 0x05++0x00 line.byte 0x00 "SGFR,Frequency Data Register" group.byte 0x04++0x00 line.byte 0x00 "SGNR,Tone Output Number Register" group.byte 0x0B++0x00 line.byte 0x00 "SGTCR,Time Cycle Register" group.byte 0x0A++0x00 line.byte 0x00 "SSGIDR,Increase And Decrease Data Register" group.word 0x08++0x01 line.word 0x00 "SGPCR,PWM Cycle Data Register" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x0C++0x00 line.byte 0x00 "SGEFR,Extended Frequency Data Register" wgroup.long 0x10++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x14++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x10++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" endif width 0x0B tree.end tree "SG2" base ad:0xB4840800 width 12. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.word 0x02++0x01 line.word 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" else group.byte 0x02++0x00 line.byte 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" endif sif !cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840800))&0x800)==0x000)&&(((per.w(ad:0xB4840800+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x01)==0x01) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif else if (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840800))&0x800)==0x000)&&(((per.w(ad:0xB4840800+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x201)==(0x01||0x200)) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif endif group.word 0x06++0x01 line.word 0x00 "SGAR,Amplitude Data Register" group.byte 0x05++0x00 line.byte 0x00 "SGFR,Frequency Data Register" group.byte 0x04++0x00 line.byte 0x00 "SGNR,Tone Output Number Register" group.byte 0x0B++0x00 line.byte 0x00 "SGTCR,Time Cycle Register" group.byte 0x0A++0x00 line.byte 0x00 "SSGIDR,Increase And Decrease Data Register" group.word 0x08++0x01 line.word 0x00 "SGPCR,PWM Cycle Data Register" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x0C++0x00 line.byte 0x00 "SGEFR,Extended Frequency Data Register" wgroup.long 0x10++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x14++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x10++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" endif width 0x0B tree.end tree "SG3" base ad:0xB4840C00 width 12. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.word 0x02++0x01 line.word 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" else group.byte 0x02++0x00 line.byte 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" endif sif !cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB4840C00))&0x800)==0x800)&&(((per.w(ad:0xB4840C00+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840C00))&0x800)==0x000)&&(((per.w(ad:0xB4840C00+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840C00))&0x800)==0x800)&&(((per.w(ad:0xB4840C00+0x00))&0x01)==0x01) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif else if (((per.w(ad:0xB4840C00))&0x800)==0x800)&&(((per.w(ad:0xB4840C00+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840C00))&0x800)==0x000)&&(((per.w(ad:0xB4840C00+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4840C00))&0x800)==0x800)&&(((per.w(ad:0xB4840C00+0x00))&0x201)==(0x01||0x200)) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif endif group.word 0x06++0x01 line.word 0x00 "SGAR,Amplitude Data Register" group.byte 0x05++0x00 line.byte 0x00 "SGFR,Frequency Data Register" group.byte 0x04++0x00 line.byte 0x00 "SGNR,Tone Output Number Register" group.byte 0x0B++0x00 line.byte 0x00 "SGTCR,Time Cycle Register" group.byte 0x0A++0x00 line.byte 0x00 "SSGIDR,Increase And Decrease Data Register" group.word 0x08++0x01 line.word 0x00 "SGPCR,PWM Cycle Data Register" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x0C++0x00 line.byte 0x00 "SGEFR,Extended Frequency Data Register" wgroup.long 0x10++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x14++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x10++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" endif width 0x0B tree.end sif (cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J336*")||cpuis("S6J337*")) tree "SG4" base ad:0xB4841000 width 12. sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.word 0x02++0x01 line.word 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" else group.byte 0x02++0x00 line.byte 0x00 "SGDER,DMA Transfer Update Enable Register" bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled" endif sif !cpuis("s6j336*")&&!cpuis("s6j337*") if (((per.w(ad:0xB4841000))&0x800)==0x800)&&(((per.w(ad:0xB4841000+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4841000))&0x800)==0x000)&&(((per.w(ad:0xB4841000+0x00))&0x01)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4841000))&0x800)==0x800)&&(((per.w(ad:0xB4841000+0x00))&0x01)==0x01) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" else bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" endif newline bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif else if (((per.w(ad:0xB4841000))&0x800)==0x800)&&(((per.w(ad:0xB4841000+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4841000))&0x800)==0x000)&&(((per.w(ad:0xB4841000+0x00))&0x201)==0x00) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" elif (((per.w(ad:0xB4841000))&0x800)==0x800)&&(((per.w(ad:0xB4841000+0x00))&0x201)==(0x01||0x200)) group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" else group.word 0x00++0x01 line.word 0x00 "SGCR,Sound Control Register" bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset" rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled" newline bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled" rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active" rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended" newline bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8" bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave" bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled" bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected" newline bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started" endif endif group.word 0x06++0x01 line.word 0x00 "SGAR,Amplitude Data Register" group.byte 0x05++0x00 line.byte 0x00 "SGFR,Frequency Data Register" group.byte 0x04++0x00 line.byte 0x00 "SGNR,Tone Output Number Register" group.byte 0x0B++0x00 line.byte 0x00 "SGTCR,Time Cycle Register" group.byte 0x0A++0x00 line.byte 0x00 "SSGIDR,Increase And Decrease Data Register" group.word 0x08++0x01 line.word 0x00 "SGPCR,PWM Cycle Data Register" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.byte 0x0C++0x00 line.byte 0x00 "SGEFR,Extended Frequency Data Register" wgroup.long 0x10++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x14++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register" wgroup.word 0x10++0x01 line.word 0x00 "SGCCR,Interrupt Clear Register" bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear" endif width 0x0B tree.end endif tree.end endif sif (cpuis("S6J336*")) tree "WFG (Wave Form Generator)" base ad:0xB8028000 width 21. group.long 0x00++0x07 line.long 0x00 "WGCHEN,Waveform Generator Channel Enable Register" bitfld.long 0x00 4. " CH4EN ,Channel 4 operation enable/disable" "Disabled,Enabled" bitfld.long 0x00 3. " CH3EN ,Channel 3 operation enable/disable" "Disabled,Enabled" bitfld.long 0x00 2. " CH2EN ,Channel 2 operation enable/disable" "Disabled,Enabled" newline bitfld.long 0x00 1. " CH1EN ,Channel 1 operation enable/disable" "Disabled,Enabled" bitfld.long 0x00 0. " CH0EN ,Channel 0 operation enable/disable" "Disabled,Enabled" line.long 0x04 "WGCHSTART,Waveform Generator Channel Start Register" bitfld.long 0x04 4. " CH4START ,Channel 4 sound source generation start" "Not started,Started" bitfld.long 0x04 3. " CH3START ,Channel 3 sound source generation start" "Not started,Started" bitfld.long 0x04 2. " CH2START ,Channel 2 sound source generation start" "Not started,Started" newline bitfld.long 0x04 1. " CH1START ,Channel 1 sound source generation start" "Not started,Started" bitfld.long 0x04 0. " CH0START ,Channel 0 sound source generation start" "Not started,Started" rgroup.long 0x08++0x03 line.long 0x00 "WGCHBUSY,Waveform Generator Channel Busy Register" bitfld.long 0x00 4. " CH4BUSY ,Channel 4 busy" "Not busy,Busy" bitfld.long 0x00 3. " CH3BUSY ,Channel 3 busy" "Not busy,Busy" bitfld.long 0x00 2. " CH2BUSY ,Channel 2 busy" "Not busy,Busy" newline bitfld.long 0x00 1. " CH1BUSY ,Channel 1 busy" "Not busy,Busy" bitfld.long 0x00 0. " CH0BUSY ,Channel 0 busy" "Not busy,Busy" group.long 0x0C++0x07 line.long 0x00 "WGCHSTOP,Waveform Generator Channel Stop Register" bitfld.long 0x00 4. " CH4STOP ,Forced termination for channel 4 sound source generation" "Available/No effect,Operating/Initiate" bitfld.long 0x00 3. " CH3STOP ,Forced termination for channel 3 sound source generation" "Available/No effect,Operating/Initiate" bitfld.long 0x00 2. " CH2STOP ,Forced termination for channel 2 sound source generation" "Available/No effect,Operating/Initiate" newline bitfld.long 0x00 1. " CH1STOP ,Forced termination for channel 1 sound source generation" "Available/No effect,Operating/Initiate" bitfld.long 0x00 0. " CH0STOP ,Forced termination for channel 0 sound source generation" "Available/No effect,Operating/Initiate" line.long 0x04 "WGCHDMAEN,Waveform Generator Channel DMA Enable Register" bitfld.long 0x04 4. " CH4DMAEN ,Channel 4 support DMA I/F for setting enable" "Disabled,Enabled" bitfld.long 0x04 3. " CH3DMAEN ,Channel 3 support DMA I/F for setting enable" "Disabled,Enabled" bitfld.long 0x04 2. " CH2DMAEN ,Channel 2 support DMA I/F for setting enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " CH0DMAEN ,Channel 1 support DMA I/F for setting enable" "Disabled,Enabled" bitfld.long 0x04 0. " CH0STOP ,Channel 0 support DMA I/F for setting enable" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "WGINTRSTATE_SET/CLR,Waveform Generator Interrupt Register" setclrfld.long 0x00 16. -0x04 16. 0x04 16. " AHBERR ,AHB MASTER INTERFACE bus error interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 4. -0x04 4. 0x04 4. " CH4END ,Channel 4 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 3. -0x04 3. 0x04 3. " CH3END ,Channel 3 sound source generation end interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 2. -0x04 2. 0x04 2. " CH2END ,Channel 2 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 1. -0x04 1. 0x04 1. " CH1END ,Channel 1 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. -0x04 0. 0x04 0. " CH0END ,Channel 0 sound source generation end interrupt enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "WGAHBERR,Waveform Generator AHB Bus Error Register" bitfld.long 0x00 0.--1. " AHBSERR ,SWFG AHB slave interface access error information indication" "No error,Address error,Write access to RO,Access size" group.long 0x24++0x0B line.long 0x00 "WGCHADD0,Waveform Generator Channel Address0 Register" hexmask.long.word 0x00 16.--28. 0x01 " CH1ADD ,Channel 1 output destination address" hexmask.long.word 0x00 0.--12. 0x01 " CH0ADD ,Channel 0 output destination address" line.long 0x04 "WGCHADD1,Waveform Generator Channel Address1 Register" hexmask.long.word 0x04 16.--28. 0x01 " CH3ADD ,Channel 3 output destination address" hexmask.long.word 0x04 0.--12. 0x01 " CH2ADD ,Channel 2 output destination address" line.long 0x08 "WGCHADD2,Waveform Generator Channel Address2 Register" hexmask.long.word 0x08 0.--12. 0x01 " CH4ADD ,Channel 4 output destination address" tree "Coefficient 0" group.long 0x80++0x03 line.long 0x00 "WGCH0FILCOEF0,Channel 0 Filter Coefficient 0 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF1 ,CH0 setting of the filter coefficient 1" hexmask.long.word 0x00 0.--15. 1. " FILCOEF0 ,CH0 setting of the filter coefficient 0" group.long 0xC0++0x03 line.long 0x00 "WGCH1FILCOEF0,Channel 1 Filter Coefficient 0 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF1 ,CH1 setting of the filter coefficient 1" hexmask.long.word 0x00 0.--15. 1. " FILCOEF0 ,CH1 setting of the filter coefficient 0" group.long 0x100++0x03 line.long 0x00 "WGCH2FILCOEF0,Channel 2 Filter Coefficient 0 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF1 ,CH2 setting of the filter coefficient 1" hexmask.long.word 0x00 0.--15. 1. " FILCOEF0 ,CH2 setting of the filter coefficient 0" group.long 0x140++0x03 line.long 0x00 "WGCH3FILCOEF0,Channel 3 Filter Coefficient 0 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF1 ,CH3 setting of the filter coefficient 1" hexmask.long.word 0x00 0.--15. 1. " FILCOEF0 ,CH3 setting of the filter coefficient 0" group.long 0x180++0x03 line.long 0x00 "WGCH4FILCOEF0,Channel 4 Filter Coefficient 0 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF1 ,CH4 setting of the filter coefficient 1" hexmask.long.word 0x00 0.--15. 1. " FILCOEF0 ,CH4 setting of the filter coefficient 0" tree.end tree "Coefficient 1" group.long 0x84++0x03 line.long 0x00 "WGCH0FILCOEF1,Channel 0 Filter Coefficient 1 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF3 ,CH0 setting of the filter coefficient 3" hexmask.long.word 0x00 0.--15. 1. " FILCOEF2 ,CH0 setting of the filter coefficient 2" group.long 0xC4++0x03 line.long 0x00 "WGCH1FILCOEF1,Channel 1 Filter Coefficient 1 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF3 ,CH1 setting of the filter coefficient 3" hexmask.long.word 0x00 0.--15. 1. " FILCOEF2 ,CH1 setting of the filter coefficient 2" group.long 0x104++0x03 line.long 0x00 "WGCH2FILCOEF1,Channel 2 Filter Coefficient 1 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF3 ,CH2 setting of the filter coefficient 3" hexmask.long.word 0x00 0.--15. 1. " FILCOEF2 ,CH2 setting of the filter coefficient 2" group.long 0x144++0x03 line.long 0x00 "WGCH3FILCOEF1,Channel 3 Filter Coefficient 1 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF3 ,CH3 setting of the filter coefficient 3" hexmask.long.word 0x00 0.--15. 1. " FILCOEF2 ,CH3 setting of the filter coefficient 2" group.long 0x184++0x03 line.long 0x00 "WGCH4FILCOEF1,Channel 4 Filter Coefficient 1 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF3 ,CH4 setting of the filter coefficient 3" hexmask.long.word 0x00 0.--15. 1. " FILCOEF2 ,CH4 setting of the filter coefficient 2" tree.end tree "Coefficient 2" group.long 0x88++0x03 line.long 0x00 "WGCH0FILCOEF2,Channel 0 Filter Coefficient 2 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF5 ,CH0 setting of the filter coefficient 5" hexmask.long.word 0x00 0.--15. 1. " FILCOEF4 ,CH0 setting of the filter coefficient 4" group.long 0xC8++0x03 line.long 0x00 "WGCH1FILCOEF2,Channel 1 Filter Coefficient 2 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF5 ,CH1 setting of the filter coefficient 5" hexmask.long.word 0x00 0.--15. 1. " FILCOEF4 ,CH1 setting of the filter coefficient 4" group.long 0x108++0x03 line.long 0x00 "WGCH2FILCOEF2,Channel 2 Filter Coefficient 2 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF5 ,CH2 setting of the filter coefficient 5" hexmask.long.word 0x00 0.--15. 1. " FILCOEF4 ,CH2 setting of the filter coefficient 4" group.long 0x148++0x03 line.long 0x00 "WGCH3FILCOEF2,Channel 3 Filter Coefficient 2 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF5 ,CH3 setting of the filter coefficient 5" hexmask.long.word 0x00 0.--15. 1. " FILCOEF4 ,CH3 setting of the filter coefficient 4" group.long 0x188++0x03 line.long 0x00 "WGCH4FILCOEF2,Channel 4 Filter Coefficient 2 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF5 ,CH4 setting of the filter coefficient 5" hexmask.long.word 0x00 0.--15. 1. " FILCOEF4 ,CH4 setting of the filter coefficient 4" tree.end tree "Coefficient 3" group.long 0x8C++0x03 line.long 0x00 "WGCH0FILCOEF3,Channel 0 Filter Coefficient 3 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF7 ,CH0 setting of the filter coefficient 7" hexmask.long.word 0x00 0.--15. 1. " FILCOEF6 ,CH0 setting of the filter coefficient 6" group.long 0xCC++0x03 line.long 0x00 "WGCH1FILCOEF3,Channel 1 Filter Coefficient 3 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF7 ,CH1 setting of the filter coefficient 7" hexmask.long.word 0x00 0.--15. 1. " FILCOEF6 ,CH1 setting of the filter coefficient 6" group.long 0x10C++0x03 line.long 0x00 "WGCH2FILCOEF3,Channel 2 Filter Coefficient 3 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF7 ,CH2 setting of the filter coefficient 7" hexmask.long.word 0x00 0.--15. 1. " FILCOEF6 ,CH2 setting of the filter coefficient 6" group.long 0x14C++0x03 line.long 0x00 "WGCH3FILCOEF3,Channel 3 Filter Coefficient 3 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF7 ,CH3 setting of the filter coefficient 7" hexmask.long.word 0x00 0.--15. 1. " FILCOEF6 ,CH3 setting of the filter coefficient 6" group.long 0x18C++0x03 line.long 0x00 "WGCH4FILCOEF3,Channel 4 Filter Coefficient 3 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF7 ,CH4 setting of the filter coefficient 7" hexmask.long.word 0x00 0.--15. 1. " FILCOEF6 ,CH4 setting of the filter coefficient 6" tree.end tree "Coefficient 4" group.long 0x90++0x03 line.long 0x00 "WGCH0FILCOEF4,Channel 0 Filter Coefficient 4 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF9 ,CH0 setting of the filter coefficient 9" hexmask.long.word 0x00 0.--15. 1. " FILCOEF8 ,CH0 setting of the filter coefficient 8" group.long 0xD0++0x03 line.long 0x00 "WGCH1FILCOEF4,Channel 1 Filter Coefficient 4 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF9 ,CH1 setting of the filter coefficient 9" hexmask.long.word 0x00 0.--15. 1. " FILCOEF8 ,CH1 setting of the filter coefficient 8" group.long 0x110++0x03 line.long 0x00 "WGCH2FILCOEF4,Channel 2 Filter Coefficient 4 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF9 ,CH2 setting of the filter coefficient 9" hexmask.long.word 0x00 0.--15. 1. " FILCOEF8 ,CH2 setting of the filter coefficient 8" group.long 0x150++0x03 line.long 0x00 "WGCH3FILCOEF4,Channel 3 Filter Coefficient 4 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF9 ,CH3 setting of the filter coefficient 9" hexmask.long.word 0x00 0.--15. 1. " FILCOEF8 ,CH3 setting of the filter coefficient 8" group.long 0x190++0x03 line.long 0x00 "WGCH4FILCOEF4,Channel 4 Filter Coefficient 4 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF9 ,CH4 setting of the filter coefficient 9" hexmask.long.word 0x00 0.--15. 1. " FILCOEF8 ,CH4 setting of the filter coefficient 8" tree.end tree "Coefficient 5" group.long 0x94++0x03 line.long 0x00 "WGCH0FILCOEF5,Channel 0 Filter Coefficient 5 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF11 ,CH0 setting of the filter coefficient 11" hexmask.long.word 0x00 0.--15. 1. " FILCOEF10 ,CH0 setting of the filter coefficient 10" group.long 0xD4++0x03 line.long 0x00 "WGCH1FILCOEF5,Channel 1 Filter Coefficient 5 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF11 ,CH1 setting of the filter coefficient 11" hexmask.long.word 0x00 0.--15. 1. " FILCOEF10 ,CH1 setting of the filter coefficient 10" group.long 0x114++0x03 line.long 0x00 "WGCH2FILCOEF5,Channel 2 Filter Coefficient 5 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF11 ,CH2 setting of the filter coefficient 11" hexmask.long.word 0x00 0.--15. 1. " FILCOEF10 ,CH2 setting of the filter coefficient 10" group.long 0x154++0x03 line.long 0x00 "WGCH3FILCOEF5,Channel 3 Filter Coefficient 5 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF11 ,CH3 setting of the filter coefficient 11" hexmask.long.word 0x00 0.--15. 1. " FILCOEF10 ,CH3 setting of the filter coefficient 10" group.long 0x194++0x03 line.long 0x00 "WGCH4FILCOEF5,Channel 4 Filter Coefficient 5 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF11 ,CH4 setting of the filter coefficient 11" hexmask.long.word 0x00 0.--15. 1. " FILCOEF10 ,CH4 setting of the filter coefficient 10" tree.end tree "Coefficient 6" group.long 0x98++0x03 line.long 0x00 "WGCH0FILCOEF6,Channel 0 Filter Coefficient 6 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF13 ,CH0 setting of the filter coefficient 13" hexmask.long.word 0x00 0.--15. 1. " FILCOEF12 ,CH0 setting of the filter coefficient 12" group.long 0xD8++0x03 line.long 0x00 "WGCH1FILCOEF6,Channel 1 Filter Coefficient 6 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF13 ,CH1 setting of the filter coefficient 13" hexmask.long.word 0x00 0.--15. 1. " FILCOEF12 ,CH1 setting of the filter coefficient 12" group.long 0x118++0x03 line.long 0x00 "WGCH2FILCOEF6,Channel 2 Filter Coefficient 6 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF13 ,CH2 setting of the filter coefficient 13" hexmask.long.word 0x00 0.--15. 1. " FILCOEF12 ,CH2 setting of the filter coefficient 12" group.long 0x158++0x03 line.long 0x00 "WGCH3FILCOEF6,Channel 3 Filter Coefficient 6 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF13 ,CH3 setting of the filter coefficient 13" hexmask.long.word 0x00 0.--15. 1. " FILCOEF12 ,CH3 setting of the filter coefficient 12" group.long 0x198++0x03 line.long 0x00 "WGCH4FILCOEF6,Channel 4 Filter Coefficient 6 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF13 ,CH4 setting of the filter coefficient 13" hexmask.long.word 0x00 0.--15. 1. " FILCOEF12 ,CH4 setting of the filter coefficient 12" tree.end tree "Coefficient 7" group.long 0x9C++0x03 line.long 0x00 "WGCH0FILCOEF7,Channel 0 Filter Coefficient 7 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF15 ,CH0 setting of the filter coefficient 15" hexmask.long.word 0x00 0.--15. 1. " FILCOEF14 ,CH0 setting of the filter coefficient 14" group.long 0xDC++0x03 line.long 0x00 "WGCH1FILCOEF7,Channel 1 Filter Coefficient 7 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF15 ,CH1 setting of the filter coefficient 15" hexmask.long.word 0x00 0.--15. 1. " FILCOEF14 ,CH1 setting of the filter coefficient 14" group.long 0x11C++0x03 line.long 0x00 "WGCH2FILCOEF7,Channel 2 Filter Coefficient 7 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF15 ,CH2 setting of the filter coefficient 15" hexmask.long.word 0x00 0.--15. 1. " FILCOEF14 ,CH2 setting of the filter coefficient 14" group.long 0x15C++0x03 line.long 0x00 "WGCH3FILCOEF7,Channel 3 Filter Coefficient 7 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF15 ,CH3 setting of the filter coefficient 15" hexmask.long.word 0x00 0.--15. 1. " FILCOEF14 ,CH3 setting of the filter coefficient 14" group.long 0x19C++0x03 line.long 0x00 "WGCH4FILCOEF7,Channel 4 Filter Coefficient 7 Register" hexmask.long.word 0x00 16.--31. 1. " FILCOEF15 ,CH4 setting of the filter coefficient 15" hexmask.long.word 0x00 0.--15. 1. " FILCOEF14 ,CH4 setting of the filter coefficient 14" tree.end tree "Control 0" group.long 0xA0++0x03 line.long 0x00 "WGCH0CTRL0,Channel 0 Control 0 Register" bitfld.long 0x00 31. " FILEN ,Filter effective/invalidity enable" "Invalid,Effective" bitfld.long 0x00 24.--26. " STOPREL ,Stop release time" "0 ms,2.5 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms" bitfld.long 0x00 16.--19. " CONTNUM ,Continuous number" "x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,Infinity" newline bitfld.long 0x00 8. " PCMZEROEN ,PCM ZERO phase enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADPHASEEN ,Adjust phase enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " ADPHASECH ,Adjust phase channel" "0,1,2,3,4,4,4,4" group.long 0xE0++0x03 line.long 0x00 "WGCH1CTRL0,Channel 1 Control 0 Register" bitfld.long 0x00 31. " FILEN ,Filter effective/invalidity enable" "Invalid,Effective" bitfld.long 0x00 24.--26. " STOPREL ,Stop release time" "0 ms,2.5 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms" bitfld.long 0x00 16.--19. " CONTNUM ,Continuous number" "x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,Infinity" newline bitfld.long 0x00 8. " PCMZEROEN ,PCM ZERO phase enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADPHASEEN ,Adjust phase enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " ADPHASECH ,Adjust phase channel" "0,1,2,3,4,4,4,4" group.long 0x120++0x03 line.long 0x00 "WGCH2CTRL0,Channel 2 Control 0 Register" bitfld.long 0x00 31. " FILEN ,Filter effective/invalidity enable" "Invalid,Effective" bitfld.long 0x00 24.--26. " STOPREL ,Stop release time" "0 ms,2.5 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms" bitfld.long 0x00 16.--19. " CONTNUM ,Continuous number" "x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,Infinity" newline bitfld.long 0x00 8. " PCMZEROEN ,PCM ZERO phase enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADPHASEEN ,Adjust phase enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " ADPHASECH ,Adjust phase channel" "0,1,2,3,4,4,4,4" group.long 0x160++0x03 line.long 0x00 "WGCH3CTRL0,Channel 3 Control 0 Register" bitfld.long 0x00 31. " FILEN ,Filter effective/invalidity enable" "Invalid,Effective" bitfld.long 0x00 24.--26. " STOPREL ,Stop release time" "0 ms,2.5 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms" bitfld.long 0x00 16.--19. " CONTNUM ,Continuous number" "x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,Infinity" newline bitfld.long 0x00 8. " PCMZEROEN ,PCM ZERO phase enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADPHASEEN ,Adjust phase enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " ADPHASECH ,Adjust phase channel" "0,1,2,3,4,4,4,4" group.long 0x1A0++0x03 line.long 0x00 "WGCH4CTRL0,Channel 4 Control 0 Register" bitfld.long 0x00 31. " FILEN ,Filter effective/invalidity enable" "Invalid,Effective" bitfld.long 0x00 24.--26. " STOPREL ,Stop release time" "0 ms,2.5 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms" bitfld.long 0x00 16.--19. " CONTNUM ,Continuous number" "x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,Infinity" newline bitfld.long 0x00 8. " PCMZEROEN ,PCM ZERO phase enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADPHASEEN ,Adjust phase enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " ADPHASECH ,Adjust phase channel" "0,1,2,3,4,4,4,4" tree.end tree "Control 1" group.long 0xA4++0x03 line.long 0x00 "WGCH0CTRL1,Channel 0 Control 1 Register" bitfld.long 0x00 31. " DBEN ,Decibel enable" "Magnification,Decibel" bitfld.long 0x00 29. " GAINUDSEL ,Gain up/down selector" "Increase,Decrease" hexmask.long.tbyte 0x00 12.--28. 1. " GAINFLUCT ,Gain fluctuation" newline bitfld.long 0x00 10. " GAINSUCEN ,Gain transfer enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " INITGAIN ,Initial gain" group.long 0xE4++0x03 line.long 0x00 "WGCH1CTRL1,Channel 1 Control 1 Register" bitfld.long 0x00 31. " DBEN ,Decibel enable" "Magnification,Decibel" bitfld.long 0x00 29. " GAINUDSEL ,Gain up/down selector" "Increase,Decrease" hexmask.long.tbyte 0x00 12.--28. 1. " GAINFLUCT ,Gain fluctuation" newline bitfld.long 0x00 10. " GAINSUCEN ,Gain transfer enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " INITGAIN ,Initial gain" group.long 0x124++0x03 line.long 0x00 "WGCH2CTRL1,Channel 2 Control 1 Register" bitfld.long 0x00 31. " DBEN ,Decibel enable" "Magnification,Decibel" bitfld.long 0x00 29. " GAINUDSEL ,Gain up/down selector" "Increase,Decrease" hexmask.long.tbyte 0x00 12.--28. 1. " GAINFLUCT ,Gain fluctuation" newline bitfld.long 0x00 10. " GAINSUCEN ,Gain transfer enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " INITGAIN ,Initial gain" group.long 0x164++0x03 line.long 0x00 "WGCH3CTRL1,Channel 3 Control 1 Register" bitfld.long 0x00 31. " DBEN ,Decibel enable" "Magnification,Decibel" bitfld.long 0x00 29. " GAINUDSEL ,Gain up/down selector" "Increase,Decrease" hexmask.long.tbyte 0x00 12.--28. 1. " GAINFLUCT ,Gain fluctuation" newline bitfld.long 0x00 10. " GAINSUCEN ,Gain transfer enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " INITGAIN ,Initial gain" group.long 0x1A4++0x03 line.long 0x00 "WGCH4CTRL1,Channel 4 Control 1 Register" bitfld.long 0x00 31. " DBEN ,Decibel enable" "Magnification,Decibel" bitfld.long 0x00 29. " GAINUDSEL ,Gain up/down selector" "Increase,Decrease" hexmask.long.tbyte 0x00 12.--28. 1. " GAINFLUCT ,Gain fluctuation" newline bitfld.long 0x00 10. " GAINSUCEN ,Gain transfer enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " INITGAIN ,Initial gain" tree.end tree "Control 2" group.long 0xA8++0x03 line.long 0x00 "WGCH0CTRL2,Channel 0 Control 2 Register" bitfld.long 0x00 31. " RELCVSEL ,Release curve selector" "Linear,Exponential" bitfld.long 0x00 24.--28. " RELEASE ,Release time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" bitfld.long 0x00 23. " ATTCVSEL ,Attack curve selector" "Linear,Exponential" newline bitfld.long 0x00 16.--20. " ATACK ,Attack time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" hexmask.long.byte 0x00 8.--14. 1. " DUTY ,DUTY setting" bitfld.long 0x00 4.--5. " FSINF ,Type of generation sound waveform" "Sign,Triangle,Square,Square" newline bitfld.long 0x00 0.--1. " MONO ,Channel output data pattern" "Both,Lower,Upper,?..." group.long 0xE8++0x03 line.long 0x00 "WGCH1CTRL2,Channel 1 Control 2 Register" bitfld.long 0x00 31. " RELCVSEL ,Release curve selector" "Linear,Exponential" bitfld.long 0x00 24.--28. " RELEASE ,Release time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" bitfld.long 0x00 23. " ATTCVSEL ,Attack curve selector" "Linear,Exponential" newline bitfld.long 0x00 16.--20. " ATACK ,Attack time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" hexmask.long.byte 0x00 8.--14. 1. " DUTY ,DUTY setting" bitfld.long 0x00 4.--5. " FSINF ,Type of generation sound waveform" "Sign,Triangle,Square,Square" newline bitfld.long 0x00 0.--1. " MONO ,Channel output data pattern" "Both,Lower,Upper,?..." group.long 0x128++0x03 line.long 0x00 "WGCH2CTRL2,Channel 2 Control 2 Register" bitfld.long 0x00 31. " RELCVSEL ,Release curve selector" "Linear,Exponential" bitfld.long 0x00 24.--28. " RELEASE ,Release time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" bitfld.long 0x00 23. " ATTCVSEL ,Attack curve selector" "Linear,Exponential" newline bitfld.long 0x00 16.--20. " ATACK ,Attack time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" hexmask.long.byte 0x00 8.--14. 1. " DUTY ,DUTY setting" bitfld.long 0x00 4.--5. " FSINF ,Type of generation sound waveform" "Sign,Triangle,Square,Square" newline bitfld.long 0x00 0.--1. " MONO ,Channel output data pattern" "Both,Lower,Upper,?..." group.long 0x168++0x03 line.long 0x00 "WGCH3CTRL2,Channel 3 Control 2 Register" bitfld.long 0x00 31. " RELCVSEL ,Release curve selector" "Linear,Exponential" bitfld.long 0x00 24.--28. " RELEASE ,Release time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" bitfld.long 0x00 23. " ATTCVSEL ,Attack curve selector" "Linear,Exponential" newline bitfld.long 0x00 16.--20. " ATACK ,Attack time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" hexmask.long.byte 0x00 8.--14. 1. " DUTY ,DUTY setting" bitfld.long 0x00 4.--5. " FSINF ,Type of generation sound waveform" "Sign,Triangle,Square,Square" newline bitfld.long 0x00 0.--1. " MONO ,Channel output data pattern" "Both,Lower,Upper,?..." group.long 0x1A8++0x03 line.long 0x00 "WGCH4CTRL2,Channel 4 Control 2 Register" bitfld.long 0x00 31. " RELCVSEL ,Release curve selector" "Linear,Exponential" bitfld.long 0x00 24.--28. " RELEASE ,Release time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" bitfld.long 0x00 23. " ATTCVSEL ,Attack curve selector" "Linear,Exponential" newline bitfld.long 0x00 16.--20. " ATACK ,Attack time" "Not used,1 ms,2 ms,3 ms,4 ms,5 ms,7.5 ms,10 ms,15 ms,20 ms,25 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,250 ms,300 ms,400 ms,500 ms,750 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms,1000 ms" hexmask.long.byte 0x00 8.--14. 1. " DUTY ,DUTY setting" bitfld.long 0x00 4.--5. " FSINF ,Type of generation sound waveform" "Sign,Triangle,Square,Square" newline bitfld.long 0x00 0.--1. " MONO ,Channel output data pattern" "Both,Lower,Upper,?..." tree.end tree "Control 3" group.long 0xAC++0x03 line.long 0x00 "WGCH0CTRL3,Channel 0 Control 3 Register" hexmask.long.word 0x00 16.--29. 1. " ITVAL2 ,Posterior mute time" hexmask.long.word 0x00 0.--13. 1. " ITVAL1 ,Anterior mute time" group.long 0xEC++0x03 line.long 0x00 "WGCH1CTRL3,Channel 1 Control 3 Register" hexmask.long.word 0x00 16.--29. 1. " ITVAL2 ,Posterior mute time" hexmask.long.word 0x00 0.--13. 1. " ITVAL1 ,Anterior mute time" group.long 0x12C++0x03 line.long 0x00 "WGCH2CTRL3,Channel 2 Control 3 Register" hexmask.long.word 0x00 16.--29. 1. " ITVAL2 ,Posterior mute time" hexmask.long.word 0x00 0.--13. 1. " ITVAL1 ,Anterior mute time" group.long 0x16C++0x03 line.long 0x00 "WGCH3CTRL3,Channel 3 Control 3 Register" hexmask.long.word 0x00 16.--29. 1. " ITVAL2 ,Posterior mute time" hexmask.long.word 0x00 0.--13. 1. " ITVAL1 ,Anterior mute time" group.long 0x1AC++0x03 line.long 0x00 "WGCH4CTRL3,Channel 4 Control 3 Register" hexmask.long.word 0x00 16.--29. 1. " ITVAL2 ,Posterior mute time" hexmask.long.word 0x00 0.--13. 1. " ITVAL1 ,Anterior mute time" tree.end tree "Control 4" group.long 0xB0++0x03 line.long 0x00 "WGCH0CTRL4,Channel 0 Control 4 Register" bitfld.long 0x00 31. " CH0START ,Channel 0 start mirror bit" "Not started,Started" hexmask.long.word 0x00 16.--29. 1. " FSLEN ,Run time" hexmask.long.word 0x00 0.--15. 1. " FSFREQ ,Frequency setting" group.long 0xF0++0x03 line.long 0x00 "WGCH1CTRL4,Channel 1 Control 4 Register" bitfld.long 0x00 31. " CH1START ,Channel 1 start mirror bit" "Not started,Started" hexmask.long.word 0x00 16.--29. 1. " FSLEN ,Run time" hexmask.long.word 0x00 0.--15. 1. " FSFREQ ,Frequency setting" group.long 0x130++0x03 line.long 0x00 "WGCH2CTRL4,Channel 2 Control 4 Register" bitfld.long 0x00 31. " CH2START ,Channel 2 start mirror bit" "Not started,Started" hexmask.long.word 0x00 16.--29. 1. " FSLEN ,Run time" hexmask.long.word 0x00 0.--15. 1. " FSFREQ ,Frequency setting" group.long 0x170++0x03 line.long 0x00 "WGCH3CTRL4,Channel 3 Control 4 Register" bitfld.long 0x00 31. " CH3START ,Channel 3 start mirror bit" "Not started,Started" hexmask.long.word 0x00 16.--29. 1. " FSLEN ,Run time" hexmask.long.word 0x00 0.--15. 1. " FSFREQ ,Frequency setting" group.long 0x1B0++0x03 line.long 0x00 "WGCH4CTRL4,Channel 4 Control 4 Register" bitfld.long 0x00 31. " CH4START ,Channel 4 start mirror bit" "Not started,Started" hexmask.long.word 0x00 16.--29. 1. " FSLEN ,Run time" hexmask.long.word 0x00 0.--15. 1. " FSFREQ ,Frequency setting" tree.end newline rgroup.long 0xB4++0x03 line.long 0x00 "WGCH0STATUS,Channel 0 Status Register" bitfld.long 0x00 16.--19. " CONTNUMR ,Continuous remaining number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15. " ENDGAINV ,End gain value status" "Invalid,Valid" hexmask.long.word 0x00 0.--9. 1. " ENDGAIN ,End gain at completion of sound source generation" rgroup.long 0xF4++0x03 line.long 0x00 "WGCH1STATUS,Channel 1 Status Register" bitfld.long 0x00 16.--19. " CONTNUMR ,Continuous remaining number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15. " ENDGAINV ,End gain value status" "Invalid,Valid" hexmask.long.word 0x00 0.--9. 1. " ENDGAIN ,End gain at completion of sound source generation" rgroup.long 0x134++0x03 line.long 0x00 "WGCH2STATUS,Channel 2 Status Register" bitfld.long 0x00 16.--19. " CONTNUMR ,Continuous remaining number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15. " ENDGAINV ,End gain value status" "Invalid,Valid" hexmask.long.word 0x00 0.--9. 1. " ENDGAIN ,End gain at completion of sound source generation" rgroup.long 0x174++0x03 line.long 0x00 "WGCH3STATUS,Channel 3 Status Register" bitfld.long 0x00 16.--19. " CONTNUMR ,Continuous remaining number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15. " ENDGAINV ,End gain value status" "Invalid,Valid" hexmask.long.word 0x00 0.--9. 1. " ENDGAIN ,End gain at completion of sound source generation" rgroup.long 0x1B4++0x03 line.long 0x00 "WGCH4STATUS,Channel 4 Status Register" bitfld.long 0x00 16.--19. " CONTNUMR ,Continuous remaining number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15. " ENDGAINV ,End gain value status" "Invalid,Valid" hexmask.long.word 0x00 0.--9. 1. " ENDGAIN ,End gain at completion of sound source generation" width 0x0B tree.end elif (!cpuis("S6J335*")&&!cpuis("S6J337*")) tree "WFG (Wave Form Generator)" base ad:0xB8028000 width 21. group.long 0x00++0x07 line.long 0x00 "WGCHEN,Waveform Generator Channel Enable Register" bitfld.long 0x00 4. " CH4EN ,Channel 4 operation enable/disable" "Disabled,Enabled" bitfld.long 0x00 3. " CH3EN ,Channel 3 operation enable/disable" "Disabled,Enabled" bitfld.long 0x00 2. " CH2EN ,Channel 2 operation enable/disable" "Disabled,Enabled" newline bitfld.long 0x00 1. " CH1EN ,Channel 1 operation enable/disable" "Disabled,Enabled" bitfld.long 0x00 0. " CH0EN ,Channel 0 operation enable/disable" "Disabled,Enabled" line.long 0x04 "WGCHSTART,Waveform Generator Channel Start Register" bitfld.long 0x04 4. " CH4START ,Channel 4 sound source generation start" "Not started,Started" bitfld.long 0x04 3. " CH3START ,Channel 3 sound source generation start" "Not started,Started" bitfld.long 0x04 2. " CH2START ,Channel 2 sound source generation start" "Not started,Started" newline bitfld.long 0x04 1. " CH1START ,Channel 1 sound source generation start" "Not started,Started" bitfld.long 0x04 0. " CH0START ,Channel 0 sound source generation start" "Not started,Started" group.long 0x10++0x0F line.long 0x00 "WGCHADD1,Waveform Generator Channel Address1 Register" hexmask.long.word 0x00 16.--28. 1. " CH1ADD ,Channel 1 output destination address" hexmask.long.word 0x00 0.--12. 1. " CH0ADD ,Channel 0 output destination address" line.long 0x04 "WGCHADD2,Waveform Generator Channel Address2 Register" hexmask.long.word 0x04 16.--28. 1. " CH3ADD ,Channel 3 output destination address" hexmask.long.word 0x04 0.--12. 1. " CH2ADD ,Channel 2 output destination address" line.long 0x08 "WGCHADD3,Waveform Generator Channel Address3 Register" hexmask.long.word 0x08 0.--12. 1. " CH4ADD ,Channel 4 output destination address" line.long 0x0C "WGCHMONO,Waveform Generator Channel Monaural Register" bitfld.long 0x0C 8.--9. " CH4MONO ,Channel 4 output data pattern" "Upper and lower,Lower 16bits,Upper 16 bits,?..." bitfld.long 0x0C 6.--7. " CH3MONO ,Channel 3 output data pattern" "Upper and lower,Lower 16bits,Upper 16 bits,?..." bitfld.long 0x0C 4.--5. " CH2MONO ,Channel 2 output data pattern" "Upper and lower,Lower 16bits,Upper 16 bits,?..." newline bitfld.long 0x0C 2.--3. " CH1MONO ,Channel 1 output data pattern" "Upper and lower,Lower 16bits,Upper 16 bits,?..." bitfld.long 0x0C 0.--1. " CH0MONO ,Channel 0 output data pattern" "Upper and lower,Lower 16bits,Upper 16 bits,?..." group.long 0x20++0x0B line.long 0x00 "WGCH0CTRL1,Waveform Generator Channel 0 Control Register1" bitfld.long 0x00 16.--20. " FSLEN ,Run time" "1ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,2500ms,3000ms,3500ms,4000ms" bitfld.long 0x00 8.--9. " FSINF ,Waveform" "Sine,Sawtooth,Square,?..." bitfld.long 0x00 0.--5. " FSFREQ ,Frequency(Frequency (Hz)/Musical scale)" "110.00/A2,116.54/A#2,123.47/B2,130.81/C3,138.59/C#3,146.83/D3,155.56/D#3,164.81/E3,174.61/F3,185.00/F#3,196.00/G3,207.65/G#3,220.00/A3,233.08/A#3,246.94/B3,261.63/C4,277.18/C#4,293.66/D4,311.13/D#4,329.63/E4,349.23/F4,369.99/F#4,392.00/G4,415.30/G#4,440.00/A4,466.16/A#4,493.88/B4,523.25/C5,554.37/C#5,587.33/D5,622.25/D#5,659.26/E5,698.46/F5,739.99/F#5,783.99/G5,830.61/G#5,880.00/A5,932.33/A#5,987.77/B5,1046.50/C6,1108.73/C#C,1174.66/D6,1244.51/D#6,1318.51/E6,1396.91/F6,1479.98/F#6,1567.98/G6,1661.22/G#6,1760.00/A6,1864.66/A#6,1975.53/B6,2093.00/C7,2217.46/C#7,2349.32/D7,2489.02/D#7,2637.02/E7,2793.83/F7,2959.96/F#7,3135.96/G7,3322.44/G#7,3520.00/A7,3729.31/A#7,3951.07/B7,4186.01/C8" line.long 0x04 "WGCH0CTRL2,Waveform Generator Channel 0 Control Register2" bitfld.long 0x04 0.--4. " ITVAL1 ,Start idle time" "0ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,12ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,3000ms,3500ms,3500ms,4000ms" line.long 0x08 "WGCH0CTRL3,Waveform Generator Channel 0 Control Register3" bitfld.long 0x08 16.--17. " FILTER ,Low Pass Filter cutoff frequency" "Disabled,8KHz,5KHz,2KHz" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" else bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" endif group.long 0x30++0x0B line.long 0x00 "WGCH1CTRL1,Waveform Generator Channel 1 Control Register1" bitfld.long 0x00 16.--20. " FSLEN ,Run time" "1ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,2500ms,3000ms,3500ms,4000ms" bitfld.long 0x00 8.--9. " FSINF ,Waveform" "Sine,Sawtooth,Square,?..." bitfld.long 0x00 0.--5. " FSFREQ ,Frequency(Frequency (Hz)/Musical scale)" "110.00/A2,116.54/A#2,123.47/B2,130.81/C3,138.59/C#3,146.83/D3,155.56/D#3,164.81/E3,174.61/F3,185.00/F#3,196.00/G3,207.65/G#3,220.00/A3,233.08/A#3,246.94/B3,261.63/C4,277.18/C#4,293.66/D4,311.13/D#4,329.63/E4,349.23/F4,369.99/F#4,392.00/G4,415.30/G#4,440.00/A4,466.16/A#4,493.88/B4,523.25/C5,554.37/C#5,587.33/D5,622.25/D#5,659.26/E5,698.46/F5,739.99/F#5,783.99/G5,830.61/G#5,880.00/A5,932.33/A#5,987.77/B5,1046.50/C6,1108.73/C#C,1174.66/D6,1244.51/D#6,1318.51/E6,1396.91/F6,1479.98/F#6,1567.98/G6,1661.22/G#6,1760.00/A6,1864.66/A#6,1975.53/B6,2093.00/C7,2217.46/C#7,2349.32/D7,2489.02/D#7,2637.02/E7,2793.83/F7,2959.96/F#7,3135.96/G7,3322.44/G#7,3520.00/A7,3729.31/A#7,3951.07/B7,4186.01/C8" line.long 0x04 "WGCH1CTRL2,Waveform Generator Channel 1 Control Register2" bitfld.long 0x04 0.--4. " ITVAL1 ,Start idle time" "0ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,12ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,3000ms,3500ms,3500ms,4000ms" line.long 0x08 "WGCH1CTRL3,Waveform Generator Channel 1 Control Register3" bitfld.long 0x08 16.--17. " FILTER ,Low Pass Filter cutoff frequency" "Disabled,8KHz,5KHz,2KHz" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" else bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" endif group.long 0x40++0x0B line.long 0x00 "WGCH2CTRL1,Waveform Generator Channel 2 Control Register1" bitfld.long 0x00 16.--20. " FSLEN ,Run time" "1ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,2500ms,3000ms,3500ms,4000ms" bitfld.long 0x00 8.--9. " FSINF ,Waveform" "Sine,Sawtooth,Square,?..." bitfld.long 0x00 0.--5. " FSFREQ ,Frequency(Frequency (Hz)/Musical scale)" "110.00/A2,116.54/A#2,123.47/B2,130.81/C3,138.59/C#3,146.83/D3,155.56/D#3,164.81/E3,174.61/F3,185.00/F#3,196.00/G3,207.65/G#3,220.00/A3,233.08/A#3,246.94/B3,261.63/C4,277.18/C#4,293.66/D4,311.13/D#4,329.63/E4,349.23/F4,369.99/F#4,392.00/G4,415.30/G#4,440.00/A4,466.16/A#4,493.88/B4,523.25/C5,554.37/C#5,587.33/D5,622.25/D#5,659.26/E5,698.46/F5,739.99/F#5,783.99/G5,830.61/G#5,880.00/A5,932.33/A#5,987.77/B5,1046.50/C6,1108.73/C#C,1174.66/D6,1244.51/D#6,1318.51/E6,1396.91/F6,1479.98/F#6,1567.98/G6,1661.22/G#6,1760.00/A6,1864.66/A#6,1975.53/B6,2093.00/C7,2217.46/C#7,2349.32/D7,2489.02/D#7,2637.02/E7,2793.83/F7,2959.96/F#7,3135.96/G7,3322.44/G#7,3520.00/A7,3729.31/A#7,3951.07/B7,4186.01/C8" line.long 0x04 "WGCH2CTRL2,Waveform Generator Channel 2 Control Register2" bitfld.long 0x04 0.--4. " ITVAL1 ,Start idle time" "0ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,12ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,3000ms,3500ms,3500ms,4000ms" line.long 0x08 "WGCH2CTRL3,Waveform Generator Channel 2 Control Register3" bitfld.long 0x08 16.--17. " FILTER ,Low Pass Filter cutoff frequency" "Disabled,8KHz,5KHz,2KHz" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" else bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" endif group.long 0x50++0x0B line.long 0x00 "WGCH3CTRL1,Waveform Generator Channel 3 Control Register1" bitfld.long 0x00 16.--20. " FSLEN ,Run time" "1ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,2500ms,3000ms,3500ms,4000ms" bitfld.long 0x00 8.--9. " FSINF ,Waveform" "Sine,Sawtooth,Square,?..." bitfld.long 0x00 0.--5. " FSFREQ ,Frequency(Frequency (Hz)/Musical scale)" "110.00/A2,116.54/A#2,123.47/B2,130.81/C3,138.59/C#3,146.83/D3,155.56/D#3,164.81/E3,174.61/F3,185.00/F#3,196.00/G3,207.65/G#3,220.00/A3,233.08/A#3,246.94/B3,261.63/C4,277.18/C#4,293.66/D4,311.13/D#4,329.63/E4,349.23/F4,369.99/F#4,392.00/G4,415.30/G#4,440.00/A4,466.16/A#4,493.88/B4,523.25/C5,554.37/C#5,587.33/D5,622.25/D#5,659.26/E5,698.46/F5,739.99/F#5,783.99/G5,830.61/G#5,880.00/A5,932.33/A#5,987.77/B5,1046.50/C6,1108.73/C#C,1174.66/D6,1244.51/D#6,1318.51/E6,1396.91/F6,1479.98/F#6,1567.98/G6,1661.22/G#6,1760.00/A6,1864.66/A#6,1975.53/B6,2093.00/C7,2217.46/C#7,2349.32/D7,2489.02/D#7,2637.02/E7,2793.83/F7,2959.96/F#7,3135.96/G7,3322.44/G#7,3520.00/A7,3729.31/A#7,3951.07/B7,4186.01/C8" line.long 0x04 "WGCH3CTRL2,Waveform Generator Channel 3 Control Register2" bitfld.long 0x04 0.--4. " ITVAL1 ,Start idle time" "0ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,12ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,3000ms,3500ms,3500ms,4000ms" line.long 0x08 "WGCH3CTRL3,Waveform Generator Channel 3 Control Register3" bitfld.long 0x08 16.--17. " FILTER ,Low Pass Filter cutoff frequency" "Disabled,8KHz,5KHz,2KHz" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" else bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" endif group.long 0x60++0x0B line.long 0x00 "WGCH4CTRL1,Waveform Generator Channel 4 Control Register1" bitfld.long 0x00 16.--20. " FSLEN ,Run time" "1ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,2500ms,3000ms,3500ms,4000ms" bitfld.long 0x00 8.--9. " FSINF ,Waveform" "Sine,Sawtooth,Square,?..." bitfld.long 0x00 0.--5. " FSFREQ ,Frequency(Frequency (Hz)/Musical scale)" "110.00/A2,116.54/A#2,123.47/B2,130.81/C3,138.59/C#3,146.83/D3,155.56/D#3,164.81/E3,174.61/F3,185.00/F#3,196.00/G3,207.65/G#3,220.00/A3,233.08/A#3,246.94/B3,261.63/C4,277.18/C#4,293.66/D4,311.13/D#4,329.63/E4,349.23/F4,369.99/F#4,392.00/G4,415.30/G#4,440.00/A4,466.16/A#4,493.88/B4,523.25/C5,554.37/C#5,587.33/D5,622.25/D#5,659.26/E5,698.46/F5,739.99/F#5,783.99/G5,830.61/G#5,880.00/A5,932.33/A#5,987.77/B5,1046.50/C6,1108.73/C#C,1174.66/D6,1244.51/D#6,1318.51/E6,1396.91/F6,1479.98/F#6,1567.98/G6,1661.22/G#6,1760.00/A6,1864.66/A#6,1975.53/B6,2093.00/C7,2217.46/C#7,2349.32/D7,2489.02/D#7,2637.02/E7,2793.83/F7,2959.96/F#7,3135.96/G7,3322.44/G#7,3520.00/A7,3729.31/A#7,3951.07/B7,4186.01/C8" line.long 0x04 "WGCH4CTRL2,Waveform Generator Channel 4 Control Register2" bitfld.long 0x04 0.--4. " ITVAL1 ,Start idle time" "0ms,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,12ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1250ms,1500ms,2000ms,3000ms,3500ms,3500ms,4000ms" line.long 0x08 "WGCH4CTRL3,Waveform Generator Channel 4 Control Register3" bitfld.long 0x08 16.--17. " FILTER ,Low Pass Filter cutoff frequency" "Disabled,8KHz,5KHz,2KHz" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" else bitfld.long 0x08 8.--12. " RELEASE ,Fade out time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " ATTACK ,Fade in time" "Not used,1ms,2ms,3ms,4ms,5ms,7.5ms,10ms,15ms,20ms,25ms,30ms,40ms,50ms,75ms,100ms,125ms,150ms,200ms,250ms,300ms,400ms,500ms,750ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms,1000ms" endif group.long 0x70++0x03 line.long 0x00 "WGCHCLR,Waveform Generator Channel Clear Register" bitfld.long 0x00 4. " CH4CL ,Channel 4 sound source initialization" "No,Yes" bitfld.long 0x00 3. " CH3CL ,Channel 3 sound source initialization" "No,Yes" bitfld.long 0x00 2. " CH2CL ,Channel 2 sound source initialization" "No,Yes" newline bitfld.long 0x00 1. " CH1CL ,Channel 1 sound source initialization" "No,Yes" bitfld.long 0x00 0. " CH0CL ,Channel 0 sound source initialization" "No,Yes" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*") group.long 0x80++0x03 line.long 0x00 "WGINTREN,Waveform Generator Interrupt Enable Register" bitfld.long 0x00 12. " CH4END ,Channel 4 sound source generation end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CH3END ,Channel 3 sound source generation end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CH2END ,Channel 2 sound source generation end interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " CH1END ,Channel 1 sound source generation end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " CH0END ,Channel 0 sound source generation end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " AHBERR ,AHB MASTER INTERFACE bus error interrupt enable" "Disabled,Enabled" rgroup.long 0x84++0x03 line.long 0x00 "WGINTRSTATE,Waveform Generator Interrupt State Register" bitfld.long 0x00 12. " CH4END ,Channel 4 sound source generation end status indication" "No interrupt,Interrupt" bitfld.long 0x00 11. " CH3END ,Channel 3 sound source generation end status indication" "No interrupt,Interrupt" bitfld.long 0x00 10. " CH2END ,Channel 2 sound source generation end status indication" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " CH1END ,Channel 1 sound source generation end status indication" "No interrupt,Interrupt" bitfld.long 0x00 8. " CH0END ,Channel 0 sound source generation end status indication" "No interrupt,Interrupt" bitfld.long 0x00 0. " AHBERR ,AHB MASTER INTERFACE bus error status indication" "No interrupt,Interrupt" wgroup.long 0x88++0x03 line.long 0x00 "WGINTRCLR,Waveform Generator Interrupt Clear Register" bitfld.long 0x00 12. " CH4END ,Channel 4 sound source generation end interrupt clear" "No effect,Clear" bitfld.long 0x00 11. " CH3END ,Channel 3 sound source generation end interrupt clear" "No effect,Clear" bitfld.long 0x00 10. " CH2END ,Channel 2 sound source generation end interrupt clear" "No effect,Clear" newline bitfld.long 0x00 9. " CH1END ,Channel 1 sound source generation end interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " CH0END ,Channel 0 sound source generation end interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " AHBERR ,AHB MASTER INTERFACE bus error interrupt clear" "No effect,Clear" else group.long 0x84++0x03 line.long 0x00 "WGINTRSTATE_set/clr,Waveform Generator Interrupt Register" setclrfld.long 0x00 12. -0x04 12. 0x04 12. " CH4END ,Channel 4 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 11. -0x04 11. 0x04 11. " CH3END ,Channel 3 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 10. -0x04 10. 0x04 10. " CH2END ,Channel 2 sound source generation end interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x00 9. -0x04 9. 0x04 9. " CH1END ,Channel 1 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 8. -0x04 8. 0x04 8. " CH0END ,Channel 0 sound source generation end interrupt enable" "Disabled,Enabled" setclrfld.long 0x00 0. -0x04 0. 0x04 0. " AHBERR ,AHB MASTER INTERFACE bus error interrupt enable" "Disabled,Enabled" endif rgroup.long 0x90++0x03 line.long 0x00 "WGAHBERR,Waveform Generator AHB Bus Error Register" bitfld.long 0x00 0.--1. " AHBSERR ,SWFG AHB Slave Interface access error information indication" "No error,Address error,Write access,Access size" width 0x0B tree.end endif sif (cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J336*")) tree "SMIX (Sound Mixer)" base ad:0xB8020000 width 21. group.long 0x00++0x13 line.long 0x00 "MXCH,Mixer Channel Register" bitfld.long 0x00 9. " PMIS4 ,PMIS4 input setting" "Invalid,Valid" bitfld.long 0x00 8. " PMIS3 ,PMIS3 input setting" "Invalid,Valid" bitfld.long 0x00 7. " PMIS2 ,PMIS2 input setting" "Invalid,Valid" bitfld.long 0x00 6. " PMIS1 ,PMIS1 input setting" "Invalid,Valid" newline bitfld.long 0x00 5. " PMIS0 ,PMIS0 input setting" "Invalid,Valid" bitfld.long 0x00 4. " WFG4 ,WFG4 input setting" "Invalid,Valid" bitfld.long 0x00 3. " WFG3 ,WFG3 input setting" "Invalid,Valid" bitfld.long 0x00 2. " WFG2 ,WFG2 input setting" "Invalid,Valid" newline bitfld.long 0x00 1. " WFG1 ,WFG1 input setting" "Invalid,Valid" bitfld.long 0x00 0. " WFG0 ,WFG0 input setting" "Invalid,Valid" line.long 0x04 "MXOCTRL,Mixer Output Control Register" bitfld.long 0x04 8.--11. " DATATN ,Number of transfers to output destination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 0.--2. 0x01 " MACRO ,Output destination address" line.long 0x08 "MXDRQCTRL,Mixer Date Request Control Register" bitfld.long 0x08 28. " DMAENCH4 ,DMA transfer to PMIS4 request setting" "Disabled,Enabled" bitfld.long 0x08 27. " DMAENCH3 ,DMA transfer to PMIS3 request setting" "Disabled,Enabled" bitfld.long 0x08 26. " DMAENCH2 ,DMA transfer to PMIS2 request setting" "Disabled,Enabled" bitfld.long 0x08 25. " DMAENCH1 ,DMA transfer to PMIS1 request setting" "Disabled,Enabled" newline bitfld.long 0x08 24. " DMAENCH0 ,DMA transfer to PMIS0 request setting" "Disabled,Enabled" bitfld.long 0x08 16.--19. " FESTCH4 ,Data transfer to PMIS4 request assert threshold setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " FESTCH3 ,Data transfer to PMIS3 request assert threshold setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 08.--11. " FESTCH2 ,Data transfer to PMIS2 request assert threshold setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 04.--07. " FESTCH1 ,Data transfer to PMIS1 request assert threshold setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 00.--03. " FESTCH0 ,Data transfer to PMIS0 request assert threshold setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "MXICTRL,Mixer Input Control Register" bitfld.long 0x0C 16.--18. " PMIS4FREQ ,Input sampling frequency to PMIS4" "96KHz,48KHz,24KHz,12KHz,8KHz,4KHz,44.1KHz,?..." bitfld.long 0x0C 12.--14. " PMIS3FREQ ,Input sampling frequency to PMIS3" "96KHz,48KHz,24KHz,12KHz,8KHz,4KHz,44.1KHz,?..." bitfld.long 0x0C 08.--10. " PMIS2FREQ ,Input sampling frequency to PMIS2" "96KHz,48KHz,24KHz,12KHz,8KHz,4KHz,44.1KHz,?..." newline bitfld.long 0x0C 04.--06. " PMIS1FREQ ,Input sampling frequency to PMIS1" "96KHz,48KHz,24KHz,12KHz,8KHz,4KHz,44.1KHz,?..." bitfld.long 0x0C 00.--02. " PMIS0FREQ ,Input sampling frequency to PMIS0" "96KHz,48KHz,24KHz,12KHz,8KHz,4KHz,44.1KHz,?..." line.long 0x10 "MXCHMONO,Mixer Channel Monaural Register" bitfld.long 0x10 8.--9. " PMIS4MONO ,PMIS4 sound source processing mode setting" "Stereo,Monaural R,Monaural L,Monaural LR" bitfld.long 0x10 6.--7. " PMIS3MONO ,PMIS3 sound source processing mode setting" "Stereo,Monaural R,Monaural L,Monaural LR" bitfld.long 0x10 4.--5. " PMIS2MONO ,PMIS2 sound source processing mode setting" "Stereo,Monaural R,Monaural L,Monaural LR" newline bitfld.long 0x10 2.--3. " PMIS1MONO ,PMIS1 sound source processing mode setting" "Stereo,Monaural R,Monaural L,Monaural LR" bitfld.long 0x10 0.--1. " PMIS0MONO ,PMIS0 sound source processing mode setting" "Stereo,Monaural R,Monaural L,Monaural LR" group.long 0x20++0x23 line.long 0x00 "MXCHVOL1,Mixer Channel Volume1 Register" hexmask.long.byte 0x00 24.--31. 1. " WFG3VOL ,Gain setting for WFG3 volume control" hexmask.long.byte 0x00 16.--23. 1. " WFG2VOL ,Gain setting for WFG2 volume control" hexmask.long.byte 0x00 08.--15. 1. " WFG1VOL ,Gain setting for WFG1 volume control" hexmask.long.byte 0x00 00.--07. 1. " WFG0VOL ,Gain setting for WFG0 volume control" line.long 0x04 "MXCHVOL2,Mixer Channel Volume2 Register" hexmask.long.byte 0x04 24.--31. 1. " PMIS2VOL ,Gain setting for PMIS2VOL volume control" hexmask.long.byte 0x04 16.--23. 1. " PMIS1VOL ,Gain setting for PMIS1VOL volume control" hexmask.long.byte 0x04 08.--15. 1. " PMIS0VOL ,Gain setting for PMIS0VOL volume control" hexmask.long.byte 0x04 00.--07. 1. " WFG4VOL ,Gain setting for WFG4 volume control" line.long 0x08 "MXCHVOL3,Mixer Channel Volume3 Register" hexmask.long.byte 0x08 16.--23. 1. " MXDVOL ,Gain setting for mixed sound source volume control" hexmask.long.byte 0x08 08.--15. 1. " PMIS4VOL ,Gain setting for PMIS4VOL volume control" hexmask.long.byte 0x08 00.--07. 1. " PMIS3VOL ,Gain setting for PMIS3VOL volume control" line.long 0x0C "MXCHMUTE,Mixer Channel Mute Register" bitfld.long 0x0C 10. " MXDMUTE ,Mixed sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 9. " PMIS4MUTE ,PMIS4 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 8. " PMIS3MUTE ,PMIS3 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 7. " PMIS2MUTE ,PMIS2 input sound source MUTE setting" "Disabled,Enabled" newline bitfld.long 0x0C 6. " PMIS1MUTE ,PMIS1 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 5. " PMIS0MUTE ,PMIS0 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 4. " WFG4MUTE ,WFG4 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 3. " WFG3MUTE ,WFG3 input sound source MUTE setting" "Disabled,Enabled" newline bitfld.long 0x0C 2. " WFG2MUTE ,WFG2 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 1. " WFG1MUTE ,WFG1 input sound source MUTE setting" "Disabled,Enabled" bitfld.long 0x0C 0. " WFG0MUTE ,WFG0 input sound source MUTE setting" "Disabled,Enabled" line.long 0x10 "MXCHFADE1,Mixer Channel Fade_In/Out1 Register" bitfld.long 0x10 24.--28. " WFG1FADEOUT ,WFG1 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x10 16.--20. " WFG1FADEIN ,WFG1 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x10 8.--12. " WFG0FADEOUT ,WFG0 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x10 0.--4. " WFG0FADEIN ,WFG0 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" line.long 0x14 "MXCHFADE2,Mixer Channel Fade_In/Out2 Register" bitfld.long 0x14 24.--28. " WFG3FADEOUT ,WFG3 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x14 16.--20. " WFG3FADEIN ,WFG3 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x14 08.--12. " WFG2FADEOUT ,WFG2 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x14 00.--04. " WFG2FADEIN ,WFG2 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" line.long 0x18 "MXCHFADE3,Mixer Channel Fade_In/Out3 Register" bitfld.long 0x18 24.--28. " PMIS0FADEOUT ,PMIS0 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x18 16.--20. " PMIS0FADEIN ,PMIS0 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x18 08.--12. " WFG4FADEOUT ,WFG4 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x18 00.--04. " WFG4FADEIN ,WFG4 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" line.long 0x1C "MXCHFADE4,Mixer Channel Fade_In/Out4 Register" bitfld.long 0x1C 24.--28. " PMIS2FADEOUT ,PMIS2 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x1C 16.--20. " PMIS2FADEIN ,PMIS2 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x1C 08.--12. " PMIS1FADEOUT ,PMIS1 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x1C 00.--04. " PMIS1FADEIN ,PMIS1 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" line.long 0x20 "MXCHFADE5,Mixer Channel Fade_In/Out5 Register" bitfld.long 0x20 24.--28. " PMIS4FADEOUT ,PMIS4 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x20 16.--20. " PMIS4FADEIN ,PMIS4 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x20 08.--12. " PMIS3FADEOUT ,PMIS3 fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x20 00.--04. " PMIS3FADEIN ,PMIS3 fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" group.long 0x44++0x07 line.long 0x00 "MXMXDFADE,Mixer Mixed Fade_In/Out Register" bitfld.long 0x00 8.--12. " MXDFADEOUT ,Mixed sound source fade out time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" bitfld.long 0x00 0.--4. " MXDFADEIN ,Mixed sound source fade in time setting" "Not used,20ms,40ms,60ms,80ms,100ms,200ms,300ms,400ms,500ms,600ms,700ms,800ms,900ms,1000ms,1100ms,1200ms,1300ms,1400ms,1500ms,1600ms,1700ms,1800ms,1900ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms,2000ms" line.long 0x04 "MXCHFADEEN,Mixer Channel Fade_In/Out Enable Register" bitfld.long 0x04 20.--21. " MXDFADEEN ,Mixed sound source fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 18.--19. " PMIS4FADEEN ,PMIS4 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 16.--17. " PMIS3FADEEN ,PMIS3 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 14.--15. " PMIS2FADEEN ,PMIS2 fade in/out operation setting" "No fade,,Enable in,Enable out" newline bitfld.long 0x04 12.--13. " PMIS1FADEEN ,PMIS1 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 10.--11. " PMIS0FADEEN ,PMIS0 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 08.--09. " WFG4FADEEN ,WFG4 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 06.--07. " WFG3FADEEN ,WFG3 fade in/out operation setting" "No fade,,Enable in,Enable out" newline bitfld.long 0x04 04.--05. " WFG2FADEEN ,WFG2 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 02.--03. " WFG1FADEEN ,WFG1 fade in/out operation setting" "No fade,,Enable in,Enable out" bitfld.long 0x04 00.--01. " WFG0FADEEN ,WFG0 fade in/out operation setting" "No fade,,Enable in,Enable out" sif cpuis("S6J336*") group.long 0x4C++0x03 line.long 0x00 "MXPMISIPDC,Mixer Insert The PCM Data Control Register" bitfld.long 0x00 4. " PMISIPDC4 ,PMISIPDC4 input setting" "Disabled,Enabled" bitfld.long 0x00 3. " PMISIPDC3 ,PMISIPDC3 input setting" "Disabled,Enabled" bitfld.long 0x00 2. " PMISIPDC2 ,PMISIPDC2 input setting" "Disabled,Enabled" bitfld.long 0x00 1. " PMISIPDC1 ,PMISIPDC1 input setting" "Disabled,Enabled" newline bitfld.long 0x00 0. " PMISIPDC0 ,PMISIPDC0 input setting" "Disabled,Enabled" endif group.long 0x50++0x07 line.long 0x00 "MXBUFFCLR,Mixer Buffer Clear Register" bitfld.long 0x00 10. " OUTBCLR ,Output buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 9. " PMIS4BCLR ,PMIS4 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 8. " PMIS3BCLR ,PMIS3 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 7. " PMIS2BCLR ,PMIS2 input buffer initialization" "Not initialized,Initialized" newline bitfld.long 0x00 6. " PMIS1BCLR ,PMIS1 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 5. " PMIS0BCLR ,PMIS0 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 4. " WFG4BCLR ,WFG4 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 3. " WFG3BCLR ,WFG3 input buffer initialization" "Not initialized,Initialized" newline bitfld.long 0x00 2. " WFG2BCLR ,WFG2 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 1. " WFG1BCLR ,WFG1 input buffer initialization" "Not initialized,Initialized" bitfld.long 0x00 0. " WFG0BCLR ,WFG0 input buffer initialization" "Not initialized,Initialized" line.long 0x04 "MXFADECLR,Mixer FADE_In/Out Clear Register" bitfld.long 0x04 10. " MIXCLR ,Mixed data FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 9. " PMIS4CLR ,PMIS4 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 8. " PMIS3CLR ,PMIS3 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 7. " PMIS2CLR ,PMIS2 FADE state initialization" "Not initialized,Initialized" newline bitfld.long 0x04 6. " PMIS1CLR ,PMIS1 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 5. " PMIS0CLR ,PMIS0 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 4. " WFG4CLR ,WFG4 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 3. " WFG3CLR ,WFG3 FADE state initialization" "Not initialized,Initialized" newline bitfld.long 0x04 2. " WFG2CLR ,WFG2 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 1. " WFG1CLR ,WFG1 FADE state initialization" "Not initialized,Initialized" bitfld.long 0x04 0. " WFG0CLR ,WFG0 FADE state initialization" "Not initialized,Initialized" group.long 0x64++0x03 line.long 0x00 "MXINTRSTATE_SET/CLR,Mixer Interrupt Status Register" setclrfld.long 0x00 31. -0x04 31. 0x04 31. " AHBERR ,AHB Master interface bus error indication" "No error,Error" setclrfld.long 0x00 28. -0x04 28. 0x04 28. " PMIS4DMAERR ,PMIS4DMA transfer error indication" "No error,Error" setclrfld.long 0x00 27. -0x04 27. 0x04 27. " PMIS3DMAERR ,PMIS3DMA transfer error indication" "No error,Error" setclrfld.long 0x00 26. -0x04 26. 0x04 26. " PMIS2DMAERR ,PMIS2DMA transfer error indication" "No error,Error" newline setclrfld.long 0x00 25. -0x04 25. 0x04 25. " PMIS1DMAERR ,PMIS1DMA transfer error indication" "No error,Error" setclrfld.long 0x00 24. -0x04 24. 0x04 24. " PMIS0DMAERR ,PMIS0DMA transfer error indication" "No error,Error" setclrfld.long 0x00 12. -0x04 12. 0x04 12. " PMIS4BUFOVFL ,PMIS4 input buffer overflow error indication" "No error,Error" setclrfld.long 0x00 11. -0x04 11. 0x04 11. " PMIS3BUFOVFL ,PMIS3 input buffer overflow error indication" "No error,Error" newline setclrfld.long 0x00 10. -0x04 10. 0x04 10. " PMIS2BUFOVFL ,PMIS2 input buffer overflow error indication" "No error,Error" setclrfld.long 0x00 9. -0x04 9. 0x04 9. " PMIS1BUFOVFL ,PMIS1 input buffer overflow error indication" "No error,Error" setclrfld.long 0x00 8. -0x04 8. 0x04 8. " PMIS0BUFOVFL ,PMIS0 input buffer overflow error indication" "No error,Error" setclrfld.long 0x00 4. -0x04 4. 0x04 4. " PMIS4BUFDREQ ,PMIS4 data transfer request indication" "Not requested,Requested" newline setclrfld.long 0x00 3. -0x04 3. 0x04 3. " PMIS3BUFDREQ ,PMIS3 data transfer request indication" "Not requested,Requested" setclrfld.long 0x00 2. -0x04 2. 0x04 2. " PMIS2BUFDREQ ,PMIS2 data transfer request indication" "Not requested,Requested" setclrfld.long 0x00 1. -0x04 1. 0x04 1. " PMIS1BUFDREQ ,PMIS1 data transfer request indication" "Not requested,Requested" setclrfld.long 0x00 0. -0x04 0. 0x04 0. " PMIS0BUFDREQ ,PMIS0 data transfer request indication" "Not requested,Requested" rgroup.long 0x70++0x13 line.long 0x00 "MXINBUFFCNT1,Mixer Input Buffer Count1 Register" hexmask.long.byte 0x00 24.--29. 1. " PMIS2CNT ,PMIS2 input buffer used volume indication" hexmask.long.byte 0x00 16.--21. 1. " PMIS1CNT ,PMIS1 input buffer used volume indication" hexmask.long.byte 0x00 8.--13. 1. " PMIS0CNT ,PMIS0 input buffer used volume indication" bitfld.long 0x00 4. " WFG4C ,WFG4 input data present/not present indication" "Without data,With data" newline bitfld.long 0x00 3. " WFG3C ,WFG3 input data present/not present indication" "Without data,With data" bitfld.long 0x00 2. " WFG2C ,WFG2 input data present/not present indication" "Without data,With data" bitfld.long 0x00 1. " WFG1C ,WFG1 input data present/not present indication" "Without data,With data" bitfld.long 0x00 0. " WFG0C ,WFG0 input data present/not present indication" "Without data,With data" line.long 0x04 "MXINBUFFCNT2,Mixer Input Buffer Count2 Register" hexmask.long.byte 0x04 8.--13. 1. " PMIS4CNT ,Input buffer used volume indication" hexmask.long.byte 0x04 0.--5. 1. " PMIS3CNT ,Input buffer used volume indication" line.long 0x08 "MXCHBUFFCNT,Mixer Channel Buffer Count Register" hexmask.long.byte 0x08 24.--27. 1. " PMIS4CNT ,PMIS4 internal buffer used volume indication" hexmask.long.byte 0x08 20.--23. 1. " PMIS3CNT ,PMIS3 internal buffer used volume indication" hexmask.long.byte 0x08 16.--19. 1. " PMIS2CNT ,PMIS2 internal buffer used volume indication" hexmask.long.byte 0x08 12.--15. 1. " PMIS1CNT ,PMIS1 internal buffer used volume indication" newline hexmask.long.byte 0x08 08.--11. 1. " PMIS0CNT ,PMIS0 internal buffer used volume indication" bitfld.long 0x08 4. " WFG4C ,WFG4 internal buffer used volume indication" "0,1" bitfld.long 0x08 3. " WFG3C ,WFG3 internal buffer used volume indication" "0,1" bitfld.long 0x08 2. " WFG2C ,WFG2 internal buffer used volume indication" "0,1" newline bitfld.long 0x08 1. " WFG1C ,WFG1 internal buffer used volume indication" "0,1" bitfld.long 0x08 0. " WFG0C ,WFG0 internal buffer used volume indication" "0,1" line.long 0x0C "MXOUTBUFFCNT,Mixer Output Buffer Count Register" hexmask.long.byte 0x0C 0.--5. 1. " OUTCNT ,Output buffer used volume indication" line.long 0x10 "MXAHBERR,Mixer AHB Bus Error Register" bitfld.long 0x10 20.--21. " CNTREGERR ,AHB Slave interface register access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 18.--19. " PMIS4ERR ,AHB Slave interface PMIS4 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 16.--17. " PMIS3ERR ,AHB Slave interface PMIS3 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 14.--15. " PMIS2ERR ,AHB Slave interface PMIS2 transfer access error information indication" "No error,Address error,W access to RO,Access size error" newline bitfld.long 0x10 12.--13. " PMIS1ERR ,AHB Slave interface PMIS1 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 10.--11. " PMIS0ERR ,AHB Slave interface PMIS0 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 8.--9. " WFG4ERR ,AHB Slave interface WFG4 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 6.--7. " WFG3ERR ,AHB Slave interface WFG3 transfer access error information indication" "No error,Address error,W access to RO,Access size error" newline bitfld.long 0x10 4.--5. " WFG2ERR ,AHB Slave interface WFG2 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 2.--3. " WFG1ERR ,AHB Slave interface WFG1 transfer access error information indication" "No error,Address error,W access to RO,Access size error" bitfld.long 0x10 0.--1. " WFG0ERR ,AHB Slave interface WFG0 transfer access error information indication" "No error,Address error,W access to RO,Access size error" width 15. wgroup.long 0x100++0x03 line.long 0x00 "MXWFG0DADR,Mixer WFG0 Data Address Register" wgroup.long 0x104++0x03 line.long 0x00 "MXWFG1DADR,Mixer WFG1 Data Address Register" wgroup.long 0x108++0x03 line.long 0x00 "MXWFG2DADR,Mixer WFG2 Data Address Register" wgroup.long 0x10C++0x03 line.long 0x00 "MXWFG3DADR,Mixer WFG3 Data Address Register" wgroup.long 0x110++0x03 line.long 0x00 "MXWFG4DADR,Mixer WFG4 Data Address Register" wgroup.long 0x200++0x03 line.long 0x00 "MXPMIS0DADR0,Mixer PCM/I2S 0 Data Address Register0" wgroup.long 0x204++0x03 line.long 0x00 "MXPMIS0DADR1,Mixer PCM/I2S 0 Data Address Register1" wgroup.long 0x208++0x03 line.long 0x00 "MXPMIS0DADR2,Mixer PCM/I2S 0 Data Address Register2" wgroup.long 0x20C++0x03 line.long 0x00 "MXPMIS0DADR3,Mixer PCM/I2S 0 Data Address Register3" wgroup.long 0x210++0x03 line.long 0x00 "MXPMIS0DADR4,Mixer PCM/I2S 0 Data Address Register4" wgroup.long 0x214++0x03 line.long 0x00 "MXPMIS0DADR5,Mixer PCM/I2S 0 Data Address Register5" wgroup.long 0x218++0x03 line.long 0x00 "MXPMIS0DADR6,Mixer PCM/I2S 0 Data Address Register6" wgroup.long 0x21C++0x03 line.long 0x00 "MXPMIS0DADR7,Mixer PCM/I2S 0 Data Address Register7" wgroup.long 0x220++0x03 line.long 0x00 "MXPMIS0DADR8,Mixer PCM/I2S 0 Data Address Register8" wgroup.long 0x224++0x03 line.long 0x00 "MXPMIS0DADR9,Mixer PCM/I2S 0 Data Address Register9" wgroup.long 0x228++0x03 line.long 0x00 "MXPMIS0DADR10,Mixer PCM/I2S 0 Data Address Register10" wgroup.long 0x22C++0x03 line.long 0x00 "MXPMIS0DADR11,Mixer PCM/I2S 0 Data Address Register11" wgroup.long 0x230++0x03 line.long 0x00 "MXPMIS0DADR12,Mixer PCM/I2S 0 Data Address Register12" wgroup.long 0x234++0x03 line.long 0x00 "MXPMIS0DADR13,Mixer PCM/I2S 0 Data Address Register13" wgroup.long 0x238++0x03 line.long 0x00 "MXPMIS0DADR14,Mixer PCM/I2S 0 Data Address Register14" wgroup.long 0x23C++0x03 line.long 0x00 "MXPMIS0DADR15,Mixer PCM/I2S 0 Data Address Register15" wgroup.long 0x240++0x03 line.long 0x00 "MXPMIS1DADR0,Mixer PCM/I2S 1 Data Address Register0" wgroup.long 0x244++0x03 line.long 0x00 "MXPMIS1DADR1,Mixer PCM/I2S 1 Data Address Register1" wgroup.long 0x248++0x03 line.long 0x00 "MXPMIS1DADR2,Mixer PCM/I2S 1 Data Address Register2" wgroup.long 0x24C++0x03 line.long 0x00 "MXPMIS1DADR3,Mixer PCM/I2S 1 Data Address Register3" wgroup.long 0x250++0x03 line.long 0x00 "MXPMIS1DADR4,Mixer PCM/I2S 1 Data Address Register4" wgroup.long 0x254++0x03 line.long 0x00 "MXPMIS1DADR5,Mixer PCM/I2S 1 Data Address Register5" wgroup.long 0x258++0x03 line.long 0x00 "MXPMIS1DADR6,Mixer PCM/I2S 1 Data Address Register6" wgroup.long 0x25C++0x03 line.long 0x00 "MXPMIS1DADR7,Mixer PCM/I2S 1 Data Address Register7" wgroup.long 0x260++0x03 line.long 0x00 "MXPMIS1DADR8,Mixer PCM/I2S 1 Data Address Register8" wgroup.long 0x264++0x03 line.long 0x00 "MXPMIS1DADR9,Mixer PCM/I2S 1 Data Address Register9" wgroup.long 0x268++0x03 line.long 0x00 "MXPMIS1DADR10,Mixer PCM/I2S 1 Data Address Register10" wgroup.long 0x26C++0x03 line.long 0x00 "MXPMIS1DADR11,Mixer PCM/I2S 1 Data Address Register11" wgroup.long 0x270++0x03 line.long 0x00 "MXPMIS1DADR12,Mixer PCM/I2S 1 Data Address Register12" wgroup.long 0x274++0x03 line.long 0x00 "MXPMIS1DADR13,Mixer PCM/I2S 1 Data Address Register13" wgroup.long 0x278++0x03 line.long 0x00 "MXPMIS1DADR14,Mixer PCM/I2S 1 Data Address Register14" wgroup.long 0x27C++0x03 line.long 0x00 "MXPMIS1DADR15,Mixer PCM/I2S 1 Data Address Register15" wgroup.long 0x280++0x03 line.long 0x00 "MXPMIS2DADR0,Mixer PCM/I2S 2 Data Address Register0" wgroup.long 0x284++0x03 line.long 0x00 "MXPMIS2DADR1,Mixer PCM/I2S 2 Data Address Register1" wgroup.long 0x288++0x03 line.long 0x00 "MXPMIS2DADR2,Mixer PCM/I2S 2 Data Address Register2" wgroup.long 0x28C++0x03 line.long 0x00 "MXPMIS2DADR3,Mixer PCM/I2S 2 Data Address Register3" wgroup.long 0x290++0x03 line.long 0x00 "MXPMIS2DADR4,Mixer PCM/I2S 2 Data Address Register4" wgroup.long 0x294++0x03 line.long 0x00 "MXPMIS2DADR5,Mixer PCM/I2S 2 Data Address Register5" wgroup.long 0x298++0x03 line.long 0x00 "MXPMIS2DADR6,Mixer PCM/I2S 2 Data Address Register6" wgroup.long 0x29C++0x03 line.long 0x00 "MXPMIS2DADR7,Mixer PCM/I2S 2 Data Address Register7" wgroup.long 0x2A0++0x03 line.long 0x00 "MXPMIS2DADR8,Mixer PCM/I2S 2 Data Address Register8" wgroup.long 0x2A4++0x03 line.long 0x00 "MXPMIS2DADR9,Mixer PCM/I2S 2 Data Address Register9" wgroup.long 0x2A8++0x03 line.long 0x00 "MXPMIS2DADR10,Mixer PCM/I2S 2 Data Address Register10" wgroup.long 0x2AC++0x03 line.long 0x00 "MXPMIS2DADR11,Mixer PCM/I2S 2 Data Address Register11" wgroup.long 0x2B0++0x03 line.long 0x00 "MXPMIS2DADR12,Mixer PCM/I2S 2 Data Address Register12" wgroup.long 0x2B4++0x03 line.long 0x00 "MXPMIS2DADR13,Mixer PCM/I2S 2 Data Address Register13" wgroup.long 0x2B8++0x03 line.long 0x00 "MXPMIS2DADR14,Mixer PCM/I2S 2 Data Address Register14" wgroup.long 0x2BC++0x03 line.long 0x00 "MXPMIS2DADR15,Mixer PCM/I2S 2 Data Address Register15" wgroup.long 0x2C0++0x03 line.long 0x00 "MXPMIS3DADR0,Mixer PCM/I2S 3 Data Address Register0" wgroup.long 0x2C4++0x03 line.long 0x00 "MXPMIS3DADR1,Mixer PCM/I2S 3 Data Address Register1" wgroup.long 0x2C8++0x03 line.long 0x00 "MXPMIS3DADR2,Mixer PCM/I2S 3 Data Address Register2" wgroup.long 0x2CC++0x03 line.long 0x00 "MXPMIS3DADR3,Mixer PCM/I2S 3 Data Address Register3" wgroup.long 0x2D0++0x03 line.long 0x00 "MXPMIS3DADR4,Mixer PCM/I2S 3 Data Address Register4" wgroup.long 0x2D4++0x03 line.long 0x00 "MXPMIS3DADR5,Mixer PCM/I2S 3 Data Address Register5" wgroup.long 0x2D8++0x03 line.long 0x00 "MXPMIS3DADR6,Mixer PCM/I2S 3 Data Address Register6" wgroup.long 0x2DC++0x03 line.long 0x00 "MXPMIS3DADR7,Mixer PCM/I2S 3 Data Address Register7" wgroup.long 0x2E0++0x03 line.long 0x00 "MXPMIS3DADR8,Mixer PCM/I2S 3 Data Address Register8" wgroup.long 0x2E4++0x03 line.long 0x00 "MXPMIS3DADR9,Mixer PCM/I2S 3 Data Address Register9" wgroup.long 0x2E8++0x03 line.long 0x00 "MXPMIS3DADR10,Mixer PCM/I2S 3 Data Address Register10" wgroup.long 0x2EC++0x03 line.long 0x00 "MXPMIS3DADR11,Mixer PCM/I2S 3 Data Address Register11" wgroup.long 0x2F0++0x03 line.long 0x00 "MXPMIS3DADR12,Mixer PCM/I2S 3 Data Address Register12" wgroup.long 0x2F4++0x03 line.long 0x00 "MXPMIS3DADR13,Mixer PCM/I2S 3 Data Address Register13" wgroup.long 0x2F8++0x03 line.long 0x00 "MXPMIS3DADR14,Mixer PCM/I2S 3 Data Address Register14" wgroup.long 0x2FC++0x03 line.long 0x00 "MXPMIS3DADR15,Mixer PCM/I2S 3 Data Address Register15" wgroup.long 0x300++0x03 line.long 0x00 "MXPMIS4DADR0,Mixer PCM/I2S 4 Data Address Register0" wgroup.long 0x304++0x03 line.long 0x00 "MXPMIS4DADR1,Mixer PCM/I2S 4 Data Address Register1" wgroup.long 0x308++0x03 line.long 0x00 "MXPMIS4DADR2,Mixer PCM/I2S 4 Data Address Register2" wgroup.long 0x30C++0x03 line.long 0x00 "MXPMIS4DADR3,Mixer PCM/I2S 4 Data Address Register3" wgroup.long 0x310++0x03 line.long 0x00 "MXPMIS4DADR4,Mixer PCM/I2S 4 Data Address Register4" wgroup.long 0x314++0x03 line.long 0x00 "MXPMIS4DADR5,Mixer PCM/I2S 4 Data Address Register5" wgroup.long 0x318++0x03 line.long 0x00 "MXPMIS4DADR6,Mixer PCM/I2S 4 Data Address Register6" wgroup.long 0x31C++0x03 line.long 0x00 "MXPMIS4DADR7,Mixer PCM/I2S 4 Data Address Register7" wgroup.long 0x320++0x03 line.long 0x00 "MXPMIS4DADR8,Mixer PCM/I2S 4 Data Address Register8" wgroup.long 0x324++0x03 line.long 0x00 "MXPMIS4DADR9,Mixer PCM/I2S 4 Data Address Register9" wgroup.long 0x328++0x03 line.long 0x00 "MXPMIS4DADR10,Mixer PCM/I2S 4 Data Address Register10" wgroup.long 0x32C++0x03 line.long 0x00 "MXPMIS4DADR11,Mixer PCM/I2S 4 Data Address Register11" wgroup.long 0x330++0x03 line.long 0x00 "MXPMIS4DADR12,Mixer PCM/I2S 4 Data Address Register12" wgroup.long 0x334++0x03 line.long 0x00 "MXPMIS4DADR13,Mixer PCM/I2S 4 Data Address Register13" wgroup.long 0x338++0x03 line.long 0x00 "MXPMIS4DADR14,Mixer PCM/I2S 4 Data Address Register14" wgroup.long 0x33C++0x03 line.long 0x00 "MXPMIS4DADR15,Mixer PCM/I2S 4 Data Address Register15" width 0x0B tree.end endif sif (!cpuis("S6J334*")&&!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "EMAC (Ethernet MAC)" base ad:0xB8000000 width 35. group.long 0x00++0x07 line.long 0x00 "NETWORK_CONTROL,Network Control Register" bitfld.long 0x00 25. " PFC_CTRL ,Enable multiple PFC pause quanta" "Disabled,Enabled" bitfld.long 0x00 24. " ONE_STEP_SYNC_MODE ,IEEE 1588 timer one step sync mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " STORE_UDP_OFFSET ,Store UDP/TCP offset" "Not stored,Stored" bitfld.long 0x00 20. " PTP_UNICAST_ENA ,PTP unicast frames enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TX_LPI_EN ,LPI transmission enable" "Disabled,Enabled" bitfld.long 0x00 18. " FLUSH_RX_PKT_CLK ,Flush next packet from external RX DPRAM" "No effect,Flush" newline bitfld.long 0x00 17. " TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME ,pause frame takes the values stored in the transmit PFC pause register" "No,Yes" bitfld.long 0x00 16. " PFC_ENABLE ,Enable PFC priority based pause reception" "Disabled,Enabled" newline bitfld.long 0x00 15. " STORE_RX_TS ,Store receive time stamp enable" "Disabled,Enabled" bitfld.long 0x00 14. " STATS_READ_SNAP ,Read snapshot (value to be read back)" "Current value,Snapshot value" newline bitfld.long 0x00 13. " STATS_TAKE_SNAP ,Take snapshot" "No effect,Snapshot" bitfld.long 0x00 12. " TX_PAUSE_FRAME_ZERO ,Transmit zero quantum pause frame" "No effect,Transmit" newline bitfld.long 0x00 11. " TX_PAUSE_FRAME_REQ ,Transmit pause frame" "No effect,Transmit" bitfld.long 0x00 10. " TX_HALT_CLK ,Transmit halt" "No effect,Halt" newline bitfld.long 0x00 9. " TX_START_CLK ,Transmit start" "No effect,Start" bitfld.long 0x00 8. " BACK_PRESSURE ,Back pressure force" "No effect,Force" newline bitfld.long 0x00 7. " STATS_WRITE_EN ,Write enable for statistics register" "Disabled,Enabled" bitfld.long 0x00 6. " INC_ALL_STATS_REGS ,Increment statistics register" "No effect,Increment" newline bitfld.long 0x00 5. " CLEAR_ALL_STATS_REGS ,Clear statistics register" "No effect,Clear" bitfld.long 0x00 4. " MAN_PORT_EN ,Management port enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " ENABLE_TRANSMIT ,Transmit enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLE_RECEIVE ,Receive enable" "Disabled,Enabled" line.long 0x04 "NETWORK_CONFIGURATION,Network Configuration Register" bitfld.long 0x04 30. " IGNORE_IPG_RX_ER ,Ignore IPG RX_ER" "Not ignored,Ignored" bitfld.long 0x04 29. " NSP_CHANGE ,Receive bad preamble" "No,Yes" newline bitfld.long 0x04 28. " IPG_STRETCH_ENABLE ,IPG stretch enable" "Disabled,Enabled" bitfld.long 0x04 26. " IGNORE_RX_FCS ,Ignore RX FCS" "Not ignored,Ignored" newline bitfld.long 0x04 24. " RECEIVE_CHECKSUM_OFFLOAD_ENABLE ,Receive checksum offload enable" "Disabled,Enabled" bitfld.long 0x04 23. " DISABLE_COPY_OF_PAUSE_FRAMES ,Disable copy of pause frames" "No,Yes" newline bitfld.long 0x04 21.--22. " DATA_BUS_WIDTH ,Data bus width select" ",64-bit AMBA AXI,?..." bitfld.long 0x04 18.--20. " MDC_CLOCK_DIVISION ,MDC clock division" "/8,/16,/32,/48,/64,/96,/128,/224" newline bitfld.long 0x04 17. " FCS_REMOVE ,FCS remove enable" "Disabled,Enabled" bitfld.long 0x04 16. " LENGTH_FIELD_ERROR_FRAME_DISCARD ,Length field error frame discard enable" "Disabled,Enabled" newline bitfld.long 0x04 14.--15. " RECEIVE_BUFFER_OFFSET ,Receive buffer offset" "No offset,One byte,Two byte,Three byte" bitfld.long 0x04 13. " PAUSE_ENABLE ,Pause enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " RETRY_TEST ,Retry test" "No,Yes" bitfld.long 0x04 8. " RECEIVE_1536_BYTE_FRAMES ,Receive 1536 byte frames enable" "Disabled,Enabled" newline bitfld.long 0x04 7. " UNICAST_HASH_ENABLE ,Unicast hash enable" "Disabled,Enabled" bitfld.long 0x04 6. " MULTICAST_HASH_ENABLE ,Multicast hash enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " NO_BROADCAST ,No broadcast" "No,Yes" bitfld.long 0x04 4. " COPY_ALL_FRAMES ,Copy all frames" "No,Yes" newline bitfld.long 0x04 3. " JUMBO_FRAMES ,Jumbo frames acceptance enable" "Disabled,Enabled" bitfld.long 0x04 2. " DISCARD_NON_VLAN_FRAMES ,Allow non-VLAN frames" "No,Yes" newline bitfld.long 0x04 1. " FULL_DUPLEX ,Full duplex enable" ",Enabled" bitfld.long 0x04 0. " SPEED ,Speed" ",100Mbps" rgroup.long 0x08++0x03 line.long 0x00 "NETWORK_STATUS,Network Status Register" bitfld.long 0x00 7. " LPI_INDICATE_CLK ,Low-power idle has been detected on receive" "Not detected,Detected" bitfld.long 0x00 6. " PFC_NEGOTIATE_CLK ,PFC priority based pause has been negotiated" "Not negotiated,Negotiated" newline bitfld.long 0x00 2. " MAN_DONE ,Management done" "Not done,Done" bitfld.long 0x00 1. " MDIO_IN ,MDIO_IN status" "Low,High" group.long 0x10++0x13 line.long 0x00 "DMA_CONFIG,DMA Configuration Register" bitfld.long 0x00 30. " DMA_ADDR_BUS_WIDTH ,DMA address bus width" "32-bit,?..." bitfld.long 0x00 29. " TX_BD_EXTENDED_MODE_EN ,Enable TX extended BD mode" "Disabled,Enabled" newline bitfld.long 0x00 28. " RX_BD_EXTENDED_MODE_EN ,Enable RX extended BD mode" "Disabled,Enabled" bitfld.long 0x00 26. " FORCE_MAX_AMBA_BURST_TX ,Force maximum length bursts on TX" "Not forced,Forced" newline bitfld.long 0x00 25. " FORCE_MAX_AMBA_BURST_RX ,Force maximum length bursts on RX" "Not forced,Forced" bitfld.long 0x00 24. " FORCE_DISCARD_ON_ERR ,Force auto discard RX packets during lack of resource" "Not forced,Forced" newline hexmask.long.byte 0x00 16.--23. 1. " RX_BUF_SIZE ,DMA receive buffer size in system memory" bitfld.long 0x00 11. " TX_PBUF_TCP_EN ,Transmitter IP/TCP and UDP checksum generation offload enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " TX_PBUF_SIZE ,Transmitter packet buffer memory size select" "8 Kbytes,16 Kbytes" bitfld.long 0x00 8.--9. " RX_PBUF_SIZE ,Receiver packet buffer memory size select" "512 bytes,1 Kbyte,2 Kbytes,4 Kbytes" newline bitfld.long 0x00 0.--4. " AMBA_BURST_LENGTH ,AMBA burst length (data transfers)" "Auto optimized,SINGLE,SINGLE,SINGLE,Up to 4,Up to 4,Up to 4,Up to 4,Up to 8,Up to 8,Up to 8,Up to 8,Up to 8,Up to 8,Up to 8,Up to 8,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16,Up to 16" line.long 0x04 "TRANSMIT_STATUS,Transmit Status Register" eventfld.long 0x04 8. " RESP_NOT_OK ,Response not OK" "No,Yes" eventfld.long 0x04 7. " LATE_COLLISION_OCCURRED ,Late collision occurred" "Not occurred,Occurred" newline eventfld.long 0x04 6. " TRANSMIT_UNDER_RUN ,Transmit underrun" "No underrun,Underrun" eventfld.long 0x04 5. " TRANSMIT_COMPLETE ,Transmit complete" "Not completed,Completed" newline eventfld.long 0x04 4. " AMBA_ERROR ,Transmit frame corruption due to AMBA (AXI) errors" "No error,Error" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") rbitfld.long 0x04 3. " TRANSMIT_GO ,Transmit ongoing" "Not in progress,In progress" else eventfld.long 0x04 3. " TRANSMIT_GO ,Transmit ongoing" "Not in progress,In progress" endif newline eventfld.long 0x04 2. " MAN_DONE ,Management done" "Not done,Done" eventfld.long 0x04 1. " MDIO_IN ,MDIO_IN status" "Low,High" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") newline eventfld.long 0x04 0. " USED_BIT_READ,Used bit read" "Not read,Read" endif line.long 0x08 "RECEIVE_Q_PTR,RX Buffer Queue Base Address Register" hexmask.long 0x08 2.--31. 0x04 " DMA_RX_Q_PTR ,Receive buffer queue base address" line.long 0x0C "TRANSMIT_Q_PTR,TX Buffer Queue Base Address Register" hexmask.long 0x0C 2.--31. 0x04 " DMA_TX_Q_PTR ,Transmit buffer queue base address" line.long 0x10 "RECEIVE_STATUS,Receive Status Register" eventfld.long 0x10 3. " RESP_NOT_OK ,BRESP not OK" "No,Yes" eventfld.long 0x10 2. " RECEIVE_OVERRUN ,Receive overrun" "No overrun,Overrun" newline eventfld.long 0x10 1. " FRAME_RECEIVED ,Frame received" "Not received,Received" eventfld.long 0x10 0. " BUFFER_NOT_AVAILABLE ,Buffer not available" "No,Yes" newline sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") group.long 0x24++0x03 line.long 0x00 "INT_STATUS,Interrupt Status Register" eventfld.long 0x00 29. " TSU_TIMER_COMPARISON_INTERRUPT ,IEEE 1588 timer comparison interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE ,Receive LPI indication status bit change" "No interrupt,Interrupt" newline eventfld.long 0x00 26. " TSU_SECONDS_REGISTER_INCREMENT ,IEEE 1588 Timer seconds register increment" "No interrupt,Interrupt" eventfld.long 0x00 25. " PTP_PDELAY_RESP_FRAME_TRANSMITTED ,PTP pdelay_resp frame transmitted" "No interrupt,Interrupt" newline eventfld.long 0x00 24. " PTP_PDELAY_REQ_FRAME_TRANSMITTED ,PTP Pdelay_Req frame transmitted" "No interrupt,Interrupt" eventfld.long 0x00 23. " PTP_PDELAY_RESP_FRAME_RECEIVED ,PTP Pdelay_Resp frame received" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " PTP_PDELAY_REQ_FRAME_RECEIVED ,PTP Pdelay_Req frame received" "No interrupt,Interrupt" eventfld.long 0x00 21. " PTP_SYNC_FRAME_TRANSMITTED ,PTP Sync frame transmitted" "No interrupt,Interrupt" newline eventfld.long 0x00 20. " PTP_DELAY_REQ_FRAME_TRANSMITTED ,PTP Delay_Req frame transmitted" "No interrupt,Interrupt" eventfld.long 0x00 19. " PTP_SYNC_FRAME_RECEIVED ,PTP sync frame received" "No interrupt,Interrupt" newline eventfld.long 0x00 18. " PTP_DELAY_REQ_FRAME_RECEIVED ,PTP Delay_Req frame received" "No interrupt,Interrupt" eventfld.long 0x00 14. " PAUSE_FRAME_TRANSMITTED ,Pause frame transmitted" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " PAUSE_TIME_ELAPSED ,Pause time elapsed" "No interrupt,Interrupt" eventfld.long 0x00 12. " PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED ,Pause frame with non-zero pause quantum received" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" eventfld.long 0x00 10. " RECEIVE_OVERRUN ,Receive overrun" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" eventfld.long 0x00 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " RETRY_LIMIT_EXCEEDED ,Retry limit exceeded" "No interrupt,Interrupt" eventfld.long 0x00 3. " TX_USED_BIT_READ ,TX used bit read" "No interrupt,Interrupt" newline eventfld.long 0x00 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" eventfld.long 0x00 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" newline eventfld.long 0x00 0. " MANAGEMENT_FRAME_SENT ,Management frame sent" "No interrupt,Interrupt" group.long 0x30++0x03 line.long 0x00 "INT_MASK,Interrupt Mask Register" setclrfld.long 0x00 29. -0x04 29. -0x08 29. " TSU_TIMER_COMPARISON_MASK ,IEEE 1588 Timer comparison interrupt mask" "Not masked,Masked" rbitfld.long 0x00 28. " WOL_EVENT_RECEIVED_MASK ,WOL event received mask" "Not masked,Masked" newline setclrfld.long 0x00 27. -0x04 27. -0x08 27. " RX_LPI_INDICATION_MASK ,Receive LPI Indication Status Bit change mask" "Not masked,Masked" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " TSU_SECONDS_REGISTER_INCREMENT_MASK ,IEEE 1588 Timer Seconds register increment mask" "Not masked,Masked" newline setclrfld.long 0x00 25. -0x04 25. -0x08 25. " PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK ,PTP Pdelay_Resp frame transmitted mask" "Not masked,Masked" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK ,PTP Pdelay_Req frame transmitted mask" "Not masked,Masked" newline setclrfld.long 0x00 23. -0x04 23. -0x08 23. " PTP_PDELAY_RESP_FRAME_RECEIVED_MASK ,PTP Pdelay_Resp frame received mask" "Not masked,Masked" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " PTP_PDELAY_REQ_FRAME_RECEIVED_MASK ,PTP Pdelay_Req frame received mask" "Not masked,Masked" newline setclrfld.long 0x00 21. -0x04 21. -0x08 21. " PTP_SYNC_FRAME_TRANSMITTED_MASK ,PTP Sync frame transmitted mask" "Not masked,Masked" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK ,PTP Delay_Req frame transmitted mask" "Not masked,Masked" newline setclrfld.long 0x00 19. -0x04 19. -0x08 19. " PTP_SYNC_FRAME_RECEIVED_MASK ,PTP Sync frame received mask" "Not masked,Masked" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " PTP_DELAY_REQ_FRAME_RECEIVED_MASK ,PTP Delay_Req frame received mask" "Not masked,Masked" newline rbitfld.long 0x00 17. " PCS_LINK_PARTNER_PAGE_MASK ,PCS link partner page mask" "Not masked,Masked" rbitfld.long 0x00 16. " PCS_AUTO_NEG_COMPLETE_INT_MASK ,PCS auto-negotiation complete interrupt mask" "Not masked,Masked" newline rbitfld.long 0x00 15. " EXTERNAL_INT_MASK ,External interrupt mask" "Not masked,Masked" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " PAUSE_FRAME_TRANSMITTED_MASK ,Pause frame transmitted mask" "Not masked,Masked" newline setclrfld.long 0x00 13. -0x04 13. -0x08 13. " PAUSE_TIME_ZERO_INT_MASK ,Pause time zero interrupt mask" "Not masked,Masked" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED_MASK ,Pause frame with non-zero pause quantum received mask" "Not masked,Masked" newline setclrfld.long 0x00 11. -0x04 11. -0x08 11. " RESP_NOT_OK_MASK ,BRESP not OK mask" "Not masked,Masked" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " RECEIVE_OVERRUN_MASK ,Receive overrun mask" "Not masked,Masked" newline rbitfld.long 0x00 9. " LINK_CHANGE_INT_MASK ,Link change interrupt mask" "Not masked,Masked" setclrfld.long 0x00 7. -0x04 7. -0x08 7. " TRANSMIT_COMPLETE_MASK ,Transmit complete mask" "Not masked,Masked" newline setclrfld.long 0x00 6. -0x04 6. -0x08 6. " AMBA_ERROR_MASK ,Transmit frame corruption due to AMBA AXI error mask" "Not masked,Masked" setclrfld.long 0x00 5. -0x04 5. -0x08 5. " RETRY_LIMIT_EXCEEDED_MASK ,Retry limit exceeded mask" "Not masked,Masked" newline rbitfld.long 0x00 4. " TRANSMIT_BUF_UNDER_RUN_INT_MASK ,Transmit buffer under run interrupt mask" "Not masked,Masked" setclrfld.long 0x00 3. -0x04 3. -0x08 3. " TX_USED_BIT_READ_MASK ,TX used bit read mask" "Not masked,Masked" newline setclrfld.long 0x00 2. -0x04 2. -0x08 2. " RX_USED_BIT_READ_MASK ,RX used bit read mask" "Not masked,Masked" setclrfld.long 0x00 1. -0x04 1. -0x08 1. " RECEIVE_COMPLETE_MASK ,Receive complete mask" "Not masked,Masked" newline setclrfld.long 0x00 0. -0x04 0. -0x08 0. " MANAGEMENT_FRAME_SENT_MASK ,Management frame sent mask" "Not masked,Masked" newline else group.long 0x24++0x03 line.long 0x00 "INT_STATUS,Interrupt Status Register" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " TSU_TIMER_COMPARISON_INTERRUPT ,IEEE 1588 timer comparison interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE ,Receive LPI indication status bit change" "No interrupt,Interrupt" newline setclrfld.long 0x00 26. 0x04 26. 0x08 26. " TSU_SECONDS_REGISTER_INCREMENT ,IEEE 1588 timer seconds register increment" "No interrupt,Interrupt" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PTP_PDELAY_RESP_FRAME_TRANSMITTED ,PTP Pdelay_Resp frame transmitted" "No interrupt,Interrupt" newline setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PTP_PDELAY_REQ_FRAME_TRANSMITTED ,PTP Pdelay_Req frame transmitted" "No interrupt,Interrupt" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PTP_PDELAY_RESP_FRAME_RECEIVED ,PTP Pdelay_Resp frame received" "No interrupt,Interrupt" newline setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PTP_PDELAY_REQ_FRAME_RECEIVED ,PTP Pdelay_Req frame received" "No interrupt,Interrupt" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PTP_SYNC_FRAME_TRANSMITTED ,PTP sync frame transmitted" "No interrupt,Interrupt" newline setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PTP_DELAY_REQ_FRAME_TRANSMITTED ,PTP Delay_Req frame transmitted" "No interrupt,Interrupt" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PTP_SYNC_FRAME_RECEIVED ,PTP sync frame received" "No interrupt,Interrupt" newline setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PTP_DELAY_REQ_FRAME_RECEIVED ,PTP Delay_Req frame received" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PAUSE_FRAME_TRANSMITTED ,Pause frame transmitted" "No interrupt,Interrupt" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PAUSE_TIME_ELAPSED ,Pause time elapsed" "No interrupt,Interrupt" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED ,Pause frame with non-zero pause quantum received" "No interrupt,Interrupt" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " RECEIVE_OVERRUN ,Receive overrun" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RETRY_LIMIT_EXCEEDED ,Retry limit exceeded" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TX_USED_BIT_READ ,TX used bit read" "No interrupt,Interrupt" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" newline setclrfld.long 0x00 0. 0x04 0. 0x08 0. " MANAGEMENT_FRAME_SENT ,Management frame sent" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "INT_MASK,Interrupt Mask Register" bitfld.long 0x00 29. " TSU_TIMER_COMPARISON_INTERRUPT_MASK ,IEEE 1588 timer comparison interrupt mask" "Not masked,Masked" bitfld.long 0x00 27. " RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE_MASK ,Receive LPI indication status bit change mask" "Not masked,Masked" newline bitfld.long 0x00 26. " TSU_SECONDS_REGISTER_INCREMENT_MASK ,IEEE 1588 timer seconds register increment mask" "Not masked,Masked" bitfld.long 0x00 25. " PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK ,PTP Pdelay_Resp frame transmitted mask" "Not masked,Masked" newline bitfld.long 0x00 24. " PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK ,PTP Pdelay_Req frame transmitted mask" "Not masked,Masked" bitfld.long 0x00 23. " PTP_PDELAY_RESP_FRAME_RECEIVED_MASK ,PTP Pdelay_Resp frame received mask" "Not masked,Masked" newline bitfld.long 0x00 22. " PTP_PDELAY_REQ_FRAME_RECEIVED_MASK ,PTP Pdelay_Req frame received mask" "Not masked,Masked" bitfld.long 0x00 21. " PTP_SYNC_FRAME_TRANSMITTED_MASK ,PTP sync frame transmitted mask" "Not masked,Masked" newline bitfld.long 0x00 20. " PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK ,PTP Delay_Req frame transmitted mask" "Not masked,Masked" bitfld.long 0x00 19. " PTP_SYNC_FRAME_RECEIVED_MASK ,PTP sync frame received mask" "Not masked,Masked" newline bitfld.long 0x00 18. " PTP_DELAY_REQ_FRAME_RECEIVED_MASK ,PTP Delay_Req frame received mask" "Not masked,Masked" bitfld.long 0x00 14. " PAUSE_FRAME_TRANSMITTED_MASK ,Pause frame transmitted mask" "Not masked,Masked" newline bitfld.long 0x00 13. " PAUSE_TIME_ELAPSED_MASK ,Pause time elapsed mask" "Not masked,Masked" bitfld.long 0x00 12. " PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED_MASK ,Pause frame with non-zero pause quantum received mask" "Not masked,Masked" newline bitfld.long 0x00 11. " RESP_NOT_OK_MASK ,BRESP not OK mask" "Not masked,Masked" bitfld.long 0x00 10. " RECEIVE_OVERRUN_MASK ,Receive overrun mask" "Not masked,Masked" newline bitfld.long 0x00 7. " TRANSMIT_COMPLETE_MASK ,Transmit complete mask" "Not masked,Masked" bitfld.long 0x00 6. " AMBA_ERROR_MASK ,Transmit frame corruption due to AMBA AXI error mask" "Not masked,Masked" newline bitfld.long 0x00 5. " RETRY_LIMIT_EXCEEDED_MASK ,Retry limit exceeded mask" "Not masked,Masked" bitfld.long 0x00 3. " TX_USED_BIT_READ_MASK ,TX used bit read mask" "Not masked,Masked" newline bitfld.long 0x00 2. " RX_USED_BIT_READ_MASK ,RX used bit read mask" "Not masked,Masked" bitfld.long 0x00 1. " RECEIVE_COMPLETE_MASK ,Receive complete mask" "Not masked,Masked" newline bitfld.long 0x00 0. " MANAGEMENT_FRAME_SENT_MASK ,Management frame sent mask" "Not masked,Masked" newline endif group.long 0x34++0x03 line.long 0x00 "PHY_MANAGEMENT,PHY Maintenance Register" bitfld.long 0x00 31. " WRITE0 ,Write 0" "0," bitfld.long 0x00 30. " WRITE1 ,Write 1" ",1" newline bitfld.long 0x00 28.--29. " OPERATION ,Operation" ",Write,Read," hexmask.long.byte 0x00 23.--27. 0x80 " PHY_ADDRESS ,PHY address" newline hexmask.long.byte 0x00 18.--22. 0x4 " REGISTER_ADDRESS ,Register address" bitfld.long 0x00 16.--17. " WRITE10 ,Write 10" ",,10," newline hexmask.long.word 0x00 0.--15. 1. " PHY_WRITE_READ_DATA ,PHY write/read data" rgroup.long 0x38++0x03 line.long 0x00 "PAUSE_TIME,Receive Pause Quantum Register" hexmask.long.word 0x00 0.--15. 1. " QUANTUM ,Received pause quantum" group.long 0x3C++0x0F line.long 0x00 "TX_PAUSE_QUANTUM,Transmit Pause Quantum Register" hexmask.long.word 0x00 16.--31. 1. " QUANTUM_P1 ,Transmit pause quantum - priority 1" hexmask.long.word 0x00 0.--15. 1. " QUANTUM ,Transmit pause quantum" line.long 0x04 "PBUF_TXCUTTHRU,TX Partial Store and Forward Register" bitfld.long 0x04 31. " DMA_TX_CUTTHRU ,TX partial store and forward" "Full,Partial" hexmask.long.word 0x04 0.--10. 1. " DMA_TX_CUTTHRU_THRESHOLD ,TX partial store and forward threshold" line.long 0x08 "PBUF_RXCUTTHRU,TX Partial Store and Forward Register" bitfld.long 0x08 31. " DMA_RX_CUTTHRU ,RX partial store and forward" "Full,Partial" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") hexmask.long.word 0x08 0.--8. 1. " DMA_RX_CUTTHRU_THRESHOLD ,RX partial store and forward threshold" else hexmask.long.word 0x08 0.--10. 1. " DMA_RX_CUTTHRU_THRESHOLD ,RX partial store and forward threshold" endif line.long 0x0C "JUMBO_MAX_LENGTH,Jumbo-Frame Maximum Length Register" hexmask.long.word 0x0C 0.--15. 1. " JUMBO_MAX_LENGTH ,Jumbo-Frame maximum length" group.long 0x54++0x03 line.long 0x00 "AXI_MAX_PIPELINE,AXI Maximum Pipeline Register" hexmask.long.byte 0x00 8.--15. 1. " AW2W_MAX_PIPELINE ,Maximum number of outstanding AXI write requests" hexmask.long.byte 0x00 0.--7. 1. " AR2R_MAX_PIPELINE ,Maximum number of outstanding AXI read requests" group.long 0x80++0x07 line.long 0x00 "HASH_BOTTOM,Hash Bottom Register" line.long 0x04 "HASH_TOP,Hash Top Register" group.long 0x88++0x07 line.long 0x00 "SPEC_ADD_BOTTOM_1,Specific Address Bottom 1 Register" line.long 0x04 "SPEC_ADD_TOP_1,Specific Address Top 1 Register" hexmask.long.byte 0x04 24.--29. 1. " FILTER_BYTE_MASK ,Filter byte mask" bitfld.long 0x04 16. " FILTER_TYPE ,Filter type" "Destination,Source" newline hexmask.long.word 0x04 0.--15. 1. " ADDRESS ,Specific address 1" group.long 0x90++0x07 line.long 0x00 "SPEC_ADD_BOTTOM_2,Specific Address Bottom 2 Register" line.long 0x04 "SPEC_ADD_TOP_2,Specific Address Top 2 Register" hexmask.long.byte 0x04 24.--29. 1. " FILTER_BYTE_MASK ,Filter byte mask" bitfld.long 0x04 16. " FILTER_TYPE ,Filter type" "Destination,Source" newline hexmask.long.word 0x04 0.--15. 1. " ADDRESS ,Specific address 2" group.long 0x98++0x07 line.long 0x00 "SPEC_ADD_BOTTOM_3,Specific Address Bottom 3 Register" line.long 0x04 "SPEC_ADD_TOP_3,Specific Address Top 3 Register" hexmask.long.byte 0x04 24.--29. 1. " FILTER_BYTE_MASK ,Filter byte mask" bitfld.long 0x04 16. " FILTER_TYPE ,Filter type" "Destination,Source" newline hexmask.long.word 0x04 0.--15. 1. " ADDRESS ,Specific address 3" group.long 0xA0++0x07 line.long 0x00 "SPEC_ADD_BOTTOM_4,Specific Address Bottom 4 Register" line.long 0x04 "SPEC_ADD_TOP_4,Specific Address Top 4 Register" hexmask.long.byte 0x04 24.--29. 1. " FILTER_BYTE_MASK ,Filter byte mask" bitfld.long 0x04 16. " FILTER_TYPE ,Filter type" "Destination,Source" newline hexmask.long.word 0x04 0.--15. 1. " ADDRESS ,Specific address 4" group.long 0xA8++0x03 line.long 0x00 "SPEC_TYPE_1,Type ID Match 1 Register" bitfld.long 0x00 31. " ENABLE_COPY ,Enable copy" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match" group.long 0xAC++0x03 line.long 0x00 "SPEC_TYPE_2,Type ID Match 2 Register" bitfld.long 0x00 31. " ENABLE_COPY ,Enable copy" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match" group.long 0xB0++0x03 line.long 0x00 "SPEC_TYPE_3,Type ID Match 3 Register" bitfld.long 0x00 31. " ENABLE_COPY ,Enable copy" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match" group.long 0xB4++0x03 line.long 0x00 "SPEC_TYPE_4,Type ID Match 4 Register" bitfld.long 0x00 31. " ENABLE_COPY ,Enable copy" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Type ID match" group.long 0xBC++0x13 line.long 0x00 "STRETCH_RATIO,IPG Stretch Register" hexmask.long.word 0x00 0.--15. 1. " IPG_STRETCH ,IPG stretch" line.long 0x04 "STACKED_VLAN,Stacked VLAN Register" bitfld.long 0x04 31. " ENABLE_PROCESSING ,Enable processing" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " MATCH ,User defined VLAN_TYPE field" line.long 0x08 "TX_PFC_PAUSE,Transmit PFC Pause Register" hexmask.long.byte 0x08 8.--15. 1. " VECTOR ,Priority vector pause size" hexmask.long.byte 0x08 0.--7. 1. " VECTOR_ENABLE ,Priority vector enable" line.long 0x0C "MASK_ADD1_BOTTOM,Specific Address Mask 1 Bottom Register" line.long 0x10 "MASK_ADD1_TOP,Specific Address Mask 1 Top Register" hexmask.long.word 0x10 0.--15. 1. " ADDRESS_MASK ,Specific address mask" group.long 0xD4++0x07 line.long 0x00 "RX_PTP_UNICAST,RX PTP Unicast IP Destination Address Register" line.long 0x04 "TX_PTP_UNICAST,TX PTP Unicast IP Destination Address Register" group.long 0xD0++0x03 line.long 0x00 "DMA_ADDR_OR_MASK,Receive DMA Data Buffer Address Mask Register" hexmask.long.byte 0x00 28.--31. 0x10 " MASK_VALUE ,Data buffer address mask value" hexmask.long.byte 0x00 0.--3. 1. " MASK_ENABLE ,Data buffer address mask enable" group.long 0xDC++0x03 line.long 0x00 "TSU_NSEC_CMP,IEEE 1588 Timer Comparison Value Nanoseconds Register" hexmask.long.tbyte 0x00 0.--21. 1. " COMPARISON_VALUE ,IEEE 1588 timer comparison value nanoseconds" group.long 0xE0++0x07 line.long 0x00 "TSU_SEC_CMP,IEEE 1588 Timer Comparison Value Seconds Register" line.long 0x04 "TSU_MSB_SEC_CMP,IEEE 1588 Timer Comparison Value Seconds Top Register" hexmask.long.word 0x04 0.--15. 1. " COMPARISON_VALUE ,IEEE 1588 timer comparison value seconds" rgroup.long 0xE8++0x0F line.long 0x00 "TSU_PTP_TX_MSB_SEC,PTP Event Frame Transmitted Seconds Register" hexmask.long.word 0x00 0.--15. 1. " TIMER_SECONDS ,PTP event frame transmitted seconds" line.long 0x04 "TSU_PTP_RX_MSB_SEC,PTP Event Frame Received Seconds Register" hexmask.long.word 0x04 0.--15. 1. " TIMER_SECONDS ,PTP event frame received seconds" line.long 0x08 "TSU_PEER_TX_MSB_SEC,PTP Peer Event Frame Transmitted Seconds Register" hexmask.long.word 0x08 0.--15. 1. " TIMER_SECONDS ,PTP peer event frame transmitted seconds" line.long 0x0C "TSU_PEER_RX_MSB_SEC,PTP Peer Event Frame Received Seconds Register" hexmask.long.word 0x0C 0.--15. 1. " TIMER_SECONDS ,PTP peer event frame received seconds" rgroup.long 0xFC++0x03 line.long 0x00 "REVISION_REG,Identification and Revision Register" hexmask.long.word 0x00 16.--31. 1. " MODULE_IDENTIFICATION_NUMBER ,Module identification number" hexmask.long.word 0x00 0.--15. 1. " MODULE_REVISION ,Module revision number" newline hgroup.long 0x100++0x03 hide.long 0x00 "OCTETS_TXED_BOTTOM,Octets Transmitted Bottom Register" in hgroup.long 0x104++0x03 hide.long 0x00 "OCTETS_TXED_TOP,Octets Transmitted Top Register" in rgroup.long 0x108++0x47 line.long 0x00 "FRAMES_TXED_OK,Frames Transmitted Register" line.long 0x04 "BROADCAST_TXED,Broadcast Frames Transmitted Register" line.long 0x08 "MULTICAST_TXED,Multicast Frames Transmitted Register" line.long 0x0C "PAUSE_FRAMES_TXED,Pause Frames Transmitted Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Transmitted pause frames" line.long 0x10 "FRAMES_TXED_64,64 Byte Frames Transmitted Register" line.long 0x14 "FRAMES_TXED_65,65 To 127 Byte Frames Transmitted Register" line.long 0x18 "FRAMES_TXED_128,128 To 255 Byte Frames Transmitted Register" line.long 0x1C "FRAMES_TXED_256,256 To 511 Byte Frames Transmitted Register" line.long 0x20 "FRAMES_TXED_512,512 To 1023 Byte Frames Transmitted Register" line.long 0x24 "FRAMES_TXED_1024,1024 To 1518 Byte Frames Transmitted Register" line.long 0x28 "FRAMES_TXED_1519,Greater Than 1518 Byte Frames Transmitted Register" line.long 0x2C "TX_UNDERRUNS,Transmit Under Runs Register" hexmask.long.word 0x2C 0.--9. 1. " COUNT ,Transmit under runs" line.long 0x30 "SINGLE_COLLISIONS,Single Collision Frames Register" hexmask.long.tbyte 0x30 0.--17. 1. " COUNT ,Single collision frames" line.long 0x34 "MULTIPLE_COLLISIONS,Multiple Collision Frames Register" hexmask.long.tbyte 0x34 0.--17. 1. " COUNT ,Multiple collision frames" line.long 0x38 "EXCESSIVE_COLLISIONS,Excessive Collisions Register" hexmask.long.word 0x38 0.--9. 1. " COUNT ,Excessive collision frames" line.long 0x3C "LATE_COLLISIONS,Late Collisions Register" hexmask.long.word 0x3C 0.--9. 1. " COUNT ,Late collision frames" line.long 0x40 "DEFERRED_FRAMES,Deferred Transmission Frames Register" hexmask.long.tbyte 0x40 0.--17. 1. " COUNT ,Deferred transmission frames" line.long 0x44 "CRS_ERRORS,Carrier Sense Errors Register" hexmask.long.word 0x44 0.--9. 1. " COUNT ,Carrier sense errors" hgroup.long 0x150++0x03 hide.long 0x00 "OCTETS_RXED_BOTTOM,Octets Receive Bottom Register" in hgroup.long 0x154++0x03 hide.long 0x00 "OCTETS_RXED_TOP,Octets Receive Top Register" in rgroup.long 0x158++0x5F line.long 0x00 "FRAMES_RXED_OK,Frames Received Register" line.long 0x04 "BROADCAST_RXED,Broadcast Frames Received Register" line.long 0x08 "MULTICAST_RXED,Multicast Frames Received Register" line.long 0x0C "PAUSE_FRAMES_RXED,Pause Frames Received Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Received pause frames" line.long 0x10 "FRAMES_RXED_64,64 Byte Frames Received Register" line.long 0x14 "FRAMES_RXED_65,65 To 127 Byte Frames Received Register" line.long 0x18 "FRAMES_RXED_128,128 To 255 Byte Frames Received Register" line.long 0x1C "FRAMES_RXED_256,256 To 511 Byte Frames Received Register" line.long 0x20 "FRAMES_RXED_512,512 To 1023 Byte Frames Received Register" line.long 0x24 "FRAMES_RXED_1024,1024 To 1518 Byte Frames Received Register" line.long 0x28 "FRAMES_RXED_1519,Greater Than 1518 Byte Frames Received Register" line.long 0x2C "UNDERSIZED_FRAMES,Undersized Frames Received Register" hexmask.long.word 0x2C 0.--9. 1. " COUNT ,Undersized frames received" line.long 0x30 "EXCESSIVE_RX_LENGTH,Oversize Frames Received Register" hexmask.long.word 0x30 0.--9. 1. " COUNT ,Oversize frames received" line.long 0x34 "RX_JABBERS,Jabbers Received Register" hexmask.long.word 0x34 0.--9. 1. " COUNT ,Jabbers received" line.long 0x38 "FCS_ERRORS,Frame check sequence errors" hexmask.long.word 0x38 0.--9. 1. " COUNT ,Excessive collision frames" line.long 0x3C "RX_LENGTH_ERRORS,Length Field Frame Errors Register" hexmask.long.word 0x3C 0.--9. 1. " COUNT ,Length field frame errors" line.long 0x40 "RX_SYMBOL_ERRORS,Receive Symbol_Errors Register" hexmask.long.word 0x40 0.--9. 1. " COUNT ,Receive symbol errors" line.long 0x44 "ALIGNMENT_ERRORS,Alignment Errors Register" hexmask.long.word 0x44 0.--9. 1. " COUNT ,Alignment errors" line.long 0x48 "RX_RESOURCE_ERRORS,Receive Resource Errors Register" hexmask.long.tbyte 0x48 0.--17. 1. " COUNT ,Receive resource errors" line.long 0x4C "RX_OVERRUNS,Receive Over Runs Register" hexmask.long.word 0x4C 0.--9. 1. " COUNT ,Receive over runs" line.long 0x50 "RX_IP_CK_ERRORS,IP Header Checksum Errors Register" hexmask.long.byte 0x50 0.--7. 1. " COUNT ,IP header checksum errors" line.long 0x54 "RX_TCP_CK_ERRORS,TCP Checksum Errors Register" hexmask.long.byte 0x54 0.--7. 1. " COUNT ,TCP checksum errors" line.long 0x58 "RX_UDP_CK_ERRORS,UDP Checksum Errors Register" hexmask.long.byte 0x58 0.--7. 1. " COUNT ,UDP checksum errors" line.long 0x5C "AUTO_FLUSHED_PKTS,Receive DMA Flushed Packets Register" hexmask.long.word 0x5C 0.--15. 1. " COUNT ,Flushed RX packets counter" rgroup.long 0x1BC++0x03 line.long 0x00 "TSU_TIMER_INCR_SUB_NSEC,IEEE 1588 Timer Increment Sub Nanoseconds Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,IEEE 1588 timer increment" group.long 0x1C0++0x03 line.long 0x00 "TSU_TIMER_MSB_SEC,IEEE 1588 Timer Seconds [47:32] Register" hexmask.long.word 0x00 0.--15. 1. " TIMER ,IEEE 1588 timer seconds [47:32]" group.long 0x1D0++0x07 line.long 0x00 "TSU_TIMER_SEC,IEEE 1588 Timer Seconds [31:0] Register" hexmask.long.word 0x00 0.--15. 1. " TIMER ,IEEE 1588 timer seconds [31:0]" line.long 0x04 "TSU_TIMER_NSEC,IEEE 1588 Timer Nanoseconds Register" hexmask.long 0x04 0.--29. 1. " TIMER ,IEEE 1588 timer nanoseconds" wgroup.long 0x1D8++0x03 line.long 0x00 "TSU_TIMER_ADJUST,IEEE 1588 Timer Adjust Register" bitfld.long 0x00 31. " ADD_SUBTRACT ,Add or subtract" "Add,Subtract" hexmask.long 0x00 0.--29. 1. " INCREMENT_VALUE ,IEEE 1588 timer increment value" group.long 0x1DC++0x03 line.long 0x00 "TSU_TIMER_INCR,IEEE 1588 Timer Increment Register" hexmask.long.byte 0x00 16.--23. 1. " NUM_INCS ,Number of incs before alt inc" hexmask.long.byte 0x00 8.--15. 1. " ALT_COUNT ,Alternative count of nanoseconds" newline hexmask.long.byte 0x00 0.--7. 1. " COUNT ,Count of nanoseconds" rgroup.long 0x1E0++0x1F line.long 0x00 "TSU_PTP_TX_SEC,PTP Event Frame Transmitted Seconds [31:0] Register" line.long 0x04 "TSU_PTP_TX_NSEC,PTP Event Frame Transmitted Nanoseconds Register" hexmask.long 0x04 0.--29. 1. " TIMER ,PTP event frame transmitted nanoseconds" line.long 0x08 "TSU_PTP_RX_SEC,PTP Event Frame Received Seconds [31:0] Register" line.long 0x0C "TSU_PTP_RX_NSEC,PTP Event Frame Received Nanoseconds Register" hexmask.long 0x0C 0.--29. 1. " TIMER ,PTP event frame received nanoseconds" line.long 0x10 "TSU_PEER_TX_SEC,PTP Peer Event Frame Transmitted Seconds [31:0] Register" line.long 0x14 "TSU_PEER_TX_NSEC,PTP Peer Event Frame Transmitted Nanoseconds Register" hexmask.long 0x14 0.--29. 1. " TIMER ,PTP peer event frame transmitted nanoseconds" line.long 0x18 "TSU_PEER_RX_SEC,PTP Peer Event Frame Received Seconds [31:0] Register" line.long 0x1C "TSU_PEER_RX_NSEC,PTP Peer Event Frame Received Nanoseconds Register" hexmask.long 0x1C 0.--29. 1. " TIMER ,PTP peer event frame received nanoseconds" group.long 0x260++0x0B line.long 0x00 "TX_PAUSE_QUANTUM1,Transmit Pause Quantum 1 Register" hexmask.long.word 0x00 16.--31. 1. " QUANTUM_P3 ,Transmit pause quantum - priority 3" hexmask.long.word 0x00 0.--15. 1. " QUANTUM_P2 ,Transmit pause quantum - priority 2" line.long 0x04 "TX_PAUSE_QUANTUM2,Transmit Pause Quantum 2 Register" hexmask.long.word 0x04 16.--31. 1. " QUANTUM_P5 ,Transmit pause quantum - priority 5" hexmask.long.word 0x04 0.--15. 1. " QUANTUM_P4 ,Transmit pause quantum - priority 4" line.long 0x08 "TX_PAUSE_QUANTUM3,Transmit Pause Quantum 3 Register" hexmask.long.word 0x08 16.--31. 1. " QUANTUM_P7 ,Transmit pause quantum - priority 7" hexmask.long.word 0x08 0.--15. 1. " QUANTUM_P6 ,Transmit pause quantum - priority 6" hgroup.long 0x270++0x03 hide.long 0x00 "RX_LPI,Receive LPI Transitions Register" in hgroup.long 0x274++0x03 hide.long 0x00 "RX_LPI_TIME,Received LPI Time Register" in group.long 0x278++0x03 line.long 0x00 "TX_LPI,Transmit LPI Transitions Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count of TX LPI transitions" hgroup.long 0x27C++0x03 hide.long 0x00 "TX_LPI_TIME,Transmit LPI Time Register" in newline sif !(cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*")) rgroup.long 0x288++0x1F line.long 0x00 "DESIGNCFG_DEBUG3,Design Configuration 3 Register" bitfld.long 0x00 24.--29. " NUM_SPEC_ADD_FILTERS ,Value of num_spec_add_filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "DESIGNCFG_DEBUG4,Design Configuration 4 Register" bitfld.long 0x04 16.--19. " TX_BASE2_FIFO_SIZE ,Value of gem_tx_base2_fifo_size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " TX_FIFO_SIZE ,Value of gem_tx_fifo_size" line.long 0x08 "DESIGNCFG_DEBUG5,Design Configuration 5 Register" bitfld.long 0x08 29.--31. " AXI_PROT_VALUE ,Value of gem_axi_prot_value" "0,1,2,3,4,5,6,7" bitfld.long 0x08 28. " TSU_CLK ,Value of gem_tsu_clk" "0,1" newline hexmask.long.byte 0x08 20.--27. 1. " RX_BUFFER_LENGTH_DEF ,Value of gem_rx_buffer_length_def" bitfld.long 0x08 19. " TX_PBUF_SIZE_DEF ,Value of gem_tx_pbuf_size_def" "0,1" newline bitfld.long 0x08 17.--18. " RX_PBUF_SIZE_DEF ,Value of gem_rx_pbuf_size_def" "0,1,2,3" bitfld.long 0x08 15.--16. " ENDIAN_SWAP_DEF ,Value of gem_endian_swap_def" "0,1,2,3" newline bitfld.long 0x08 12.--14. " MDC_CLOCK_DIV ,Value of gem_mdc_clock_div" "0,1,2,3,4,5,6,7" bitfld.long 0x08 10.--11. " DMA_BUS_WIDTH_DEF ,Value of gem_dma_bus_width_def" "0,1,2,3" newline bitfld.long 0x08 9. " PHY_IDENT ,Value of gem_phy_ident" "0,1" bitfld.long 0x08 8. " TSU ,Value of gem_tsu" "0,1" newline bitfld.long 0x08 4.--7. " TX_FIFO_CNT_WIDTH ,Value of gem_tx_fifo_cnt_width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " RX_FIFO_CNT_WIDTH ,Value of gem_rx_fifo_cnt_width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "DESIGNCFG_DEBUG6,Design Configuration 6 Register" bitfld.long 0x0C 25. " PBUF_CUTTHRU ,Value of gem_pbuf_cutthru" "0,1" bitfld.long 0x0C 24. " PFC_MULTI_QUANTUM ,Value of gem_pfc_multi_quantum" "0,1" newline bitfld.long 0x0C 23. " DMA_ADDR_WIDTH_IS_64B ,Value of gem_dma_addr_width_is_64b" "0,1" bitfld.long 0x0C 22. " HOST_IF_SOFT_SELECT ,Value of gem_host_if_soft_select" "0,1" newline bitfld.long 0x0C 21. " TX_ADD_FIFO_IF ,Value of gem_tx_add_fifo_if" "0,1" bitfld.long 0x0C 20. " EXT_TSU_TIMER ,Value of gem_ext_tsu_timer" "0,1" newline bitfld.long 0x0C 16.--19. " TX_PBUF_QUEUE_SEGMENT_SIZE ,Value of gem_tx_pbuf_queue_segment_size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 15. " DMA_PRIORITY_QUEUE15 ,Value of gem_dma_priority_queue15" "Low,High" newline bitfld.long 0x0C 14. " DMA_PRIORITY_QUEUE14 ,Value of gem_dma_priority_queue14" "Low,High" bitfld.long 0x0C 13. " DMA_PRIORITY_QUEUE13 ,Value of gem_dma_priority_queue13" "Low,High" newline bitfld.long 0x0C 12. " DMA_PRIORITY_QUEUE12 ,Value of gem_dma_priority_queue12" "Low,High" bitfld.long 0x0C 11. " DMA_PRIORITY_QUEUE11 ,Value of gem_dma_priority_queue11" "Low,High" newline bitfld.long 0x0C 10. " DMA_PRIORITY_QUEUE10 ,Value of gem_dma_priority_queue10" "Low,High" bitfld.long 0x0C 9. " DMA_PRIORITY_QUEUE9 ,Value of gem_dma_priority_queue9" "Low,High" newline bitfld.long 0x0C 8. " DMA_PRIORITY_QUEUE8 ,Value of gem_dma_priority_queue8" "Low,High" bitfld.long 0x0C 7. " DMA_PRIORITY_QUEUE7 ,Value of gem_dma_priority_queue7" "Low,High" newline bitfld.long 0x0C 6. " DMA_PRIORITY_QUEUE6 ,Value of gem_dma_priority_queue6" "Low,High" bitfld.long 0x0C 5. " DMA_PRIORITY_QUEUE5 ,Value of gem_dma_priority_queue5" "Low,High" newline bitfld.long 0x0C 4. " DMA_PRIORITY_QUEUE4 ,Value of gem_dma_priority_queue4" "Low,High" bitfld.long 0x0C 3. " DMA_PRIORITY_QUEUE3 ,Value of gem_dma_priority_queue3" "Low,High" newline bitfld.long 0x0C 2. " DMA_PRIORITY_QUEUE2 ,Value of gem_dma_priority_queue2" "Low,High" bitfld.long 0x0C 1. " DMA_PRIORITY_QUEUE1 ,Value of gem_dma_priority_queue1" "Low,High" newline bitfld.long 0x0C 0. " DMA_PRIORITY_QUEUE0 ,Value of gem_dma_priority_queue0" "Low,High" line.long 0x10 "DESIGNCFG_DEBUG7,Design Configuration 7 Register" bitfld.long 0x10 28.--31. " TX_PBUF_NUM_SEGMENTS_Q7 ,Value of gem_tx_pbuf_num_segments_q7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " TX_PBUF_NUM_SEGMENTS_Q6 ,Value of gem_tx_pbuf_num_segments_q6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 20.--23. " TX_PBUF_NUM_SEGMENTS_Q5 ,Value of gem_tx_pbuf_num_segments_q5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. " TX_PBUF_NUM_SEGMENTS_Q4 ,Value of gem_tx_pbuf_num_segments_q4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. " TX_PBUF_NUM_SEGMENTS_Q3 ,Value of gem_tx_pbuf_num_segments_q3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. " TX_PBUF_NUM_SEGMENTS_Q2 ,Value of gem_tx_pbuf_num_segments_q2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. " TX_PBUF_NUM_SEGMENTS_Q1 ,Value of gem_tx_pbuf_num_segments_q1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " TX_PBUF_NUM_SEGMENTS_Q0 ,Value of gem_tx_pbuf_num_segments_q0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "DESIGNCFG_DEBUG8,Design Configuration 8 Register" hexmask.long.byte 0x14 24.--31. 1. " NUM_TYPE1_SCREENERS ,Value of gem_num_type1_screeners" hexmask.long.byte 0x14 16.--23. 1. " NUM_TYPE2_SCREENERS ,Value of gem_num_type2_screeners" newline hexmask.long.byte 0x14 8.--15. 1. " NUM_SCR2_ETHTYPE_REGS ,Value of gem_num_scr2_ethtype_regs" hexmask.long.byte 0x14 0.--7. 1. " NUM_SCR2_COMPARE_REGS ,Value of gem_num_scr2_compare_regs" line.long 0x18 "DESIGNCFG_DEBUG9,Design Configuration 9 Register" bitfld.long 0x18 28.--31. " TX_PBUF_NUM_SEGMENTS_Q15 ,Value of gem_tx_pbuf_num_segments_q15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 24.--27. " TX_PBUF_NUM_SEGMENTS_Q14 ,Value of gem_tx_pbuf_num_segments_q14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 20.--23. " TX_PBUF_NUM_SEGMENTS_Q13 ,Value of gem_tx_pbuf_num_segments_q13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 16.--19. " TX_PBUF_NUM_SEGMENTS_Q12 ,Value of gem_tx_pbuf_num_segments_q12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 12.--15. " TX_PBUF_NUM_SEGMENTS_Q11 ,Value of gem_tx_pbuf_num_segments_q11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. " TX_PBUF_NUM_SEGMENTS_Q10 ,Value of gem_tx_pbuf_num_segments_q10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 4.--7. " TX_PBUF_NUM_SEGMENTS_Q9 ,Value of gem_tx_pbuf_num_segments_q9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. " TX_PBUF_NUM_SEGMENTS_Q8 ,Value of gem_tx_pbuf_num_segments_q8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "DESIGNCFG_DEBUG10,Design Configuration 10 Register" bitfld.long 0x1C 28.--31. " EMAC_BUS_WIDTH ,Value of gem_emac_bus_width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 24.--27. " TX_PBUF_DATA ,Value of gem_tx_pbuf_data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 20.--23. " RX_PBUF_DATA ,Value of gem_rx_pbuf_data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 16.--19. " AXI_ACCESS_PIPELINE_BITS ,Value of gem_axi_access_pipeline_bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--15. " AXI_TX_DESC_RD_BUFF_BITS ,Value of gem_ axi_tx_desc_rd_buff_bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. " AXI_RX_DESC_RD_BUFF_BITS ,Value of gem_axi_rx_desc_rd_buff_bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 4.--7. " AXI_TX_DESC_WR_BUFF_BITS ,Value of gem_axi_tx_desc_wr_buff_bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. " AXI_RX_DESC_WR_BUFF_BITS ,Value of gem_axi_rx_desc_wr_buff_bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") group.long 0x400++0x03 line.long 0x00 "INT_STATUS_Q1,Interrupt Status Queue 1 Register" bitfld.long 0x00 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" bitfld.long 0x00 10. " RECEIVE_OVERRUN ,Receive over run" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" bitfld.long 0x00 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION ,Retry limit exceeded" "No interrupt,Interrupt" bitfld.long 0x00 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" else group.long 0x400++0x03 line.long 0x00 "INT_STATUS_Q1,Interrupt Status Queue 1 Register" setclrfld.long 0x00 11. 0x200 11. 0x220 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x200 10. 0x220 10. " RECEIVE_OVERRUN ,Receive over run" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. 0x200 7. 0x220 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x200 6. 0x220 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x200 5. 0x220 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION ,Retry limit exceeded" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x200 2. 0x220 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x200 1. 0x220 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") group.long 0x404++0x03 line.long 0x00 "INT_STATUS_Q2,Interrupt Status Queue 2 Register" bitfld.long 0x00 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" bitfld.long 0x00 10. " RECEIVE_OVERRUN ,Receive over run" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" bitfld.long 0x00 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION ,Retry limit exceeded" "No interrupt,Interrupt" bitfld.long 0x00 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" else group.long 0x404++0x03 line.long 0x00 "INT_STATUS_Q2,Interrupt Status Queue 2 Register" setclrfld.long 0x00 11. 0x200 11. 0x220 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x200 10. 0x220 10. " RECEIVE_OVERRUN ,Receive over run" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. 0x200 7. 0x220 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x200 6. 0x220 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x200 5. 0x220 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION ,Retry limit exceeded" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x200 2. 0x220 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x200 1. 0x220 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") group.long 0x408++0x03 line.long 0x00 "INT_STATUS_Q3,Interrupt Status Queue 3 Register" bitfld.long 0x00 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" bitfld.long 0x00 10. " RECEIVE_OVERRUN ,Receive over run" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" bitfld.long 0x00 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION ,Retry limit exceeded" "No interrupt,Interrupt" bitfld.long 0x00 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" else group.long 0x408++0x03 line.long 0x00 "INT_STATUS_Q3,Interrupt Status Queue 3 Register" setclrfld.long 0x00 11. 0x200 11. 0x220 11. " RESP_NOT_OK ,BRESP not OK" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x200 10. 0x220 10. " RECEIVE_OVERRUN ,Receive over run" "No interrupt,Interrupt" newline setclrfld.long 0x00 7. 0x200 7. 0x220 7. " TRANSMIT_COMPLETE ,Transmit complete" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x200 6. 0x220 6. " AMBA_ERROR ,Transmit frame corruption due to AMBA AXI error" "No interrupt,Interrupt" newline setclrfld.long 0x00 5. 0x200 5. 0x220 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION ,Retry limit exceeded" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x200 2. 0x220 2. " RX_USED_BIT_READ ,RX used bit read" "No interrupt,Interrupt" newline setclrfld.long 0x00 1. 0x200 1. 0x220 1. " RECEIVE_COMPLETE ,Receive complete" "No interrupt,Interrupt" endif newline hgroup.long 0x440++0x03 hide.long 0x00 "TRANSMIT_Q1_PTR,TX Buffer Queue 1 Base Address Register" in hgroup.long 0x444++0x03 hide.long 0x00 "TRANSMIT_Q2_PTR,TX Buffer Queue 2 Base Address Register" in hgroup.long 0x448++0x03 hide.long 0x00 "TRANSMIT_Q3_PTR,TX Buffer Queue 3 Base Address Register" in hgroup.long 0x480++0x03 hide.long 0x00 "RECEIVE_Q1_PTR,RX Buffer Queue 1 Base Address Register" in hgroup.long 0x484++0x03 hide.long 0x00 "RECEIVE_Q2_PTR,RX Buffer Queue 2 Base Address Register" in hgroup.long 0x488++0x03 hide.long 0x00 "RECEIVE_Q3_PTR,RX Buffer Queue 3 Base Address Register" in group.long 0x4A0++0x03 line.long 0x00 "RXBUF_SIZE_Q1,RX Buffer Size Queue 1 Register" hexmask.long.byte 0x00 0.--7. 1. " DMA_RX_Q_BUF_SIZE ,DMA receive buffer size in system memory" group.long 0x4A4++0x03 line.long 0x00 "RXBUF_SIZE_Q2,RX Buffer Size Queue 2 Register" hexmask.long.byte 0x00 0.--7. 1. " DMA_RX_Q_BUF_SIZE ,DMA receive buffer size in system memory" group.long 0x4A8++0x03 line.long 0x00 "RXBUF_SIZE_Q3,RX Buffer Size Queue 3 Register" hexmask.long.byte 0x00 0.--7. 1. " DMA_RX_Q_BUF_SIZE ,DMA receive buffer size in system memory" group.long 0x4AC++0x03 line.long 0x00 "RXBUF_SIZE_Q4,RX Buffer Size Queue 4 Register" hexmask.long.byte 0x00 0.--7. 1. " DMA_RX_Q_BUF_SIZE ,DMA receive buffer size in system memory" group.long 0x4BC++0x17 line.long 0x00 "CBS_CONTROL,CBS Control Register" bitfld.long 0x00 1. " CBS_ENABLE_QUEUE_B ,Enable credit based shaping on second highest priority queue" "Disabled,Enabled" bitfld.long 0x00 0. " CBS_ENABLE_QUEUE_A ,Enable credit based shaping on highest priority queue" "Disabled,Enabled" line.long 0x04 "CBS_IDLESLOPE_Q_A,CBS IdleSlope Queue A Register" line.long 0x08 "CBS_IDLESLOPE_Q_B,CBS IdleSlope Queue B Register" line.long 0x0C "MSB_BUFF_Q_BASE_ADDR_REG,MSB Buffer Queue Base Address Register" line.long 0x10 "TX_BD_CONTROL,TX BD Control Register" bitfld.long 0x10 4.--5. " TX_BD_TS_MODE ,TX descriptor timestamp insertion mode" "Disabled,PTP Event Frames,All PTP Frames,All Frames" line.long 0x14 "RX_BD_CONTROL,RX BD Control Register" bitfld.long 0x14 4.--5. " RX_BD_TS_MODE ,RX descriptor timestamp insertion mode" "Disabled,PTP Event Frames,All PTP Frames,All Frames" group.long 0x500++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_0,Screening Type 1 Register 0" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x504++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_1,Screening Type 1 Register 1" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x508++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_2,Screening Type 1 Register 2" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50C++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_3,Screening Type 1 Register 3" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x510++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_4,Screening Type 1 Register 4" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x514++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_5,Screening Type 1 Register 5" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x518++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_6,Screening Type 1 Register 6" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x51C++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_7,Screening Type 1 Register 7" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x520++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_8,Screening Type 1 Register 8" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x524++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_9,Screening Type 1 Register 9" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x528++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_10,Screening Type 1 Register 10" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x52C++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_11,Screening Type 1 Register 11" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x530++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_12,Screening Type 1 Register 12" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x534++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_13,Screening Type 1 Register 13" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x538++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_14,Screening Type 1 Register 14" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x53C++0x03 line.long 0x00 "SCREENING_TYPE_1_REGISTER_15,Screening Type 1 Register 15" bitfld.long 0x00 29. " UDP_PORT_MATCH_ENABLE ,UDP port match enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSTC_ENABLE ,DS/TC enable" "Disabled,Enabled" newline hexmask.long.word 0x00 12.--27. 1. " UDP_PORT_MATCH ,UDP port match" hexmask.long.byte 0x00 4.--11. 1. " DSTC_MATCH ,DS/TC match" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x540++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_0,Screening Type 2 Register 0" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x544++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_1,Screening Type 2 Register 1" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x548++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_2,Screening Type 2 Register 2" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54C++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_3,Screening Type 2 Register 3" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x550++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_4,Screening Type 2 Register 4" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x554++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_5,Screening Type 2 Register 5" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x558++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_6,Screening Type 2 Register 6" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x55C++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_7,Screening Type 2 Register 7" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x560++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_8,Screening Type 2 Register 8" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x564++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_9,Screening Type 2 Register 9" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x568++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_10,Screening Type 2 Register 10" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x56C++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_11,Screening Type 2 Register 11" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x570++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_12,Screening Type 2 Register 12" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x574++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_13,Screening Type 2 Register 13" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x578++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_14,Screening Type 2 Register 14" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x57C++0x03 line.long 0x00 "SCREENING_TYPE_2_REGISTER_15,Screening Type 2 Register 15" bitfld.long 0x00 30. " COMPARE_C_ENABLE ,Compare C enable" "Disabled,Enabled" bitfld.long 0x00 25.--29. " COMPARE_C ,Compare C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. " COMPARE_B_ENABLE ,Compare B enable" "Disabled,Enabled" bitfld.long 0x00 19.--23. " COMPARE_B ,Compare B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " COMPARE_A_ENABLE ,Compare A enable" "Disabled,Enabled" bitfld.long 0x00 13.--17. " COMPARE_A ,Compare A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12. " ETHERTYPE_ENABLE ,EtherType enable" "Disabled,Enabled" bitfld.long 0x00 9.--11. " INDEX ,EtherType" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. " VLAN_ENABLE ,VLAN enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VLAN_PRIORITY ,VLAN priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. " QUEUE_NUMBER ,Queue number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J335*") newline group.long 0x640++0x03 line.long 0x00 "INT_MASK_Q1,Interrupt Mask Queue 1 Register" setclrfld.long 0x00 11. -0x20 11. -0x40 11. " RESP_NOT_OK_INT_MASK ,BRESP not OK interrupt mask" "Not masked,Masked" setclrfld.long 0x00 10. -0x20 10. -0x40 10. " RECEIVE_OVERRUN_INT_MASK ,Receive over run interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 7. -0x20 7. -0x40 7. " TRANSMIT_COMPLETE_INT_MASK ,Transmit complete interrupt mask" "Not masked,Masked" setclrfld.long 0x00 6. -0x20 6. -0x40 6. " AMBA_ERROR_INT_MASK ,Transmit frame corruption due to AMBA AXI error interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 5. -0x20 5. -0x40 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INT_MASK ,Retry limit exceeded interrupt mask" "Not masked,Masked" setclrfld.long 0x00 2. -0x20 2. -0x40 2. " RX_USED_BIT_READ_INT_MASK ,RX used bit read interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 1. -0x20 1. -0x40 1. " RECEIVE_COMPLETE_INT_MASK ,Receive complete interrupt mask" "Not masked,Masked" group.long 0x644++0x03 line.long 0x00 "INT_MASK_Q2,Interrupt Mask Queue 2 Register" setclrfld.long 0x00 11. -0x20 11. -0x40 11. " RESP_NOT_OK_INT_MASK ,BRESP not OK interrupt mask" "Not masked,Masked" setclrfld.long 0x00 10. -0x20 10. -0x40 10. " RECEIVE_OVERRUN_INT_MASK ,Receive over run interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 7. -0x20 7. -0x40 7. " TRANSMIT_COMPLETE_INT_MASK ,Transmit complete interrupt mask" "Not masked,Masked" setclrfld.long 0x00 6. -0x20 6. -0x40 6. " AMBA_ERROR_INT_MASK ,Transmit frame corruption due to AMBA AXI error interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 5. -0x20 5. -0x40 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INT_MASK ,Retry limit exceeded interrupt mask" "Not masked,Masked" setclrfld.long 0x00 2. -0x20 2. -0x40 2. " RX_USED_BIT_READ_INT_MASK ,RX used bit read interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 1. -0x20 1. -0x40 1. " RECEIVE_COMPLETE_INT_MASK ,Receive complete interrupt mask" "Not masked,Masked" group.long 0x648++0x03 line.long 0x00 "INT_MASK_Q3,Interrupt Mask Queue 3 Register" setclrfld.long 0x00 11. -0x20 11. -0x40 11. " RESP_NOT_OK_INT_MASK ,BRESP not OK interrupt mask" "Not masked,Masked" setclrfld.long 0x00 10. -0x20 10. -0x40 10. " RECEIVE_OVERRUN_INT_MASK ,Receive over run interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 7. -0x20 7. -0x40 7. " TRANSMIT_COMPLETE_INT_MASK ,Transmit complete interrupt mask" "Not masked,Masked" setclrfld.long 0x00 6. -0x20 6. -0x40 6. " AMBA_ERROR_INT_MASK ,Transmit frame corruption due to AMBA AXI error interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 5. -0x20 5. -0x40 5. " RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INT_MASK ,Retry limit exceeded interrupt mask" "Not masked,Masked" setclrfld.long 0x00 2. -0x20 2. -0x40 2. " RX_USED_BIT_READ_INT_MASK ,RX used bit read interrupt mask" "Not masked,Masked" newline setclrfld.long 0x00 1. -0x20 1. -0x40 1. " RECEIVE_COMPLETE_INT_MASK ,Receive complete interrupt mask" "Not masked,Masked" newline endif group.long 0x6E0++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_0,EtherType 2 Register 0" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6E4++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_1,EtherType 2 Register 1" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6E8++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_2,EtherType 2 Register 2" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6EC++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_3,EtherType 2 Register 3" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6F0++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_4,EtherType 2 Register 4" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6F4++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_5,EtherType 2 Register 5" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6F8++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_6,EtherType 2 Register 6" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" group.long 0x6FC++0x03 line.long 0x00 "SCREENING_TYPE_2_ETHERTYPE_REG_7,EtherType 2 Register 7" hexmask.long.word 0x00 0.--15. 1. " COMPARE_VALUE ,Compare value" newline group.long 0x700++0x07 line.long 0x00 "TYPE2_COMPARE_0_WORD_0,Type2 Compare Word 0 0 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_0_WORD_1,Type2 Compare Word 1 0 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x708++0x07 line.long 0x00 "TYPE2_COMPARE_1_WORD_0,Type2 Compare Word 0 1 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_1_WORD_1,Type2 Compare Word 1 1 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x710++0x07 line.long 0x00 "TYPE2_COMPARE_2_WORD_0,Type2 Compare Word 0 2 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_2_WORD_1,Type2 Compare Word 1 2 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x718++0x07 line.long 0x00 "TYPE2_COMPARE_3_WORD_0,Type2 Compare Word 0 3 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_3_WORD_1,Type2 Compare Word 1 3 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x720++0x07 line.long 0x00 "TYPE2_COMPARE_4_WORD_0,Type2 Compare Word 0 4 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_4_WORD_1,Type2 Compare Word 1 4 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x728++0x07 line.long 0x00 "TYPE2_COMPARE_5_WORD_0,Type2 Compare Word 0 5 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_5_WORD_1,Type2 Compare Word 1 5 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x730++0x07 line.long 0x00 "TYPE2_COMPARE_6_WORD_0,Type2 Compare Word 0 6 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_6_WORD_1,Type2 Compare Word 1 6 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x738++0x07 line.long 0x00 "TYPE2_COMPARE_7_WORD_0,Type2 Compare Word 0 7 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_7_WORD_1,Type2 Compare Word 1 7 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x740++0x07 line.long 0x00 "TYPE2_COMPARE_8_WORD_0,Type2 Compare Word 0 8 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_8_WORD_1,Type2 Compare Word 1 8 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x748++0x07 line.long 0x00 "TYPE2_COMPARE_9_WORD_0,Type2 Compare Word 0 9 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_9_WORD_1,Type2 Compare Word 1 9 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x750++0x07 line.long 0x00 "TYPE2_COMPARE_10_WORD_0,Type2 Compare Word 0 10 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_10_WORD_1,Type2 Compare Word 1 10 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x758++0x07 line.long 0x00 "TYPE2_COMPARE_11_WORD_0,Type2 Compare Word 0 11 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_11_WORD_1,Type2 Compare Word 1 11 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x760++0x07 line.long 0x00 "TYPE2_COMPARE_12_WORD_0,Type2 Compare Word 0 12 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_12_WORD_1,Type2 Compare Word 1 12 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x768++0x07 line.long 0x00 "TYPE2_COMPARE_13_WORD_0,Type2 Compare Word 0 13 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_13_WORD_1,Type2 Compare Word 1 13 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x770++0x07 line.long 0x00 "TYPE2_COMPARE_14_WORD_0,Type2 Compare Word 0 14 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_14_WORD_1,Type2 Compare Word 1 14 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x778++0x07 line.long 0x00 "TYPE2_COMPARE_15_WORD_0,Type2 Compare Word 0 15 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_15_WORD_1,Type2 Compare Word 1 15 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x780++0x07 line.long 0x00 "TYPE2_COMPARE_16_WORD_0,Type2 Compare Word 0 16 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_16_WORD_1,Type2 Compare Word 1 16 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x788++0x07 line.long 0x00 "TYPE2_COMPARE_17_WORD_0,Type2 Compare Word 0 17 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_17_WORD_1,Type2 Compare Word 1 17 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x790++0x07 line.long 0x00 "TYPE2_COMPARE_18_WORD_0,Type2 Compare Word 0 18 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_18_WORD_1,Type2 Compare Word 1 18 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x798++0x07 line.long 0x00 "TYPE2_COMPARE_19_WORD_0,Type2 Compare Word 0 19 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_19_WORD_1,Type2 Compare Word 1 19 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7A0++0x07 line.long 0x00 "TYPE2_COMPARE_20_WORD_0,Type2 Compare Word 0 20 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_20_WORD_1,Type2 Compare Word 1 20 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7A8++0x07 line.long 0x00 "TYPE2_COMPARE_21_WORD_0,Type2 Compare Word 0 21 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_21_WORD_1,Type2 Compare Word 1 21 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7B0++0x07 line.long 0x00 "TYPE2_COMPARE_22_WORD_0,Type2 Compare Word 0 22 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_22_WORD_1,Type2 Compare Word 1 22 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7B8++0x07 line.long 0x00 "TYPE2_COMPARE_23_WORD_0,Type2 Compare Word 0 23 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_23_WORD_1,Type2 Compare Word 1 23 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7C0++0x07 line.long 0x00 "TYPE2_COMPARE_24_WORD_0,Type2 Compare Word 0 24 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_24_WORD_1,Type2 Compare Word 1 24 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7C8++0x07 line.long 0x00 "TYPE2_COMPARE_25_WORD_0,Type2 Compare Word 0 25 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_25_WORD_1,Type2 Compare Word 1 25 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7D0++0x07 line.long 0x00 "TYPE2_COMPARE_26_WORD_0,Type2 Compare Word 0 26 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_26_WORD_1,Type2 Compare Word 1 26 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7D8++0x07 line.long 0x00 "TYPE2_COMPARE_27_WORD_0,Type2 Compare Word 0 27 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_27_WORD_1,Type2 Compare Word 1 27 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7E0++0x07 line.long 0x00 "TYPE2_COMPARE_28_WORD_0,Type2 Compare Word 0 28 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_28_WORD_1,Type2 Compare Word 1 28 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7E8++0x07 line.long 0x00 "TYPE2_COMPARE_29_WORD_0,Type2 Compare Word 0 29 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_29_WORD_1,Type2 Compare Word 1 29 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7F0++0x07 line.long 0x00 "TYPE2_COMPARE_30_WORD_0,Type2 Compare Word 0 30 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_30_WORD_1,Type2 Compare Word 1 30 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" group.long 0x7F8++0x07 line.long 0x00 "TYPE2_COMPARE_31_WORD_0,Type2 Compare Word 0 31 Register" hexmask.long.word 0x00 16.--31. 1. " COMPARE_VALUE ,Compare value" hexmask.long.word 0x00 0.--15. 1. " MASK_VALUE ,Mask value" line.long 0x04 "TYPE2_COMPARE_31_WORD_1,Type2 Compare Word 1 31 Register" bitfld.long 0x04 7.--8. " COMPARE_OFFSET ,Compare offset" "From beginning of frame,From byte after EtherType,From byte following end of IP header,From byte following end of TCP/UDP header" hexmask.long.byte 0x04 0.--6. 1. " OFFSET_VALUE ,Offset value" width 0x0B tree.end endif sif (cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")) tree "MEDIALB (MEDIA LOCAL BUS INTERFACE)" base ad:0xB8008000 width 14. group.long 0x00++0x07 line.long 0x00 "MLB0_DCCR,Device Control Configuration Register" bitfld.long 0x00 31. " MDE ,MediaLB device enable" "Disabled,Enabled" bitfld.long 0x00 30. " LBM ,Loop-Back mode enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " MCS ,MediaLB clock select" "256Fs-8q,512Fs-16q,1024Fs-32q," newline bitfld.long 0x00 27. " M5PS ,MediaLB 5-pin select" "3-pin,?..." sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*") rbitfld.long 0x00 26. " MLK ,MediaLB lock" "Unlocked,Locked" else bitfld.long 0x00 26. " MLK ,MediaLB lock" "Unlocked,Locked" endif bitfld.long 0x00 25. " MLE ,MediaLB Little endian mode" "Big,Little" newline bitfld.long 0x00 24. " MHRE ,MediaLB hardware reset enable" "Disabled,Enabled" bitfld.long 0x00 23. " MRS ,MediaLB software Reset" "No reset,Reset" hexmask.long.byte 0x00 0.--7. 1. " MDA ,MediaLB device address" line.long 0x04 "MLB0_SSCR,System Status Configuration Register" bitfld.long 0x04 7. " SSRE ,System service request enable" "Disabled,Enabled" eventfld.long 0x04 6. " SDMU ,System detects MediaLB unlock" "Not detected,Detected" eventfld.long 0x04 5. " SDML ,System detect MediaLB lock" "Not detected,Detected" newline eventfld.long 0x04 4. " SDSC ,System detects subcommand" "Not detected,Detected" eventfld.long 0x04 3. " SDCS ,System detects channel scan" "Not detected,Detected" eventfld.long 0x04 2. " SDNU ,System detects network unlock" "Not detected,Detected" newline eventfld.long 0x04 1. " SDNL ,System detects network lock" "Not detected,Detected" eventfld.long 0x04 0. " SDR ,System detects reset" "Not detected,Detected" rgroup.long 0x08++0x03 line.long 0x00 "MLB0_SDCR,System Data Configuration Register" group.long 0x0C++0x03 line.long 0x00 "MLB0_SMCR,System Mask Configuration Register" bitfld.long 0x00 6. " SMMU ,System masks MediaLB unlock" "Not masked,Masked" bitfld.long 0x00 5. " SMML ,System masks MediaLB lock" "Not masked,Masked" bitfld.long 0x00 4. " SMSC ,System masks subcommand" "Not masked,Masked" newline bitfld.long 0x00 3. " SMCS ,System masks channel scan" "Not masked,Masked" bitfld.long 0x00 2. " SMNU ,System masks network unlock" "Not masked,Masked" bitfld.long 0x00 1. " SMNL ,System masks network lock" "Not masked,Masked" newline bitfld.long 0x00 0. " SMR ,System masks reset" "Not masked,Masked" rgroup.long 0x1C++0x03 line.long 0x00 "MLB0_VCCR,Version Control Configuration" hexmask.long.byte 0x00 24.--31. 1. " UMA ,User major revision code" hexmask.long.byte 0x00 16.--23. 1. " UMI ,User minor revision code" hexmask.long.byte 0x00 8.--15. 1. " MMA ,MediaLB major revision code" newline hexmask.long.byte 0x00 0.--7. 1. " MMI ,MediaLB minor revision code" group.long 0x20++0x0F line.long 0x00 "MLB0_SBCR,Synchronous Base Address Configuration Register" hexmask.long.word 0x00 16.--31. 1. " SRBA ,Upper half of synchronous receive base address for DMA mode" hexmask.long.word 0x00 0.--15. 1. " STBA ,Upper half of synchronous transmit base address for DMA mode" line.long 0x04 "MLB0_ABCR,Asynchronous Base Address Configuration Register" hexmask.long.word 0x04 16.--31. 1. " ARBA ,Upper half of asynchronous receive base address for DMA mode" hexmask.long.word 0x04 0.--15. 1. " ATBA ,Upper half of asynchronous transmit base address for DMA mode" line.long 0x08 "MLB0_CBCR,Control Base Address Configuration Register" hexmask.long.word 0x08 16.--31. 1. " CRBA ,Upper half of control receive base address for DMA mode" hexmask.long.word 0x08 0.--15. 1. " CTBA ,Upper half of control transmit base address for DMA mode" line.long 0x0C "MLB0_IBCR,Isochronous Base Address Configuration Register" hexmask.long.word 0x0C 16.--31. 1. " IRBA ,Upper half of isochronous receive base address for DMA mode" hexmask.long.word 0x0C 0.--15. 1. " ITBA ,Upper half of isochronous transmit base address for DMA mode" rgroup.long 0x30++0x03 line.long 0x00 "MLB0_CICR,Channel interrupt configuration register" bitfld.long 0x00 15. " CNSU15 ,Channel status update for channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " CNSU14 ,Channel status update for channel 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " CNSU13 ,Channel status update for channel 13" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " CNSU12 ,Channel status update for channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " CNSU11 ,Channel status update for channel 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " CNSU10 ,Channel status update for channel 10" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " CNSU9 ,Channel status update for channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " CNSU8 ,Channel status update for channel 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " CNSU7 ,Channel status update for channel 7" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " CNSU6 ,Channel status update for channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " CNSU5 ,Channel status update for channel 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " CNSU4 ,Channel status update for channel 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " CNSU3 ,Channel status update for channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CNSU2 ,Channel status update for channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " CNSU1 ,Channel status update for channel 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " CNSU0 ,Channel status update for channel 0" "No interrupt,Interrupt" group.long 0x3C++0x03 line.long 0x00 "MLB0_AHBMCTL,AHB Master Control Register" hexmask.long.word 0x00 16.--31. 1. " MAXTRANS ,MAXTRANS" hexmask.long.word 0x00 0.--15. 1. " MCYCNONREQ ,MCYCNONREQ" tree "MLB0_CECR 0--15 and MLB0_CSCR" if (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x00000000) group.long 0x40++0x03 line.long 0x00 "MLB0_CECR_0,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x10000000) group.long 0x40++0x03 line.long 0x00 "MLB0_CECR_0,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x40))&0x6000000)==0x4000000) group.long 0x40++0x03 line.long 0x00 "MLB0_CECR_0,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x40++0x03 line.long 0x00 "MLB0_CECR_0,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x40))&0x6000000)==0x4000000) group.long 0x40++0x03 line.long 0x00 "MLB0_CECR_0,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x40++0x03 line.long 0x00 "MLB0_CECR_0,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x40))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x00000000) group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x10000000) group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x20000000) group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x00000000) group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x10000000) group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x40))&0x30000000)==0x20000000) group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x40+0x04)++0x03 line.long 0x00 "MLB0_CSCR_0,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x00000000) group.long 0x50++0x03 line.long 0x00 "MLB0_CECR_1,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x10000000) group.long 0x50++0x03 line.long 0x00 "MLB0_CECR_1,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x50))&0x6000000)==0x4000000) group.long 0x50++0x03 line.long 0x00 "MLB0_CECR_1,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x50++0x03 line.long 0x00 "MLB0_CECR_1,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x50))&0x6000000)==0x4000000) group.long 0x50++0x03 line.long 0x00 "MLB0_CECR_1,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x50++0x03 line.long 0x00 "MLB0_CECR_1,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x50))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x00000000) group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x10000000) group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x20000000) group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x00000000) group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x10000000) group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x50))&0x30000000)==0x20000000) group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x50+0x04)++0x03 line.long 0x00 "MLB0_CSCR_1,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x00000000) group.long 0x60++0x03 line.long 0x00 "MLB0_CECR_2,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x10000000) group.long 0x60++0x03 line.long 0x00 "MLB0_CECR_2,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x60))&0x6000000)==0x4000000) group.long 0x60++0x03 line.long 0x00 "MLB0_CECR_2,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x60++0x03 line.long 0x00 "MLB0_CECR_2,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x60))&0x6000000)==0x4000000) group.long 0x60++0x03 line.long 0x00 "MLB0_CECR_2,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x60++0x03 line.long 0x00 "MLB0_CECR_2,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x60))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x00000000) group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x10000000) group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x20000000) group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x00000000) group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x10000000) group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x60))&0x30000000)==0x20000000) group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x60+0x04)++0x03 line.long 0x00 "MLB0_CSCR_2,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x00000000) group.long 0x70++0x03 line.long 0x00 "MLB0_CECR_3,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x10000000) group.long 0x70++0x03 line.long 0x00 "MLB0_CECR_3,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x70))&0x6000000)==0x4000000) group.long 0x70++0x03 line.long 0x00 "MLB0_CECR_3,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x70++0x03 line.long 0x00 "MLB0_CECR_3,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x70))&0x6000000)==0x4000000) group.long 0x70++0x03 line.long 0x00 "MLB0_CECR_3,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x70++0x03 line.long 0x00 "MLB0_CECR_3,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x70))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x00000000) group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x10000000) group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x20000000) group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x00000000) group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x10000000) group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x70))&0x30000000)==0x20000000) group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x70+0x04)++0x03 line.long 0x00 "MLB0_CSCR_3,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x00000000) group.long 0x80++0x03 line.long 0x00 "MLB0_CECR_4,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x10000000) group.long 0x80++0x03 line.long 0x00 "MLB0_CECR_4,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x80))&0x6000000)==0x4000000) group.long 0x80++0x03 line.long 0x00 "MLB0_CECR_4,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x80++0x03 line.long 0x00 "MLB0_CECR_4,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x80))&0x6000000)==0x4000000) group.long 0x80++0x03 line.long 0x00 "MLB0_CECR_4,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x80++0x03 line.long 0x00 "MLB0_CECR_4,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x80))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x00000000) group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x10000000) group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x20000000) group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x00000000) group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x10000000) group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x80))&0x30000000)==0x20000000) group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x80+0x04)++0x03 line.long 0x00 "MLB0_CSCR_4,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x00000000) group.long 0x90++0x03 line.long 0x00 "MLB0_CECR_5,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x10000000) group.long 0x90++0x03 line.long 0x00 "MLB0_CECR_5,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x90))&0x6000000)==0x4000000) group.long 0x90++0x03 line.long 0x00 "MLB0_CECR_5,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x90++0x03 line.long 0x00 "MLB0_CECR_5,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x90))&0x6000000)==0x4000000) group.long 0x90++0x03 line.long 0x00 "MLB0_CECR_5,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x90++0x03 line.long 0x00 "MLB0_CECR_5,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x90))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x00000000) group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x10000000) group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x20000000) group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x00000000) group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x10000000) group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x90))&0x30000000)==0x20000000) group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x90+0x04)++0x03 line.long 0x00 "MLB0_CSCR_5,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x00000000) group.long 0xA0++0x03 line.long 0x00 "MLB0_CECR_6,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x10000000) group.long 0xA0++0x03 line.long 0x00 "MLB0_CECR_6,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0xA0))&0x6000000)==0x4000000) group.long 0xA0++0x03 line.long 0x00 "MLB0_CECR_6,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xA0++0x03 line.long 0x00 "MLB0_CECR_6,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0xA0))&0x6000000)==0x4000000) group.long 0xA0++0x03 line.long 0x00 "MLB0_CECR_6,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xA0++0x03 line.long 0x00 "MLB0_CECR_6,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0xA0))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x00000000) group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x10000000) group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x20000000) group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x00000000) group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x10000000) group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xA0))&0x30000000)==0x20000000) group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xA0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_6,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x00000000) group.long 0xB0++0x03 line.long 0x00 "MLB0_CECR_7,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x10000000) group.long 0xB0++0x03 line.long 0x00 "MLB0_CECR_7,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0xB0))&0x6000000)==0x4000000) group.long 0xB0++0x03 line.long 0x00 "MLB0_CECR_7,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xB0++0x03 line.long 0x00 "MLB0_CECR_7,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0xB0))&0x6000000)==0x4000000) group.long 0xB0++0x03 line.long 0x00 "MLB0_CECR_7,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xB0++0x03 line.long 0x00 "MLB0_CECR_7,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0xB0))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x00000000) group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x10000000) group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x20000000) group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x00000000) group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x10000000) group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xB0))&0x30000000)==0x20000000) group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xB0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_7,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x00000000) group.long 0xC0++0x03 line.long 0x00 "MLB0_CECR_8,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x10000000) group.long 0xC0++0x03 line.long 0x00 "MLB0_CECR_8,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0xC0))&0x6000000)==0x4000000) group.long 0xC0++0x03 line.long 0x00 "MLB0_CECR_8,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xC0++0x03 line.long 0x00 "MLB0_CECR_8,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0xC0))&0x6000000)==0x4000000) group.long 0xC0++0x03 line.long 0x00 "MLB0_CECR_8,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xC0++0x03 line.long 0x00 "MLB0_CECR_8,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0xC0))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x00000000) group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x10000000) group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x20000000) group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x00000000) group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x10000000) group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xC0))&0x30000000)==0x20000000) group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xC0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_8,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x00000000) group.long 0xD0++0x03 line.long 0x00 "MLB0_CECR_9,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x10000000) group.long 0xD0++0x03 line.long 0x00 "MLB0_CECR_9,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0xD0))&0x6000000)==0x4000000) group.long 0xD0++0x03 line.long 0x00 "MLB0_CECR_9,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xD0++0x03 line.long 0x00 "MLB0_CECR_9,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0xD0))&0x6000000)==0x4000000) group.long 0xD0++0x03 line.long 0x00 "MLB0_CECR_9,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xD0++0x03 line.long 0x00 "MLB0_CECR_9,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0xD0))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x00000000) group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x10000000) group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x20000000) group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x00000000) group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x10000000) group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xD0))&0x30000000)==0x20000000) group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xD0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_9,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x00000000) group.long 0xE0++0x03 line.long 0x00 "MLB0_CECR_10,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x10000000) group.long 0xE0++0x03 line.long 0x00 "MLB0_CECR_10,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0xE0))&0x6000000)==0x4000000) group.long 0xE0++0x03 line.long 0x00 "MLB0_CECR_10,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xE0++0x03 line.long 0x00 "MLB0_CECR_10,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0xE0))&0x6000000)==0x4000000) group.long 0xE0++0x03 line.long 0x00 "MLB0_CECR_10,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xE0++0x03 line.long 0x00 "MLB0_CECR_10,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0xE0))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x00000000) group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x10000000) group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x20000000) group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x00000000) group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x10000000) group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xE0))&0x30000000)==0x20000000) group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xE0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_10,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x00000000) group.long 0xF0++0x03 line.long 0x00 "MLB0_CECR_11,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x10000000) group.long 0xF0++0x03 line.long 0x00 "MLB0_CECR_11,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0xF0))&0x6000000)==0x4000000) group.long 0xF0++0x03 line.long 0x00 "MLB0_CECR_11,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xF0++0x03 line.long 0x00 "MLB0_CECR_11,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0xF0))&0x6000000)==0x4000000) group.long 0xF0++0x03 line.long 0x00 "MLB0_CECR_11,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0xF0++0x03 line.long 0x00 "MLB0_CECR_11,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0xF0))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x00000000) group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x10000000) group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x20000000) group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x00000000) group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x10000000) group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0xF0))&0x30000000)==0x20000000) group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0xF0+0x04)++0x03 line.long 0x00 "MLB0_CSCR_11,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x00000000) group.long 0x100++0x03 line.long 0x00 "MLB0_CECR_12,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x10000000) group.long 0x100++0x03 line.long 0x00 "MLB0_CECR_12,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x100))&0x6000000)==0x4000000) group.long 0x100++0x03 line.long 0x00 "MLB0_CECR_12,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x100++0x03 line.long 0x00 "MLB0_CECR_12,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x100))&0x6000000)==0x4000000) group.long 0x100++0x03 line.long 0x00 "MLB0_CECR_12,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x100++0x03 line.long 0x00 "MLB0_CECR_12,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x100))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x00000000) group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x10000000) group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x20000000) group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x00000000) group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x10000000) group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x100))&0x30000000)==0x20000000) group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x100+0x04)++0x03 line.long 0x00 "MLB0_CSCR_12,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x00000000) group.long 0x110++0x03 line.long 0x00 "MLB0_CECR_13,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x10000000) group.long 0x110++0x03 line.long 0x00 "MLB0_CECR_13,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x110))&0x6000000)==0x4000000) group.long 0x110++0x03 line.long 0x00 "MLB0_CECR_13,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x110++0x03 line.long 0x00 "MLB0_CECR_13,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x110))&0x6000000)==0x4000000) group.long 0x110++0x03 line.long 0x00 "MLB0_CECR_13,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x110++0x03 line.long 0x00 "MLB0_CECR_13,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x110))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x00000000) group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x10000000) group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x20000000) group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x00000000) group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x10000000) group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x110))&0x30000000)==0x20000000) group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x110+0x04)++0x03 line.long 0x00 "MLB0_CSCR_13,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x00000000) group.long 0x120++0x03 line.long 0x00 "MLB0_CECR_14,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x10000000) group.long 0x120++0x03 line.long 0x00 "MLB0_CECR_14,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x120))&0x6000000)==0x4000000) group.long 0x120++0x03 line.long 0x00 "MLB0_CECR_14,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x120++0x03 line.long 0x00 "MLB0_CECR_14,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x120))&0x6000000)==0x4000000) group.long 0x120++0x03 line.long 0x00 "MLB0_CECR_14,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x120++0x03 line.long 0x00 "MLB0_CECR_14,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x120))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x00000000) group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x10000000) group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x20000000) group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x00000000) group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x10000000) group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x120))&0x30000000)==0x20000000) group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x120+0x04)++0x03 line.long 0x00 "MLB0_CSCR_14,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif if (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x00000000) group.long 0x130++0x03 line.long 0x00 "MLB0_CECR_15,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FSE ,Frame synchronization disabled/enabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 15. " FSCD ,Frame synchronization disable" "No,Yes" newline bitfld.long 0x00 8.--11. " FSPC ,Number of frame synchronous physical channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x10000000) group.long 0x130++0x03 line.long 0x00 "MLB0_CECR_15,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " FCE ,Generation of ReceiverBusy response" "Prohibited,Allowed" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" newline hexmask.long.byte 0x00 8.--15. 1. " IPL ,Packet Length" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" elif (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x20000000) if (((per.l(ad:0xB8008000+0x130))&0x6000000)==0x4000000) group.long 0x130++0x03 line.long 0x00 "MLB0_CECR_15,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x130++0x03 line.long 0x00 "MLB0_CECR_15,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif else if (((per.l(ad:0xB8008000+0x130))&0x6000000)==0x4000000) group.long 0x130++0x03 line.long 0x00 "MLB0_CECR_15,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 27. " PCE ,Reception packet counter disable/enable" "Disabled,Enabled" bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 8.--12. 1. " PCTH ,Packet count threshold" newline hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" else group.long 0x130++0x03 line.long 0x00 "MLB0_CECR_15,Channel entry configuration register" bitfld.long 0x00 31. " CE ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " TR ,Channel transmit select" "Receive,Transmit" bitfld.long 0x00 28.--29. " CT ,Channel type select" "Synchronous,Isochronous,Asynchronous,Control" newline bitfld.long 0x00 25.--26. " MDS ,Channel mode select" "DMA Ping-pong,DMA Circular,IO mode,?..." bitfld.long 0x00 22. " MASK6 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 20. " MASK4 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 19. " MASK3 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " MASK2 ,Channel interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MASK1 ,Channel interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " MASK0 ,Channel interrupt mask" "Not masked,Masked" hexmask.long.byte 0x00 0.--7. 1. " CA ,Channel address" endif endif if (((per.l(ad:0xB8008000+0x130))&0x6000000)==0x4000000) if (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x00000000) group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x10000000) group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate isochronous receive break" "Disabled,Enabled" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" elif (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x20000000) group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enables break generation" "Disabled,Enabled" newline eventfld.long 0x00 9. " STS9 ,Receive packet start bit" "Not started,Started" eventfld.long 0x00 8. " STS8 ,Receive packer abort bit" "Not detected,Detected" eventfld.long 0x00 3. " STS3 ,Transmit service request bit" "Not requested,Requested" newline eventfld.long 0x00 2. " STS2 ,Receive service request bit" "Not requested,Requested" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif else if (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x00000000) group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" newline eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 6. " STS6 ,Lost frame synchronization bit" "No,Yes" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x10000000) group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" rbitfld.long 0x00 18.--19. " IVB ,Isochronous valid bytes" "BCA-5,BCA-4,BCA-3,BCA-2" newline bitfld.long 0x00 17. " GB ,Generate break" "No,Yes" bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 4. " STS4 ,Buffer error bit" "No error,Error" eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" elif (((per.l(ad:0xB8008000+0x130))&0x30000000)==0x20000000) group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" else group.long (0x130+0x04)++0x03 line.long 0x00 "MLB0_CSCR_15,Channel Status Configuration Register" rbitfld.long 0x00 31. " BM ,Buffer empty" "Not empty,Empty" rbitfld.long 0x00 30. " BF ,Buffer full" "Not full,Full" bitfld.long 0x00 17. " GB ,Enable break generation" "Disabled,Enabled" newline bitfld.long 0x00 16. " RDY ,Next buffer ready" "Not ready,Ready" eventfld.long 0x00 11. " STS11 ,First quadlet of previous buffer start bit successfully transmitted or received" "Not succeed,Succeed" eventfld.long 0x00 10. " STS10 ,Last quadlet of previous buffer done bit successfully transmitted or received" "Not succeed,Succeed" newline eventfld.long 0x00 9. " STS9 ,Previous buffer detect break bit" "Not detected,Detected" eventfld.long 0x00 8. " STS8 ,Previous buffer protocol error bit" "No error,Error" eventfld.long 0x00 5. " STS5 ,Host bus error bit" "No error,Error" newline eventfld.long 0x00 3. " STS3 ,Current buffer start bit" "Not started,Started" eventfld.long 0x00 2. " STS2 ,Current buffer done bit" "Succeed,Not succeed" eventfld.long 0x00 1. " STS1 ,Current buffer detect break bit" "Not detected,Detected" newline eventfld.long 0x00 0. " STS0 ,Current buffer protocol error bit" "Not detected,Detected" endif endif tree.end width 17. if (((per.l(ad:0xB8008000+0x48-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x48-0x08))&0x6000000)==0x2000000) rgroup.long 0x48++0x03 line.long 0x00 "MLB0_CCBCR0,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x48++0x03 line.long 0x00 "MLB0_CCBCR0,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x58-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x58-0x08))&0x6000000)==0x2000000) rgroup.long 0x58++0x03 line.long 0x00 "MLB0_CCBCR1,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x58++0x03 line.long 0x00 "MLB0_CCBCR1,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x68-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x68-0x08))&0x6000000)==0x2000000) rgroup.long 0x68++0x03 line.long 0x00 "MLB0_CCBCR2,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x68++0x03 line.long 0x00 "MLB0_CCBCR2,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x78-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x78-0x08))&0x6000000)==0x2000000) rgroup.long 0x78++0x03 line.long 0x00 "MLB0_CCBCR3,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x78++0x03 line.long 0x00 "MLB0_CCBCR3,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x88-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x88-0x08))&0x6000000)==0x2000000) rgroup.long 0x88++0x03 line.long 0x00 "MLB0_CCBCR4,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x88++0x03 line.long 0x00 "MLB0_CCBCR4,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x98-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x98-0x08))&0x6000000)==0x2000000) rgroup.long 0x98++0x03 line.long 0x00 "MLB0_CCBCR5,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x98++0x03 line.long 0x00 "MLB0_CCBCR5,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0xA8-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xA8-0x08))&0x6000000)==0x2000000) rgroup.long 0xA8++0x03 line.long 0x00 "MLB0_CCBCR6,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0xA8++0x03 line.long 0x00 "MLB0_CCBCR6,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0xB8-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xB8-0x08))&0x6000000)==0x2000000) rgroup.long 0xB8++0x03 line.long 0x00 "MLB0_CCBCR7,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0xB8++0x03 line.long 0x00 "MLB0_CCBCR7,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0xC8-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xC8-0x08))&0x6000000)==0x2000000) rgroup.long 0xC8++0x03 line.long 0x00 "MLB0_CCBCR8,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0xC8++0x03 line.long 0x00 "MLB0_CCBCR8,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0xD8-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xD8-0x08))&0x6000000)==0x2000000) rgroup.long 0xD8++0x03 line.long 0x00 "MLB0_CCBCR9,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0xD8++0x03 line.long 0x00 "MLB0_CCBCR9,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0xE8-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xE8-0x08))&0x6000000)==0x2000000) rgroup.long 0xE8++0x03 line.long 0x00 "MLB0_CCBCR10,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0xE8++0x03 line.long 0x00 "MLB0_CCBCR10,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0xF8-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xF8-0x08))&0x6000000)==0x2000000) rgroup.long 0xF8++0x03 line.long 0x00 "MLB0_CCBCR11,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0xF8++0x03 line.long 0x00 "MLB0_CCBCR11,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x108-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x108-0x08))&0x6000000)==0x2000000) rgroup.long 0x108++0x03 line.long 0x00 "MLB0_CCBCR12,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x108++0x03 line.long 0x00 "MLB0_CCBCR12,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x118-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x118-0x08))&0x6000000)==0x2000000) rgroup.long 0x118++0x03 line.long 0x00 "MLB0_CCBCR13,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x118++0x03 line.long 0x00 "MLB0_CCBCR13,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x128-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x128-0x08))&0x6000000)==0x2000000) rgroup.long 0x128++0x03 line.long 0x00 "MLB0_CCBCR14,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x128++0x03 line.long 0x00 "MLB0_CCBCR14,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x138-0x08))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x138-0x08))&0x6000000)==0x2000000) rgroup.long 0x138++0x03 line.long 0x00 "MLB0_CCBCR15,Channel Current Buffer Configuration Register" hexmask.long.word 0x00 16.--31. 1. " BCA ,Buffer current address" hexmask.long.word 0x00 0.--15. 1. " BFA ,Buffer final address" else rgroup.long 0x138++0x03 line.long 0x00 "MLB0_CCBCR15,Channel Current Buffer Configuration Register" endif if (((per.l(ad:0xB8008000+0x4C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x4C-0x0C))&0x6000000)==0x2000000) group.long 0x4C++0x03 line.long 0x00 "MLB0_CNBCR0,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x4C++0x03 line.long 0x00 "MLB0_CNBCR0,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x5C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x5C-0x0C))&0x6000000)==0x2000000) group.long 0x5C++0x03 line.long 0x00 "MLB0_CNBCR1,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x5C++0x03 line.long 0x00 "MLB0_CNBCR1,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x6C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x6C-0x0C))&0x6000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "MLB0_CNBCR2,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x6C++0x03 line.long 0x00 "MLB0_CNBCR2,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x7C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x7C-0x0C))&0x6000000)==0x2000000) group.long 0x7C++0x03 line.long 0x00 "MLB0_CNBCR3,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x7C++0x03 line.long 0x00 "MLB0_CNBCR3,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x8C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x8C-0x0C))&0x6000000)==0x2000000) group.long 0x8C++0x03 line.long 0x00 "MLB0_CNBCR4,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x8C++0x03 line.long 0x00 "MLB0_CNBCR4,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x9C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x9C-0x0C))&0x6000000)==0x2000000) group.long 0x9C++0x03 line.long 0x00 "MLB0_CNBCR5,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x9C++0x03 line.long 0x00 "MLB0_CNBCR5,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0xAC-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xAC-0x0C))&0x6000000)==0x2000000) group.long 0xAC++0x03 line.long 0x00 "MLB0_CNBCR6,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0xAC++0x03 line.long 0x00 "MLB0_CNBCR6,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0xBC-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xBC-0x0C))&0x6000000)==0x2000000) group.long 0xBC++0x03 line.long 0x00 "MLB0_CNBCR7,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0xBC++0x03 line.long 0x00 "MLB0_CNBCR7,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0xCC-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xCC-0x0C))&0x6000000)==0x2000000) group.long 0xCC++0x03 line.long 0x00 "MLB0_CNBCR8,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0xCC++0x03 line.long 0x00 "MLB0_CNBCR8,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0xDC-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xDC-0x0C))&0x6000000)==0x2000000) group.long 0xDC++0x03 line.long 0x00 "MLB0_CNBCR9,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0xDC++0x03 line.long 0x00 "MLB0_CNBCR9,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0xEC-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xEC-0x0C))&0x6000000)==0x2000000) group.long 0xEC++0x03 line.long 0x00 "MLB0_CNBCR10,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0xEC++0x03 line.long 0x00 "MLB0_CNBCR10,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0xFC-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0xFC-0x0C))&0x6000000)==0x2000000) group.long 0xFC++0x03 line.long 0x00 "MLB0_CNBCR11,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0xFC++0x03 line.long 0x00 "MLB0_CNBCR11,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x10C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x10C-0x0C))&0x6000000)==0x2000000) group.long 0x10C++0x03 line.long 0x00 "MLB0_CNBCR12,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x10C++0x03 line.long 0x00 "MLB0_CNBCR12,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x11C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x11C-0x0C))&0x6000000)==0x2000000) group.long 0x11C++0x03 line.long 0x00 "MLB0_CNBCR13,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x11C++0x03 line.long 0x00 "MLB0_CNBCR13,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x12C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x12C-0x0C))&0x6000000)==0x2000000) group.long 0x12C++0x03 line.long 0x00 "MLB0_CNBCR14,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x12C++0x03 line.long 0x00 "MLB0_CNBCR14,Channel next buffer configuration register" endif if (((per.l(ad:0xB8008000+0x13C-0x0C))&0x6000000)==0x0000000)||(((per.l(ad:0xB8008000+0x13C-0x0C))&0x6000000)==0x2000000) group.long 0x13C++0x03 line.long 0x00 "MLB0_CNBCR15,Channel next buffer configuration register" hexmask.long.word 0x00 16.--31. 1. " BSA ,Buffer start address bits" hexmask.long.word 0x00 0.--15. 1. " BEA ,Buffer end address bits" else group.long 0x13C++0x03 line.long 0x00 "MLB0_CNBCR15,Channel next buffer configuration register" endif sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*") group.long 0x280++0x03 line.long 0x00 "MLB0_LCBCR0,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x284++0x03 line.long 0x00 "MLB0_LCBCR1,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x288++0x03 line.long 0x00 "MLB0_LCBCR2,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x28C++0x03 line.long 0x00 "MLB0_LCBCR3,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x290++0x03 line.long 0x00 "MLB0_LCBCR4,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x294++0x03 line.long 0x00 "MLB0_LCBCR5,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x298++0x03 line.long 0x00 "MLB0_LCBCR6,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x29C++0x03 line.long 0x00 "MLB0_LCBCR7,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2A0++0x03 line.long 0x00 "MLB0_LCBCR8,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2A4++0x03 line.long 0x00 "MLB0_LCBCR9,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2A8++0x03 line.long 0x00 "MLB0_LCBCR10,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2AC++0x03 line.long 0x00 "MLB0_LCBCR11,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2B0++0x03 line.long 0x00 "MLB0_LCBCR12,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2B4++0x03 line.long 0x00 "MLB0_LCBCR13,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2B8++0x03 line.long 0x00 "MLB0_LCBCR14,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2BC++0x03 line.long 0x00 "MLB0_LCBCR15,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" else group.long 0x280++0x03 line.long 0x00 "MLB0_LCBCR0,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x290++0x03 line.long 0x00 "MLB0_LCBCR1,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2A0++0x03 line.long 0x00 "MLB0_LCBCR2,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2B0++0x03 line.long 0x00 "MLB0_LCBCR3,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2C0++0x03 line.long 0x00 "MLB0_LCBCR4,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2D0++0x03 line.long 0x00 "MLB0_LCBCR5,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2E0++0x03 line.long 0x00 "MLB0_LCBCR6,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x2F0++0x03 line.long 0x00 "MLB0_LCBCR7,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x300++0x03 line.long 0x00 "MLB0_LCBCR8,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x310++0x03 line.long 0x00 "MLB0_LCBCR9,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x320++0x03 line.long 0x00 "MLB0_LCBCR10,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x330++0x03 line.long 0x00 "MLB0_LCBCR11,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x340++0x03 line.long 0x00 "MLB0_LCBCR12,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x350++0x03 line.long 0x00 "MLB0_LCBCR13,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x360++0x03 line.long 0x00 "MLB0_LCBCR14,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" group.long 0x370++0x03 line.long 0x00 "MLB0_LCBCR15,Local channel buffer configuration register" hexmask.long.byte 0x00 22.--28. 1. " TH ,Buffer threshold" bitfld.long 0x00 13.--18. " BD ,Buffer depth" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" bitfld.long 0x00 0.--5. " SA ,Buffer start address" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*") rgroup.long 0x2FC++0x03 line.long 0x00 "MLB0_MID,MediaLB0 Module Identification Register" endif width 0x0B tree.end endif sif (cpuis("S6J331*")||cpuis("S6J332*")) tree "SADAC (STEREO AUDIO DAC)" base ad:0xB8020400 width 16. group.long 0x00++0x07 line.long 0x00 "SADAC_DAOSR,DAC Over Sampling Register" bitfld.long 0x00 4.--6. " DACCLK ,Analog DAC clock setting" "/8,/10,/16,/2,/1,?..." bitfld.long 0x00 0.--1. " OSR ,Over sampling" "64,128,256,512" line.long 0x04 "SADAC_DACR,DAC Configuration" bitfld.long 0x04 8. " INIT ,Initialize" "No,Yes" bitfld.long 0x04 0. " DAE ,DAC enable" "Disabled,Enabled" rgroup.long 0x08++0x03 line.long 0x00 "SADAC_DABUSY,DAC Busy Register" bitfld.long 0x00 0. " DABUSY ,DAOSR/DACR busy" "Idle,Busy" group.long 0x0C++0x07 line.long 0x00 "SADAC_DACTRL,DAC Control Register" bitfld.long 0x00 16.--20. " FEST ,FIFO empty threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8. " DMAEN ,DMA enable" "Disabled,Enabled" line.long 0x04 "SADAC_DAFLUSH,DAC Flush Register" bitfld.long 0x04 0. " FLUSH ,FIFO flush" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "SADAC_INTRSTAT,Interrupt State Register" setclrfld.long 0x00 3. -0x04 3. 0x04 3. " DMA_ERR_set/clr ,DMA block error" "Disabled,Enabled" setclrfld.long 0x00 2. -0x04 2. 0x04 2. " UDRN_set/clr ,FIFO under-run error" "Disabled,Enabled" newline setclrfld.long 0x00 1. -0x04 1. 0x04 1. " OVFL_set/clr ,FIFO overflow error" "Disabled,Enabled" setclrfld.long 0x00 0. -0x04 0. 0x04 0. " DREQ_set/clr ,Date request" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "SADAC_DPCR,DAC Polarity Configuration Register" bitfld.long 0x00 1. " PCL ,Upper 16-bits (Left-DATA) polarity conversion" "Disabled,Enabled" bitfld.long 0x00 0. " PCR ,Lower 16-bits (Right-DATA) polarity conversion" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x40++0x03 line.long 0x00 "SADAC_DADR0,Data 0 Register" else group.long 0x40++0x03 line.long 0x00 "SADAC_DADR0,Data 0 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x44++0x03 line.long 0x00 "SADAC_DADR1,Data 1 Register" else group.long 0x44++0x03 line.long 0x00 "SADAC_DADR1,Data 1 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x48++0x03 line.long 0x00 "SADAC_DADR2,Data 2 Register" else group.long 0x48++0x03 line.long 0x00 "SADAC_DADR2,Data 2 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x4C++0x03 line.long 0x00 "SADAC_DADR3,Data 3 Register" else group.long 0x4C++0x03 line.long 0x00 "SADAC_DADR3,Data 3 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x50++0x03 line.long 0x00 "SADAC_DADR4,Data 4 Register" else group.long 0x50++0x03 line.long 0x00 "SADAC_DADR4,Data 4 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x54++0x03 line.long 0x00 "SADAC_DADR5,Data 5 Register" else group.long 0x54++0x03 line.long 0x00 "SADAC_DADR5,Data 5 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x58++0x03 line.long 0x00 "SADAC_DADR6,Data 6 Register" else group.long 0x58++0x03 line.long 0x00 "SADAC_DADR6,Data 6 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x5C++0x03 line.long 0x00 "SADAC_DADR7,Data 7 Register" else group.long 0x5C++0x03 line.long 0x00 "SADAC_DADR7,Data 7 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x60++0x03 line.long 0x00 "SADAC_DADR8,Data 8 Register" else group.long 0x60++0x03 line.long 0x00 "SADAC_DADR8,Data 8 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x64++0x03 line.long 0x00 "SADAC_DADR9,Data 9 Register" else group.long 0x64++0x03 line.long 0x00 "SADAC_DADR9,Data 9 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x68++0x03 line.long 0x00 "SADAC_DADR10,Data 10 Register" else group.long 0x68++0x03 line.long 0x00 "SADAC_DADR10,Data 10 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x6C++0x03 line.long 0x00 "SADAC_DADR11,Data 11 Register" else group.long 0x6C++0x03 line.long 0x00 "SADAC_DADR11,Data 11 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x70++0x03 line.long 0x00 "SADAC_DADR12,Data 12 Register" else group.long 0x70++0x03 line.long 0x00 "SADAC_DADR12,Data 12 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x74++0x03 line.long 0x00 "SADAC_DADR13,Data 13 Register" else group.long 0x74++0x03 line.long 0x00 "SADAC_DADR13,Data 13 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x78++0x03 line.long 0x00 "SADAC_DADR14,Data 14 Register" else group.long 0x78++0x03 line.long 0x00 "SADAC_DADR14,Data 14 Register" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*") wgroup.long 0x7C++0x03 line.long 0x00 "SADAC_DADR15,Data 15 Register" else group.long 0x7C++0x03 line.long 0x00 "SADAC_DADR15,Data 15 Register" endif width 0x0B tree.end endif sif !cpuis("S6J335*") tree.open "I2S (INTER IC SOUND)" sif !cpuis("S6J337*") tree "I2S0" base ad:0xB8020C00 width 10. hgroup.long 0x0++0x03 hide.long 0x00 "RXFDAT0,Reception FIFO Data Register 0" in hgroup.long 0x4++0x03 hide.long 0x00 "RXFDAT1,Reception FIFO Data Register 1" in hgroup.long 0x8++0x03 hide.long 0x00 "RXFDAT2,Reception FIFO Data Register 2" in hgroup.long 0xC++0x03 hide.long 0x00 "RXFDAT3,Reception FIFO Data Register 3" in hgroup.long 0x10++0x03 hide.long 0x00 "RXFDAT4,Reception FIFO Data Register 4" in hgroup.long 0x14++0x03 hide.long 0x00 "RXFDAT5,Reception FIFO Data Register 5" in hgroup.long 0x18++0x03 hide.long 0x00 "RXFDAT6,Reception FIFO Data Register 6" in hgroup.long 0x1C++0x03 hide.long 0x00 "RXFDAT7,Reception FIFO Data Register 7" in hgroup.long 0x20++0x03 hide.long 0x00 "RXFDAT8,Reception FIFO Data Register 8" in hgroup.long 0x24++0x03 hide.long 0x00 "RXFDAT9,Reception FIFO Data Register 9" in hgroup.long 0x28++0x03 hide.long 0x00 "RXFDAT10,Reception FIFO Data Register 10" in hgroup.long 0x2C++0x03 hide.long 0x00 "RXFDAT11,Reception FIFO Data Register 11" in hgroup.long 0x30++0x03 hide.long 0x00 "RXFDAT12,Reception FIFO Data Register 12" in hgroup.long 0x34++0x03 hide.long 0x00 "RXFDAT13,Reception FIFO Data Register 13" in hgroup.long 0x38++0x03 hide.long 0x00 "RXFDAT14,Reception FIFO Data Register 14" in hgroup.long 0x3C++0x03 hide.long 0x00 "RXFDAT15,Reception FIFO Data Register 15" in wgroup.long 0x40++0x03 line.long 0x00 "TXFDAT0,Transmission FIFO Data Register 0" wgroup.long 0x44++0x03 line.long 0x00 "TXFDAT1,Transmission FIFO Data Register 1" wgroup.long 0x48++0x03 line.long 0x00 "TXFDAT2,Transmission FIFO Data Register 2" wgroup.long 0x4C++0x03 line.long 0x00 "TXFDAT3,Transmission FIFO Data Register 3" wgroup.long 0x50++0x03 line.long 0x00 "TXFDAT4,Transmission FIFO Data Register 4" wgroup.long 0x54++0x03 line.long 0x00 "TXFDAT5,Transmission FIFO Data Register 5" wgroup.long 0x58++0x03 line.long 0x00 "TXFDAT6,Transmission FIFO Data Register 6" wgroup.long 0x5C++0x03 line.long 0x00 "TXFDAT7,Transmission FIFO Data Register 7" wgroup.long 0x60++0x03 line.long 0x00 "TXFDAT8,Transmission FIFO Data Register 8" wgroup.long 0x64++0x03 line.long 0x00 "TXFDAT9,Transmission FIFO Data Register 9" wgroup.long 0x68++0x03 line.long 0x00 "TXFDAT10,Transmission FIFO Data Register 10" wgroup.long 0x6C++0x03 line.long 0x00 "TXFDAT11,Transmission FIFO Data Register 11" wgroup.long 0x70++0x03 line.long 0x00 "TXFDAT12,Transmission FIFO Data Register 12" wgroup.long 0x74++0x03 line.long 0x00 "TXFDAT13,Transmission FIFO Data Register 13" wgroup.long 0x78++0x03 line.long 0x00 "TXFDAT14,Transmission FIFO Data Register 14" wgroup.long 0x7C++0x03 line.long 0x00 "TXFDAT15,Transmission FIFO Data Register 15" if ((((per.l(ad:0xB8020C00+0x80))&0x1000)==0x00)&&(((per.l(ad:0xB8020C00+0x84))&0x7C00)==0x00)) group.long 0x80++0x03 line.long 0x00 "CNTREG,Control Register" bitfld.long 0x00 26.--31. " CKRT ,Clock divider" "Not divided,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62,/64,/66,/68,/70,/72,/74,/76,/78,/80,/82,/84,/86,/88,/90,/92,/94,/96,/98,/100,/102,/104,/106,/108,/110,/112,/114,/116,/118,/120,/122,/124,/126" hexmask.long.word 0x00 16.--25. 1. " OVHD ,Frame rate control" bitfld.long 0x00 14. " MSKB ,Serial output data in case of invalid/empty frame transmission" "0,1" newline bitfld.long 0x00 13. " MSMD ,Master and slave mode select" "Slave,Master" bitfld.long 0x00 12. " SBFN ,Sub frame construction" "1,2" bitfld.long 0x00 11. " RHLL ,Word construction" "1 word,2 half words" newline bitfld.long 0x00 10. " ECKM ,Clock selector" "Internal,External" bitfld.long 0x00 9. " BEXT ,Bit extension" "0,Sign bit" bitfld.long 0x00 8. " FRUN ,Output mode of frame synchronous signal" "Burst mode,Free-running mode" newline bitfld.long 0x00 7. " MSLB ,Shifting order" "MSB,LSB" bitfld.long 0x00 6. " TXDIS ,Transmitter disable" "No,Yes" bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No,Yes" newline bitfld.long 0x00 4. " SMPL ,Sampling point" "Center,End" bitfld.long 0x00 3. " CPOL ,Clock polarity" "Rising->falling,Falling->raising" bitfld.long 0x00 2. " FSPH ,Frame sync phase" "Before,Same time" newline bitfld.long 0x00 1. " FSLN ,Frame sync pulse width" "1-bit,?..." bitfld.long 0x00 0. " FSPL ,Frame sync polarity" "1,0" else group.long 0x80++0x03 line.long 0x00 "CNTREG,Control Register" bitfld.long 0x00 26.--31. " CKRT ,Clock divider" "Not divided,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62,/64,/66,/68,/70,/72,/74,/76,/78,/80,/82,/84,/86,/88,/90,/92,/94,/96,/98,/100,/102,/104,/106,/108,/110,/112,/114,/116,/118,/120,/122,/124,/126" hexmask.long.word 0x00 16.--25. 1. " OVHD ,Frame rate control" bitfld.long 0x00 14. " MSKB ,Serial output data in case of invalid/empty frame transmission" "0,1" newline bitfld.long 0x00 13. " MSMD ,Master and slave mode select" "Slave,Master" bitfld.long 0x00 12. " SBFN ,Sub frame construction" "1,2" bitfld.long 0x00 11. " RHLL ,Word construction" "1 word,2 half words" newline bitfld.long 0x00 10. " ECKM ,Clock selector" "Internal,External" bitfld.long 0x00 9. " BEXT ,Bit extension" "0,Sign bit" bitfld.long 0x00 8. " FRUN ,Output mode of frame synchronous signal" "Burst mode,Free-running mode" newline bitfld.long 0x00 7. " MSLB ,Shifting order" "MSB,LSB" bitfld.long 0x00 6. " TXDIS ,Transmitter disable" "No,Yes" bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No,Yes" newline bitfld.long 0x00 4. " SMPL ,Sampling point" "Center,End" bitfld.long 0x00 3. " CPOL ,Clock polarity" "Rising->falling,Falling->raising" bitfld.long 0x00 2. " FSPH ,Frame sync phase" "Before,Same time" newline bitfld.long 0x00 1. " FSLN ,Frame sync pulse width" "1-bit,1 channel" bitfld.long 0x00 0. " FSPL ,Frame sync polarity" "1,0" endif if (((per.l(ad:0xB8020C00+0x80))&0x1000)==0x1000) if (((per.l(ad:0xB8020C00+0x80))&0x800)==0x800) group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" bitfld.long 0x00 26.--30. " S1CHN ,Sub frame 1 channel number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." endif bitfld.long 0x00 16.--20. " S1WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." newline bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,?..." endif bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." else group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" bitfld.long 0x00 26.--30. " S1CHN ,Sub frame 1 channel number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 16.--20. " S1WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" newline bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" endif else if (((per.l(ad:0xB8020C00+0x80))&0x800)==0x800) group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." endif bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." endif bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." else group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" endif endif group.long 0x88++0x03 line.long 0x00 "MCR1REG,Channel Control Register 1" bitfld.long 0x00 31. " S0CH[31] ,Sub frame 0 channel enable31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Sub frame 0 channel enable30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Sub frame 0 channel enable29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Sub frame 0 channel enable28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Sub frame 0 channel enable27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Sub frame 0 channel enable26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Sub frame 0 channel enable25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Sub frame 0 channel enable24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Sub frame 0 channel enable23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Sub frame 0 channel enable22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Sub frame 0 channel enable21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Sub frame 0 channel enable20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Sub frame 0 channel enable19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Sub frame 0 channel enable18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Sub frame 0 channel enable17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Sub frame 0 channel enable16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Sub frame 0 channel enable15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Sub frame 0 channel enable14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Sub frame 0 channel enable13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Sub frame 0 channel enable12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Sub frame 0 channel enable11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Sub frame 0 channel enable10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Sub frame 0 channel enable9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Sub frame 0 channel enable8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Sub frame 0 channel enable7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Sub frame 0 channel enable6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Sub frame 0 channel enable5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Sub frame 0 channel enable4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Sub frame 0 channel enable3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Sub frame 0 channel enable2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Sub frame 0 channel enable1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Sub frame 0 channel enable0" "Disabled,Enabled" if (((per.l(ad:0xB8020C00+0x80))&0x1000)==0x1000) group.long 0x8C++0x03 line.long 0x00 "MCR2REG,Channel Control Register 2" bitfld.long 0x00 31. " S1CH[31] ,Sub frame 1 channel enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Sub frame 1 channel enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Sub frame 1 channel enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Sub frame 1 channel enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Sub frame 1 channel enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Sub frame 1 channel enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Sub frame 1 channel enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Sub frame 1 channel enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Sub frame 1 channel enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Sub frame 1 channel enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Sub frame 1 channel enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Sub frame 1 channel enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Sub frame 1 channel enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Sub frame 1 channel enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Sub frame 1 channel enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Sub frame 1 channel enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Sub frame 1 channel enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Sub frame 1 channel enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Sub frame 1 channel enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Sub frame 1 channel enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Sub frame 1 channel enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Sub frame 1 channel enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Sub frame 1 channel enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Sub frame 1 channel enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Sub frame 1 channel enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Sub frame 1 channel enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Sub frame 1 channel enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Sub frame 1 channel enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Sub frame 1 channel enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Sub frame 1 channel enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Sub frame 1 channel enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Sub frame 1 channel enable 0" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "MCR2REG,Channel Control Register 2" endif group.long 0x90++0x13 line.long 0x00 "OPRREG,Operation Control Register" bitfld.long 0x00 24. " RXENB ,Receive enable" "Disabled,Enabled" bitfld.long 0x00 16. " TXENB ,Transmit enable" "Disabled,Enabled" bitfld.long 0x00 0. " START ,I2S enable" "Disabled,Enabled" line.long 0x04 "SRST,Software Reset Register" bitfld.long 0x04 0. " SRST ,Software Reset" "No reset,Reset" line.long 0x08 "INTCNT,Interrupt Control Register" bitfld.long 0x08 30. " TXUD1M ,TX FIFO underflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 29. " TBERM ,TX block size error interrupt mask" "Not masked,Masked" bitfld.long 0x08 28. " FERRM ,Frame error interrupt mask" "Not masked,Masked" newline bitfld.long 0x08 27. " TXUD0M ,TX FIFO underflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 26. " TXOVM ,TX FIFO overflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 25. " TXFDM ,TX DMA mask" "Not masked,Masked" newline bitfld.long 0x08 24. " TXFIM ,TX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x08 21. " RBERM ,RX block size error interrupt mask" "Not masked,Masked" bitfld.long 0x08 20. " RXUDM ,RX FIFO underflow interrupt mask" "Not masked,Masked" newline bitfld.long 0x08 19. " RXOVM ,RX FIFO overflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 18. " EOPM ,EOPI interrupt mask" "Not masked,Masked" bitfld.long 0x08 17. " RXFDM ,RX FIFO DMA mask" "Not masked,Masked" newline bitfld.long 0x08 16. " RXFIM ,RX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x08 8.--11. " TFTH ,TX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--5. " RPTMR ,RX completion timer" "0,54000,108000,216000" newline bitfld.long 0x08 0.--3. " RFTH ,RX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "STATUS,Status Register" rbitfld.long 0x0C 31. " TBERR ,TX block size error" "No error,Error" rbitfld.long 0x0C 30. " RBERR ,RX block size error" "No error,Error" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x0C 29. " FERR ,Frame error" "No error,Error" newline bitfld.long 0x0C 28. " TXUDR1 ,TX FIFO underflow error" "No error,Error" bitfld.long 0x0C 27. " TXUDR0 ,TX FIFO underflow error" "No error,Error" bitfld.long 0x0C 26. " TXOVR ,TX FIFO overflow error" "No error,Error" newline bitfld.long 0x0C 25. " RXUDR ,RX FIFO underflow error" "No error,Error" bitfld.long 0x0C 24. " RXOVR ,RX FIFO overflow error" "No error,Error" bitfld.long 0x0C 19. " EOPI ,Interrupt flag for RX timer" "Not occurred,Occurred" else eventfld.long 0x0C 29. " FERR ,Frame error" "No error,Error" newline eventfld.long 0x0C 28. " TXUDR1 ,TX FIFO underflow error" "No error,Error" eventfld.long 0x0C 27. " TXUDR0 ,TX FIFO underflow error" "No error,Error" eventfld.long 0x0C 26. " TXOVR ,TX FIFO overflow error" "No error,Error" newline eventfld.long 0x0C 25. " RXUDR ,RX FIFO underflow error" "No error,Error" eventfld.long 0x0C 24. " RXOVR ,RX FIFO overflow error" "No error,Error" eventfld.long 0x0C 19. " EOPI ,Interrupt flag for RX timer" "Not occurred,Occurred" endif newline rbitfld.long 0x0C 18. " BSY ,Serial TX busy" "Idle,Busy" rbitfld.long 0x0C 17. " TXFI ,TX FIFO empty" "Not empty,Empty" rbitfld.long 0x0C 16. " RXFI ,RX FIFO full" "Not full,Full" newline hexmask.long.byte 0x0C 8.--15. 1. " TXNUM ,Number of TX FIFO data" hexmask.long.byte 0x0C 0.--7. 1. " RXNUM ,Number of Data in RX FIFO" line.long 0x10 "DMAACT,DMA Activate Register" bitfld.long 0x10 16. " TDMACT ,TX DMA control" "Disabled,Enabled" bitfld.long 0x10 0. " RDMACT ,RX DMA control" "Disabled,Enabled" if (((per.l(ad:0xB8020C00+0x80))&0x2000)==0x2000) group.long 0xA4++0x03 line.long 0x00 "DEBUG,Debug Register" bitfld.long 0x00 0. " DBGE ,Debug enable" "Disabled,Enabled" else hgroup.long 0xA4++0x03 hide.long 0x00 "DEBUG,Debug Register" endif rgroup.long 0xA8++0x03 line.long 0x00 "MIDREG,Module ID Register" width 0x0B tree.end endif tree "I2S1" base ad:0xB8021000 width 10. hgroup.long 0x0++0x03 hide.long 0x00 "RXFDAT0,Reception FIFO Data Register 0" in hgroup.long 0x4++0x03 hide.long 0x00 "RXFDAT1,Reception FIFO Data Register 1" in hgroup.long 0x8++0x03 hide.long 0x00 "RXFDAT2,Reception FIFO Data Register 2" in hgroup.long 0xC++0x03 hide.long 0x00 "RXFDAT3,Reception FIFO Data Register 3" in hgroup.long 0x10++0x03 hide.long 0x00 "RXFDAT4,Reception FIFO Data Register 4" in hgroup.long 0x14++0x03 hide.long 0x00 "RXFDAT5,Reception FIFO Data Register 5" in hgroup.long 0x18++0x03 hide.long 0x00 "RXFDAT6,Reception FIFO Data Register 6" in hgroup.long 0x1C++0x03 hide.long 0x00 "RXFDAT7,Reception FIFO Data Register 7" in hgroup.long 0x20++0x03 hide.long 0x00 "RXFDAT8,Reception FIFO Data Register 8" in hgroup.long 0x24++0x03 hide.long 0x00 "RXFDAT9,Reception FIFO Data Register 9" in hgroup.long 0x28++0x03 hide.long 0x00 "RXFDAT10,Reception FIFO Data Register 10" in hgroup.long 0x2C++0x03 hide.long 0x00 "RXFDAT11,Reception FIFO Data Register 11" in hgroup.long 0x30++0x03 hide.long 0x00 "RXFDAT12,Reception FIFO Data Register 12" in hgroup.long 0x34++0x03 hide.long 0x00 "RXFDAT13,Reception FIFO Data Register 13" in hgroup.long 0x38++0x03 hide.long 0x00 "RXFDAT14,Reception FIFO Data Register 14" in hgroup.long 0x3C++0x03 hide.long 0x00 "RXFDAT15,Reception FIFO Data Register 15" in wgroup.long 0x40++0x03 line.long 0x00 "TXFDAT0,Transmission FIFO Data Register 0" wgroup.long 0x44++0x03 line.long 0x00 "TXFDAT1,Transmission FIFO Data Register 1" wgroup.long 0x48++0x03 line.long 0x00 "TXFDAT2,Transmission FIFO Data Register 2" wgroup.long 0x4C++0x03 line.long 0x00 "TXFDAT3,Transmission FIFO Data Register 3" wgroup.long 0x50++0x03 line.long 0x00 "TXFDAT4,Transmission FIFO Data Register 4" wgroup.long 0x54++0x03 line.long 0x00 "TXFDAT5,Transmission FIFO Data Register 5" wgroup.long 0x58++0x03 line.long 0x00 "TXFDAT6,Transmission FIFO Data Register 6" wgroup.long 0x5C++0x03 line.long 0x00 "TXFDAT7,Transmission FIFO Data Register 7" wgroup.long 0x60++0x03 line.long 0x00 "TXFDAT8,Transmission FIFO Data Register 8" wgroup.long 0x64++0x03 line.long 0x00 "TXFDAT9,Transmission FIFO Data Register 9" wgroup.long 0x68++0x03 line.long 0x00 "TXFDAT10,Transmission FIFO Data Register 10" wgroup.long 0x6C++0x03 line.long 0x00 "TXFDAT11,Transmission FIFO Data Register 11" wgroup.long 0x70++0x03 line.long 0x00 "TXFDAT12,Transmission FIFO Data Register 12" wgroup.long 0x74++0x03 line.long 0x00 "TXFDAT13,Transmission FIFO Data Register 13" wgroup.long 0x78++0x03 line.long 0x00 "TXFDAT14,Transmission FIFO Data Register 14" wgroup.long 0x7C++0x03 line.long 0x00 "TXFDAT15,Transmission FIFO Data Register 15" if ((((per.l(ad:0xB8021000+0x80))&0x1000)==0x00)&&(((per.l(ad:0xB8021000+0x84))&0x7C00)==0x00)) group.long 0x80++0x03 line.long 0x00 "CNTREG,Control Register" bitfld.long 0x00 26.--31. " CKRT ,Clock divider" "Not divided,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62,/64,/66,/68,/70,/72,/74,/76,/78,/80,/82,/84,/86,/88,/90,/92,/94,/96,/98,/100,/102,/104,/106,/108,/110,/112,/114,/116,/118,/120,/122,/124,/126" hexmask.long.word 0x00 16.--25. 1. " OVHD ,Frame rate control" bitfld.long 0x00 14. " MSKB ,Serial output data in case of invalid/empty frame transmission" "0,1" newline bitfld.long 0x00 13. " MSMD ,Master and slave mode select" "Slave,Master" bitfld.long 0x00 12. " SBFN ,Sub frame construction" "1,2" bitfld.long 0x00 11. " RHLL ,Word construction" "1 word,2 half words" newline bitfld.long 0x00 10. " ECKM ,Clock selector" "Internal,External" bitfld.long 0x00 9. " BEXT ,Bit extension" "0,Sign bit" bitfld.long 0x00 8. " FRUN ,Output mode of frame synchronous signal" "Burst mode,Free-running mode" newline bitfld.long 0x00 7. " MSLB ,Shifting order" "MSB,LSB" bitfld.long 0x00 6. " TXDIS ,Transmitter disable" "No,Yes" bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No,Yes" newline bitfld.long 0x00 4. " SMPL ,Sampling point" "Center,End" bitfld.long 0x00 3. " CPOL ,Clock polarity" "Rising->falling,Falling->raising" bitfld.long 0x00 2. " FSPH ,Frame sync phase" "Before,Same time" newline bitfld.long 0x00 1. " FSLN ,Frame sync pulse width" "1-bit,?..." bitfld.long 0x00 0. " FSPL ,Frame sync polarity" "1,0" else group.long 0x80++0x03 line.long 0x00 "CNTREG,Control Register" bitfld.long 0x00 26.--31. " CKRT ,Clock divider" "Not divided,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62,/64,/66,/68,/70,/72,/74,/76,/78,/80,/82,/84,/86,/88,/90,/92,/94,/96,/98,/100,/102,/104,/106,/108,/110,/112,/114,/116,/118,/120,/122,/124,/126" hexmask.long.word 0x00 16.--25. 1. " OVHD ,Frame rate control" bitfld.long 0x00 14. " MSKB ,Serial output data in case of invalid/empty frame transmission" "0,1" newline bitfld.long 0x00 13. " MSMD ,Master and slave mode select" "Slave,Master" bitfld.long 0x00 12. " SBFN ,Sub frame construction" "1,2" bitfld.long 0x00 11. " RHLL ,Word construction" "1 word,2 half words" newline bitfld.long 0x00 10. " ECKM ,Clock selector" "Internal,External" bitfld.long 0x00 9. " BEXT ,Bit extension" "0,Sign bit" bitfld.long 0x00 8. " FRUN ,Output mode of frame synchronous signal" "Burst mode,Free-running mode" newline bitfld.long 0x00 7. " MSLB ,Shifting order" "MSB,LSB" bitfld.long 0x00 6. " TXDIS ,Transmitter disable" "No,Yes" bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No,Yes" newline bitfld.long 0x00 4. " SMPL ,Sampling point" "Center,End" bitfld.long 0x00 3. " CPOL ,Clock polarity" "Rising->falling,Falling->raising" bitfld.long 0x00 2. " FSPH ,Frame sync phase" "Before,Same time" newline bitfld.long 0x00 1. " FSLN ,Frame sync pulse width" "1-bit,1 channel" bitfld.long 0x00 0. " FSPL ,Frame sync polarity" "1,0" endif if (((per.l(ad:0xB8021000+0x80))&0x1000)==0x1000) if (((per.l(ad:0xB8021000+0x80))&0x800)==0x800) group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" bitfld.long 0x00 26.--30. " S1CHN ,Sub frame 1 channel number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." endif bitfld.long 0x00 16.--20. " S1WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." newline bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,?..." endif bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." else group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" bitfld.long 0x00 26.--30. " S1CHN ,Sub frame 1 channel number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 16.--20. " S1WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" newline bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" endif else if (((per.l(ad:0xB8021000+0x80))&0x800)==0x800) group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." endif bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" else bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." endif bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,?..." else group.long 0x84++0x03 line.long 0x00 "MCR0REG,Channel Control Register 0" bitfld.long 0x00 21.--25. " S1CHL ,Sub frame 1 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 10.--14. " S0CHN ,Sub frame 0 channel numbers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline bitfld.long 0x00 5.--9. " S0CHL ,Sub frame 0 channel length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" bitfld.long 0x00 0.--4. " S0WDL ,Sub frame 1 word length" ",,,,,,7bits,8bits,9bits,10bits,11bits,12bits,13bits,14bits,15bits,16bits,17bits,18bits,19bits,20bits,21bits,22bits,23bits,24bits,25bits,26bits,27bits,28bits,29bits,30bits,31bits,32bits" endif endif group.long 0x88++0x03 line.long 0x00 "MCR1REG,Channel Control Register 1" bitfld.long 0x00 31. " S0CH[31] ,Sub frame 0 channel enable31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Sub frame 0 channel enable30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Sub frame 0 channel enable29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Sub frame 0 channel enable28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Sub frame 0 channel enable27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Sub frame 0 channel enable26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Sub frame 0 channel enable25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Sub frame 0 channel enable24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Sub frame 0 channel enable23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Sub frame 0 channel enable22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Sub frame 0 channel enable21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Sub frame 0 channel enable20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Sub frame 0 channel enable19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Sub frame 0 channel enable18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Sub frame 0 channel enable17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Sub frame 0 channel enable16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Sub frame 0 channel enable15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Sub frame 0 channel enable14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Sub frame 0 channel enable13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Sub frame 0 channel enable12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Sub frame 0 channel enable11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Sub frame 0 channel enable10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Sub frame 0 channel enable9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Sub frame 0 channel enable8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Sub frame 0 channel enable7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Sub frame 0 channel enable6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Sub frame 0 channel enable5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Sub frame 0 channel enable4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Sub frame 0 channel enable3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Sub frame 0 channel enable2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Sub frame 0 channel enable1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Sub frame 0 channel enable0" "Disabled,Enabled" if (((per.l(ad:0xB8021000+0x80))&0x1000)==0x1000) group.long 0x8C++0x03 line.long 0x00 "MCR2REG,Channel Control Register 2" bitfld.long 0x00 31. " S1CH[31] ,Sub frame 1 channel enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Sub frame 1 channel enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Sub frame 1 channel enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Sub frame 1 channel enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Sub frame 1 channel enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Sub frame 1 channel enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Sub frame 1 channel enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Sub frame 1 channel enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Sub frame 1 channel enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Sub frame 1 channel enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Sub frame 1 channel enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Sub frame 1 channel enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Sub frame 1 channel enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Sub frame 1 channel enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Sub frame 1 channel enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Sub frame 1 channel enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Sub frame 1 channel enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Sub frame 1 channel enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Sub frame 1 channel enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Sub frame 1 channel enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Sub frame 1 channel enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Sub frame 1 channel enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Sub frame 1 channel enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Sub frame 1 channel enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Sub frame 1 channel enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Sub frame 1 channel enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Sub frame 1 channel enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Sub frame 1 channel enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Sub frame 1 channel enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Sub frame 1 channel enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Sub frame 1 channel enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Sub frame 1 channel enable 0" "Disabled,Enabled" else hgroup.long 0x8C++0x03 hide.long 0x00 "MCR2REG,Channel Control Register 2" endif group.long 0x90++0x13 line.long 0x00 "OPRREG,Operation Control Register" bitfld.long 0x00 24. " RXENB ,Receive enable" "Disabled,Enabled" bitfld.long 0x00 16. " TXENB ,Transmit enable" "Disabled,Enabled" bitfld.long 0x00 0. " START ,I2S enable" "Disabled,Enabled" line.long 0x04 "SRST,Software Reset Register" bitfld.long 0x04 0. " SRST ,Software Reset" "No reset,Reset" line.long 0x08 "INTCNT,Interrupt Control Register" bitfld.long 0x08 30. " TXUD1M ,TX FIFO underflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 29. " TBERM ,TX block size error interrupt mask" "Not masked,Masked" bitfld.long 0x08 28. " FERRM ,Frame error interrupt mask" "Not masked,Masked" newline bitfld.long 0x08 27. " TXUD0M ,TX FIFO underflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 26. " TXOVM ,TX FIFO overflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 25. " TXFDM ,TX DMA mask" "Not masked,Masked" newline bitfld.long 0x08 24. " TXFIM ,TX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x08 21. " RBERM ,RX block size error interrupt mask" "Not masked,Masked" bitfld.long 0x08 20. " RXUDM ,RX FIFO underflow interrupt mask" "Not masked,Masked" newline bitfld.long 0x08 19. " RXOVM ,RX FIFO overflow interrupt mask" "Not masked,Masked" bitfld.long 0x08 18. " EOPM ,EOPI interrupt mask" "Not masked,Masked" bitfld.long 0x08 17. " RXFDM ,RX FIFO DMA mask" "Not masked,Masked" newline bitfld.long 0x08 16. " RXFIM ,RX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x08 8.--11. " TFTH ,TX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--5. " RPTMR ,RX completion timer" "0,54000,108000,216000" newline bitfld.long 0x08 0.--3. " RFTH ,RX FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "STATUS,Status Register" rbitfld.long 0x0C 31. " TBERR ,TX block size error" "No error,Error" rbitfld.long 0x0C 30. " RBERR ,RX block size error" "No error,Error" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x0C 29. " FERR ,Frame error" "No error,Error" newline bitfld.long 0x0C 28. " TXUDR1 ,TX FIFO underflow error" "No error,Error" bitfld.long 0x0C 27. " TXUDR0 ,TX FIFO underflow error" "No error,Error" bitfld.long 0x0C 26. " TXOVR ,TX FIFO overflow error" "No error,Error" newline bitfld.long 0x0C 25. " RXUDR ,RX FIFO underflow error" "No error,Error" bitfld.long 0x0C 24. " RXOVR ,RX FIFO overflow error" "No error,Error" bitfld.long 0x0C 19. " EOPI ,Interrupt flag for RX timer" "Not occurred,Occurred" else eventfld.long 0x0C 29. " FERR ,Frame error" "No error,Error" newline eventfld.long 0x0C 28. " TXUDR1 ,TX FIFO underflow error" "No error,Error" eventfld.long 0x0C 27. " TXUDR0 ,TX FIFO underflow error" "No error,Error" eventfld.long 0x0C 26. " TXOVR ,TX FIFO overflow error" "No error,Error" newline eventfld.long 0x0C 25. " RXUDR ,RX FIFO underflow error" "No error,Error" eventfld.long 0x0C 24. " RXOVR ,RX FIFO overflow error" "No error,Error" eventfld.long 0x0C 19. " EOPI ,Interrupt flag for RX timer" "Not occurred,Occurred" endif newline rbitfld.long 0x0C 18. " BSY ,Serial TX busy" "Idle,Busy" rbitfld.long 0x0C 17. " TXFI ,TX FIFO empty" "Not empty,Empty" rbitfld.long 0x0C 16. " RXFI ,RX FIFO full" "Not full,Full" newline hexmask.long.byte 0x0C 8.--15. 1. " TXNUM ,Number of TX FIFO data" hexmask.long.byte 0x0C 0.--7. 1. " RXNUM ,Number of Data in RX FIFO" line.long 0x10 "DMAACT,DMA Activate Register" bitfld.long 0x10 16. " TDMACT ,TX DMA control" "Disabled,Enabled" bitfld.long 0x10 0. " RDMACT ,RX DMA control" "Disabled,Enabled" if (((per.l(ad:0xB8021000+0x80))&0x2000)==0x2000) group.long 0xA4++0x03 line.long 0x00 "DEBUG,Debug Register" bitfld.long 0x00 0. " DBGE ,Debug enable" "Disabled,Enabled" else hgroup.long 0xA4++0x03 hide.long 0x00 "DEBUG,Debug Register" endif rgroup.long 0xA8++0x03 line.long 0x00 "MIDREG,Module ID Register" width 0x0B tree.end tree.end endif tree "Programmable CRC" base ad:0xB8018000 width 11. group.long 0x00++0x0B line.long 0x00 "CRC0_POLY,CRC Polynomial Register" line.long 0x04 "CRC0_SEED,CRC Seed Register" line.long 0x08 "CRC0_FXOR,CRC Final XOR Register" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*") group.long 0x0C++0x03 line.long 0x00 "CRC0_CFG,CRC Configuration Register" rbitfld.long 0x00 28. " LOCK ,CRC engine status bit" "Ready,Busy" bitfld.long 0x00 26. " CDEN ,DMA request enable bit" "Disabled,Enabled" bitfld.long 0x00 25. " CIEN ,CRC interrupt enable bit to CPU" "Disabled,Enabled" rbitfld.long 0x00 24. " CIRQ ,CRC interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 22.--23. " SZ ,CRC input data size configuration bits" "8,16,24,32" bitfld.long 0x00 16.--21. " LEN ,CRC polynomial/checksum length configuration bits" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 11. " RIBIT ,Reflect input bits" "Disabled,Enabled" bitfld.long 0x00 10. " RIBYT ,Reflect input bytes" "Disabled,Enabled" newline bitfld.long 0x00 9. " ROBIT ,Reflect output bits" "Disabled,Enabled" bitfld.long 0x00 8. " ROBYT ,Reflect output bytes" "Disabled,Enabled" bitfld.long 0x00 0. " CIRQCLR ,Interrupt clear" "No effect,Clear" else group.long 0x0C++0x03 line.long 0x00 "CRC0_CFG,CRC Configuration Register" bitfld.long 0x00 28. " LOCK ,CRC engine status bit" "Ready,Busy" bitfld.long 0x00 26. " CDEN ,DMA request enable bit" "Disabled,Enabled" bitfld.long 0x00 25. " CIEN ,CRC interrupt enable bit to CPU" "Disabled,Enabled" bitfld.long 0x00 24. " CIRQ ,CRC interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 22.--23. " SZ ,CRC input data size configuration bits" "8,16,24,32" rbitfld.long 0x00 16.--21. " LEN ,CRC polynomial/checksum length configuration bits" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x00 11. " RIBIT ,Reflect input bits" "Disabled,Enabled" bitfld.long 0x00 10. " RIBYT ,Reflect input bytes" "Disabled,Enabled" newline bitfld.long 0x00 9. " ROBIT ,Reflect output bits" "Disabled,Enabled" bitfld.long 0x00 8. " ROBYT ,Reflect output bytes" "Disabled,Enabled" bitfld.long 0x00 0. " CIRQCLR ,Interrupt clear" "No effect,Clear" endif group.long 0x10++0x07 line.long 0x00 "CRC0_WR,CRC Write Register" line.long 0x04 "CRC0_RD,CRC Read Register" width 0x0B tree.end sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "CM (Clock Monitor)" base ad:0xB0643000 width 10. group.long 0x00++0x03 line.long 0x00 "CKOTCNTR,CloCk Output Function Control Register" bitfld.long 0x00 24. " ENCLKO ,Clock output enable bit" "Disabled,Enabled" bitfld.long 0x00 8.--10. " CKOUTDIV ,Clock division bits" "Not divided,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 0.--3. " CKSEL ,Clock select bits" "Fast-CR,Slow-CR,Main,Sub,PLL0,CLK_CAN,CLK_LCP0,CLK_LCP0A,SSCG PPL0,CLK_LCP1,CLK_LCP1A,CLK_SYSC0H,,,,Tied to low" width 0x0B tree.end endif sif (cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J336*")) tree "PCMPWM" base ad:0xB8020800 width 25. group.long 0x00++0x13 line.long 0x00 "PCMPWM_CONTROL,PCMPWM Control Register" hexmask.long.byte 0x00 24.--31. 1. " DTVAL ,Dead timer value" bitfld.long 0x00 16.--20. " FEST ,FIFO empty space threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 13. " DOUBLE ,Double mode enable" "Single,Double" newline bitfld.long 0x00 11.--12. " MODE ,Operation mode" "Low-pass filter,Simplified H-bridge,Full H-bridge,?..." bitfld.long 0x00 10. " STEREO ,Stereo mode enable" "Mono,Stereo" bitfld.long 0x00 9. " DBGEN ,Debug mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " DMAEN ,DMA mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " SILENCE ,Silence Module Trigger" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,PCMPWM module enable" "Disabled,Enabled" line.long 0x04 "PCMPWM_OCTRL,PCMPWM Output Control Register" bitfld.long 0x04 17. " LEVL1 ,Output level select channel 1 (AH_BH/AL_BL)" "Low/High,High/Low" bitfld.long 0x04 16. " LEVL0 ,Output level select channel 0 (AH_BH/AL_BL)" "Low/High,High/Low" bitfld.long 0x04 1. " EN1 ,Output enable channel 1" "Disabled,Enabled" newline bitfld.long 0x04 0. " EN0 ,Output enable channel 0" "Disabled,Enabled" line.long 0x08 "PCMPWM_CLKSEL,PCMPWM Clock Select Register" bitfld.long 0x08 0.--1. " CLK_SEL ,Clock select" "/1,/2,/4,/8" line.long 0x0C "PCMPWM_COUNTP,PCMPWM Count Period Register" hexmask.long.word 0x0C 0.--15. 1. " COUNTP ,Count period" line.long 0x10 "PCMPWM_PCMOFFS,PCM Offset Register" hexmask.long.word 0x10 0.--15. 0x01 " PCM_OFFS ,PCM offset" group.long 0x18++0x03 line.long 0x00 "PCMPWM_INTRSTAT_SET/CLR,PCM Interrupt Enable Register" setclrfld.long 0x00 3. -0x04 3. 0x04 3. " DMA_ERR ,DMA block error" "Disabled,Enabled" setclrfld.long 0x00 2. -0x04 2. 0x04 2. " UDRN ,FIFO under-run error" "Disabled,Enabled" setclrfld.long 0x00 1. -0x04 1. 0x04 1. " OVFL ,FIFO overflow error" "Disabled,Enabled" newline setclrfld.long 0x00 0. -0x04 0. 0x04 0. " DREQ ,Data request" "Disabled,Enabled" group.long 0x40++0x03 line.long 0x00 "PCMPWM_DATA0,Data 0 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x44++0x03 line.long 0x00 "PCMPWM_DATA1,Data 1 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x48++0x03 line.long 0x00 "PCMPWM_DATA2,Data 2 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x4C++0x03 line.long 0x00 "PCMPWM_DATA3,Data 3 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x50++0x03 line.long 0x00 "PCMPWM_DATA4,Data 4 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x54++0x03 line.long 0x00 "PCMPWM_DATA5,Data 5 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x58++0x03 line.long 0x00 "PCMPWM_DATA6,Data 6 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x5C++0x03 line.long 0x00 "PCMPWM_DATA7,Data 7 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x60++0x03 line.long 0x00 "PCMPWM_DATA8,Data 8 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x64++0x03 line.long 0x00 "PCMPWM_DATA9,Data 9 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x68++0x03 line.long 0x00 "PCMPWM_DATA10,Data 10 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x6C++0x03 line.long 0x00 "PCMPWM_DATA11,Data 11 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x70++0x03 line.long 0x00 "PCMPWM_DATA12,Data 12 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x74++0x03 line.long 0x00 "PCMPWM_DATA13,Data 13 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x78++0x03 line.long 0x00 "PCMPWM_DATA14,Data 14 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" group.long 0x7C++0x03 line.long 0x00 "PCMPWM_DATA15,Data 15 Register" hexmask.long.word 0x00 16.--31. 1. " Data1 ,Data input channel 1" hexmask.long.word 0x00 0.--15. 1. " Data0 ,Data input channel 0" width 0x0B tree.end endif sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "HYPERBUS (Hyper Bus Interface)" tree "Channel 0" base ad:0xB8028400 width 17. rgroup.long 0x00++0x03 line.long 0x00 "HYPERBUSI0_CSR,Controller Status Register" bitfld.long 0x00 26. " WRSTOERR ,RSTO error in write transaction" "No error,Error" bitfld.long 0x00 25. " WTRSERR ,transaction error in write transaction" "No error,Error" bitfld.long 0x00 24. " WDECERR ,Decode error in write transaction" "No error,Error" bitfld.long 0x00 16. " WACT ,Write transaction active" "Not active,Active" newline bitfld.long 0x00 11. " RDSSTALL ,RDS stall error in read transaction" "No error,Error" bitfld.long 0x00 10. " RRSTOERR ,RSTO error in read transaction" "No error,Error" bitfld.long 0x00 9. " RTRSERR ,Transaction error in read transaction" "No error,Error" bitfld.long 0x00 8. " RDECERR ,Decode error in read transaction" "No error,Error" newline bitfld.long 0x00 0. " RACT ,Read transaction active" "Not active,Active" sif cpuis("S6E2D*")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") group.long 0x04++0x03 line.long 0x00 "HYPERBUSI0_IEN,Interrupt Enable Register" bitfld.long 0x00 31. " INTP ,Interrupt polarity" "Active low,Active high" bitfld.long 0x00 0. " RPCINTE ,HyperBus memory interrupt enable" "Disabled,Enabled" else rgroup.long 0x04++0x03 line.long 0x00 "HYPERBUSI0_IEN,Interrupt Enable Register" bitfld.long 0x00 31. " INTP ,Interrupt polarity" "Active low,Active high" bitfld.long 0x00 0. " RPCINTE ,HyperBus memory interrupt enable" "Disabled,Enabled" endif rgroup.long 0x08++0x03 line.long 0x00 "HYPERBUSI0_ISR,Interrupt Status Register" bitfld.long 0x00 0. " RPCINTS ,HyperBus memory interrupt status" "No interrupt,Interrupt" sif cpuis("S6E2D*") group.long 0x10++0x07 line.long 0x00 "HYPERBUSI0_MBR0,Memory Base Address Register 0" line.long 0x04 "HYPERBUSI0_MBR1,Memory Base Address Register 1" group.long 0x18++0x03 line.long 0x00 "HYPERBUSI0_MCR0,Memory Configuration Register 0" bitfld.long 0x00 17. " CRMO ,Continuous read merging option" "No merging,Merging" bitfld.long 0x00 16. " ACS ,Asymmetry cache system support" "Not supported,Supported" bitfld.long 0x00 5. " CRT ,Configuration register target" "Memory space,Configuration space" newline bitfld.long 0x00 4. " DEVTYPE ,Device type" "HyperFlash,HyperRAM" bitfld.long 0x00 0.--1. " WRAPSIZE ,Wrapped burst size (bytes)" ",64,16,32" group.long 0x1C++0x03 line.long 0x00 "HYPERBUSI0_MCR1,Memory Configuration Register 1" bitfld.long 0x00 17. " CRMO ,Continuous read merging option" "No merging,Merging" bitfld.long 0x00 16. " ACS ,Asymmetry cache system support" "Not supported,Supported" bitfld.long 0x00 5. " CRT ,Configuration register target" "Memory space,Configuration space" newline bitfld.long 0x00 4. " DEVTYPE ,Device type" "HyperFlash,HyperRAM" bitfld.long 0x00 0.--1. " WRAPSIZE ,Wrapped burst size (bytes)" ",64,16,32" group.long 0x20++0x03 line.long 0x00 "HYPERBUSI0_MTR0,Memory Timing Register" bitfld.long 0x00 28.--31. " RCSHI ,Read chip select High between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 24.--27. " WCSHI ,Write chip select high between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 20.--23. " RCSS ,Read chip select setup to next CK rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 16.--19. " WCSS ,Write chip select setup to next CK rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" newline bitfld.long 0x00 12.--15. " RCSH ,Read chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 8.--11. " WCSH ,Write chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 0.--3. " LTCY ,Latency cycle for HyperRAM mode" "5 CK Latency,6 CK Latency,,,,,,,,,,,,,,4 CK Latency" group.long 0x24++0x03 line.long 0x00 "HYPERBUSI0_MTR1,Memory Timing Register" bitfld.long 0x00 28.--31. " RCSHI ,Read chip select High between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 24.--27. " WCSHI ,Write chip select high between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 20.--23. " RCSS ,Read chip select setup to next CK rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 16.--19. " WCSS ,Write chip select setup to next CK rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" newline bitfld.long 0x00 12.--15. " RCSH ,Read chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 8.--11. " WCSH ,Write chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 0.--3. " LTCY ,Latency cycle for HyperRAM mode" "5 CK Latency,6 CK Latency,,,,,,,,,,,,,,4 CK Latency" group.long 0x28++0x07 line.long 0x00 "HYPERBUSI0_GPOR,General Purpose Output Register" bitfld.long 0x00 1. " GP1 ,General purpose output interface" "Low,High" bitfld.long 0x00 0. " GPO ,General purpose output interface" "Low,High" line.long 0x04 "HYPERBUSI0_WPR,Write Protection Register" bitfld.long 0x04 0. " WP ,Write protection" "No protection,Protection" hgroup.long 0x30++0x03 hide.long 0x00 "HYPERBUSI0_TEST,Test Register" else group.long 0x10++0x07 line.long 0x00 "HYPERBUSI0_MBR0,Memory Base Address Register 0" line.long 0x04 "HYPERBUSI0_MBR1,Memory Base Address Register 1" group.long 0x20++0x03 line.long 0x00 "HYPERBUSI0_MCR0,Memory Configuration Register 0" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 31. " MAXEN ,Maximum length enable" "Disabled,Enabled" hexmask.long.word 0x00 18.--26. 1. " MAXLEN ,Maximum length" newline endif bitfld.long 0x00 17. " CRMO ,Continuous read merging option" "No merging,Merging" bitfld.long 0x00 16. " ACS ,Asymmetry cache system support" "Not supported,Supported" bitfld.long 0x00 5. " CRT ,Configuration register target" "Memory space,Configuration space" newline bitfld.long 0x00 4. " DEVTYPE ,Device type" "HyperFlash,HyperRAM" bitfld.long 0x00 0.--1. " WRAPSIZE ,Wrapped burst size (bytes)" ",64,16,32" group.long 0x24++0x03 line.long 0x00 "HYPERBUSI0_MCR1,Memory Configuration Register 1" sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*") bitfld.long 0x00 31. " MAXEN ,Maximum length enable" "Disabled,Enabled" hexmask.long.word 0x00 18.--26. 1. " MAXLEN ,Maximum length" newline endif bitfld.long 0x00 17. " CRMO ,Continuous read merging option" "No merging,Merging" bitfld.long 0x00 16. " ACS ,Asymmetry cache system support" "Not supported,Supported" bitfld.long 0x00 5. " CRT ,Configuration register target" "Memory space,Configuration space" newline bitfld.long 0x00 4. " DEVTYPE ,Device type" "HyperFlash,HyperRAM" bitfld.long 0x00 0.--1. " WRAPSIZE ,Wrapped burst size (bytes)" ",64,16,32" group.long 0x30++0x03 line.long 0x00 "HYPERBUSI0_MTR0,Memory Timing Register" bitfld.long 0x00 28.--31. " RCSHI ,Read chip select high between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 24.--27. " WCSHI ,Write chip select high between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 20.--23. " RCSS ,Read chip select setup to next ck rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 16.--19. " WCSS ,Write chip select setup to next CK rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" newline bitfld.long 0x00 12.--15. " RCSH ,Read chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 8.--11. " WCSH ,Write chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 0.--3. " LTCY ,Latency cycle for HyperRAM mode" "5 CK Latency,6 CK Latency,,,,,,,,,,,,,,4 CK Latency" group.long 0x34++0x03 line.long 0x00 "HYPERBUSI0_MTR1,Memory Timing Register" bitfld.long 0x00 28.--31. " RCSHI ,Read chip select high between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 24.--27. " WCSHI ,Write chip select high between operations" "1.5 CK,2.5 CK,3.5 CK,4.5 CK,5.5 CK,6.5 CK,7.5 CK,8.5 CK,9.5 CK,10.5 CK,11.5 CK,12.5 CK,13.5 CK,14.5 CK,15.5 CK,16.5 CK" bitfld.long 0x00 20.--23. " RCSS ,Read chip select setup to next ck rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 16.--19. " WCSS ,Write chip select setup to next CK rising edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" newline bitfld.long 0x00 12.--15. " RCSH ,Read chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 8.--11. " WCSH ,Write chip select hold after CK falling edge" "1 CK,2 CK,3 CK,4 CK,5 CK,6 CK,7 CK,8 CK,9 CK,10 CK,11 CK,12 CK,13 CK,14 CK,15 CK,16 CK" bitfld.long 0x00 0.--3. " LTCY ,Latency cycle for HyperRAM mode" "5 CK Latency,6 CK Latency,,,,,,,,,,,,,,4 CK Latency" group.long 0x40++0x07 line.long 0x00 "HYPERBUSI0_GPOR,General Purpose Output Register" bitfld.long 0x00 1. " GP1 ,General purpose output interface" "Low,High" bitfld.long 0x00 0. " GPO ,General purpose output interface" "Low,High" line.long 0x04 "HYPERBUSI0_WPR,Write Protection Register" bitfld.long 0x04 0. " WP ,Write protection" "No protection,Protection" hgroup.long 0x48++0x03 hide.long 0x00 "HYPERBUSI0_TEST,Test Register" endif width 0x0B tree.end tree.end endif sif (cpuis("S6J336*")||cpuis("S6J337*")) tree "EPLL (Expand PLL)" base ad:0xB8050000 width 16. if (((per.l(ad:0xB8050000+0x18))&(0x100<<0))==0x00) group.long 0x0++0x07 line.long 0x00 "EXCSVPLL0CFGR0,Expand PLL0 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "EXCSVPLL0CFGR1,Expand PLL00Clock Supervisor Setting Register 1" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Lower-limit threshold value bits" else rgroup.long 0x0++0x07 line.long 0x00 "EXCSVPLL0CFGR0,Expand PLL0 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "EXCSVPLL0CFGR1,Expand PLL00Clock Supervisor Setting Register 1" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Lower-limit threshold value bits" endif if (((per.l(ad:0xB8050000+0x18))&(0x100<<1))==0x00) group.long 0x8++0x07 line.long 0x00 "EXCSVPLL1CFGR0,Expand PLL1 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "EXCSVPLL1CFGR1,Expand PLL01Clock Supervisor Setting Register 1" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Lower-limit threshold value bits" else rgroup.long 0x8++0x07 line.long 0x00 "EXCSVPLL1CFGR0,Expand PLL1 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "EXCSVPLL1CFGR1,Expand PLL01Clock Supervisor Setting Register 1" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Lower-limit threshold value bits" endif if (((per.l(ad:0xB8050000+0x18))&(0x100<<2))==0x00) group.long 0x10++0x07 line.long 0x00 "EXCSVPLL2CFGR0,Expand PLL2 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "EXCSVPLL2CFGR1,Expand PLL02Clock Supervisor Setting Register 1" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Lower-limit threshold value bits" else rgroup.long 0x10++0x07 line.long 0x00 "EXCSVPLL2CFGR0,Expand PLL2 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "EXCSVPLL2CFGR1,Expand PLL02Clock Supervisor Setting Register 1" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Lower-limit threshold value bits" endif group.long 0x18++0x03 line.long 0x00 "EXCSVCFGR,Expand Clock Supervisor Setting Register" bitfld.long 0x00 10. " EXPLL2CSVE ,EXPLL2 clock supervisor enable" "Disabled,Enabled" bitfld.long 0x00 9. " EXPLL1CSVE ,EXPLL1 clock supervisor enable" "Disabled,Enabled" bitfld.long 0x00 8. " EXPLL0CSVE ,EXPLL0 clock supervisor enable" "Disabled,Enabled" rgroup.long 0x1C++0x03 line.long 0x00 "EXCSVERR,Expand Clock Supervisor Error Register" bitfld.long 0x00 10. " EXPLL2IF ,PLL2 abnormality detection error NMI request" "Not detected,Detected" bitfld.long 0x00 9. " EXPLL1IF ,PLL1 abnormality detection error NMI request" "Not detected,Detected" bitfld.long 0x00 8. " EXPLL0IF ,PLL0 abnormality detection error NMI request" "Not detected,Detected" group.long 0x20++0x03 line.long 0x00 "EXCSVERRCLR,Expand Clock Supervisor Error Clear Register" bitfld.long 0x00 10. " EXPLL2ICLR ,PLL2 abnormality detection error interrupt factor clear" "No effect,Clear" bitfld.long 0x00 9. " EXPLL1ICLR ,PLL1 abnormality detection error interrupt factor clear" "No effect,Clear" bitfld.long 0x00 8. " EXPLL0ICLR ,PLL0 abnormality detection error interrupt factor clear" "No effect,Clear" if (((per.l(ad:0xB8050000+0x4C))&(0x100<<0))==0x00) group.long 0x40++0x03 line.long 0x00 "EXPLL0CNTR,Expand PLL0 Control Register" bitfld.long 0x00 24.--27. " PLL0STABS ,Stabilization time for PLL0 clock" ",,,,,,,,^9,^10,^11,^12,^13,^14,^15,^16" hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" newline bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "Not divided,/2,/4,/6" else rgroup.long 0x40++0x03 line.long 0x00 "EXPLL0CNTR,Expand PLL0 Control Register" bitfld.long 0x00 24.--27. " PLL0STABS ,Stabilization time for PLL0 clock" ",,,,,,,,^9,^10,^11,^12,^13,^14,^15,^16" hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" newline bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "Not divided,/2,/4,/6" endif if (((per.l(ad:0xB8050000+0x4C))&(0x100<<1))==0x00) group.long 0x44++0x03 line.long 0x00 "EXPLL1CNTR,Expand PLL1 Control Register" bitfld.long 0x00 24.--27. " PLL1STABS ,Stabilization time for PLL1 clock" ",,,,,,,,^9,^10,^11,^12,^13,^14,^15,^16" hexmask.long.byte 0x00 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL1DIVM ,PLL1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" newline bitfld.long 0x00 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "Not divided,/2,/4,/6" else rgroup.long 0x44++0x03 line.long 0x00 "EXPLL1CNTR,Expand PLL1 Control Register" bitfld.long 0x00 24.--27. " PLL1STABS ,Stabilization time for PLL1 clock" ",,,,,,,,^9,^10,^11,^12,^13,^14,^15,^16" hexmask.long.byte 0x00 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL1DIVM ,PLL1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" newline bitfld.long 0x00 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "Not divided,/2,/4,/6" endif if (((per.l(ad:0xB8050000+0x4C))&(0x100<<2))==0x00) group.long 0x48++0x03 line.long 0x00 "EXPLL2CNTR,Expand PLL2 Control Register" bitfld.long 0x00 24.--27. " PLL2STABS ,Stabilization time for PLL2 clock" ",,,,,,,,^9,^10,^11,^12,^13,^14,^15,^16" hexmask.long.byte 0x00 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL2DIVM ,PLL2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" newline bitfld.long 0x00 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "Not divided,/2,/4,/6" else rgroup.long 0x48++0x03 line.long 0x00 "EXPLL2CNTR,Expand PLL2 Control Register" bitfld.long 0x00 24.--27. " PLL2STABS ,Stabilization time for PLL2 clock" ",,,,,,,,^9,^10,^11,^12,^13,^14,^15,^16" hexmask.long.byte 0x00 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL2DIVM ,PLL2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" newline bitfld.long 0x00 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "Not divided,/2,/4,/6" endif group.long 0x4C++0x03 line.long 0x00 "EXPLLEN,Expand PLL Enable Register" rbitfld.long 0x00 26. " EXPLL2RDY ,EXPLL2 clock oscillation stabilization" "Not stable,Stable" rbitfld.long 0x00 25. " EXPLL1RDY ,EXPLL1 clock oscillation stabilization" "Not stable,Stable" rbitfld.long 0x00 24. " EXPLL0RDY ,EXPLL0 clock oscillation stabilization" "Not stable,Stable" newline bitfld.long 0x00 10. " EXPLL2EN ,EXPLL2 clock enable" "Disabled,Enabled" bitfld.long 0x00 9. " EXPLL1EN ,EXPLL1 clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " EXPLL0EN ,EXPLL0 clock enable" "Disabled,Enabled" if (((per.l(ad:0xB8050000+0x4C))&(0x100<<0))==0x00) group.long 0x50++0x03 line.long 0x00 "EXCKDIVR0,Expand Clock Divider Register 0" bitfld.long 0x00 24.--28. " EXPAND_CLKCD0 ,Expand_CLKCD0 clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 16.--19. " EXPAND_CLKCD0A ,Expand_CLKCD0A clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " EXPAND_CLKCD0B ,Expand_CLKCD0B clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else rgroup.long 0x50++0x03 line.long 0x00 "EXCKDIVR0,Expand Clock Divider Register 0" bitfld.long 0x00 24.--28. " EXPAND_CLKCD0 ,Expand_CLKCD0 clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 16.--19. " EXPAND_CLKCD0A ,Expand_CLKCD0A clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " EXPAND_CLKCD0B ,Expand_CLKCD0B clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif if (((per.l(ad:0xB8050000+0x4C))&(0x100<<1))==0x00) group.long 0x54++0x03 line.long 0x00 "EXCKDIVR1,Expand Clock Divider Register 1" bitfld.long 0x00 24.--28. " EXPAND_CLKCD1 ,Expand_CLKCD1 clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 16.--19. " EXPAND_CLKCD1A ,Expand_CLKCD1A clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " EXPAND_CLKCD1B ,Expand_CLKCD1B clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else rgroup.long 0x54++0x03 line.long 0x00 "EXCKDIVR1,Expand Clock Divider Register 1" bitfld.long 0x00 24.--28. " EXPAND_CLKCD1 ,Expand_CLKCD1 clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 16.--19. " EXPAND_CLKCD1A ,Expand_CLKCD1A clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " EXPAND_CLKCD1B ,Expand_CLKCD1B clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif if (((per.l(ad:0xB8050000+0x4C))&(0x100<<2))==0x00) group.long 0x58++0x03 line.long 0x00 "EXCKDIVR2,Expand Clock Divider Register 2" bitfld.long 0x00 24.--28. " EXPAND_CLKCD2 ,Expand_CLKCD2 clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 16.--19. " EXPAND_CLKCD2A ,Expand_CLKCD2A clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " EXPAND_CLKCD2B ,Expand_CLKCD2B clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else rgroup.long 0x58++0x03 line.long 0x00 "EXCKDIVR2,Expand Clock Divider Register 2" bitfld.long 0x00 24.--28. " EXPAND_CLKCD2 ,Expand_CLKCD2 clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 16.--19. " EXPAND_CLKCD2A ,Expand_CLKCD2A clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 8.--11. " EXPAND_CLKCD2B ,Expand_CLKCD2B clock divider setting bits" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif if (((per.l(ad:0xB8050000+0x4C))&0x4000000)==0x00) group.long 0x5C++0x03 line.long 0x00 "EXPLLSEL,Expand PLL Select Register" bitfld.long 0x00 2. " EXPLLSEL2 ,PLL clock select" "CLK_LCP1,?..." bitfld.long 0x00 1. " EXPLLSEL1 ,PLL clock select" "CLK_LCP1,?..." bitfld.long 0x00 0. " EXPLLSEL0 ,PLL clock select" "CLK_LCP1,?..." else group.long 0x5C++0x03 line.long 0x00 "EXPLLSEL,Expand PLL Select Register" bitfld.long 0x00 2. " EXPLLSEL2 ,PLL clock select" "CLK_LCP1,Expand_PLL" bitfld.long 0x00 1. " EXPLLSEL1 ,PLL clock select" "CLK_LCP1,Expand_PLL" bitfld.long 0x00 0. " EXPLLSEL0 ,PLL clock select" "CLK_LCP1,Expand_PLL" endif width 0x0B tree.end endif sif (!cpuis("S6J335*")) tree "LCDC (LCD CONTROLER)" base ad:0xB48C5C00 width 8. sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.b(ad:0xB48C5C00+0x01))&0x80)==0x00) group.byte 0x01++0x00 line.byte 0x00 "LCR0,LCD Control Register 0" bitfld.byte 0x00 7. " CSS ,Clock selection bit" "Main clock,Sub clock" bitfld.byte 0x00 6. " LCEN ,PSS timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled" bitfld.byte 0x00 5. " VSEL ,LCD drive power control" "Disconnected,Connected" bitfld.byte 0x00 4. " BK ,Blanking selection" "Displayed,Not displayed" bitfld.byte 0x00 2.--3. " MS ,Display mode selection" "Stop,1/2 duty,1/3 duty,1/4 duty" bitfld.byte 0x00 0.--1. " FP ,Frame cycle" "(2^11*N)/Fcl,(2^12*N)/Fcl,(2^13*N)/Fcl,(2^14*N)/Fcl" else group.byte 0x01++0x00 line.byte 0x00 "LCR0,LCD Control Register 0" bitfld.byte 0x00 7. " CSS ,Clock selection bit" "Main clock,Sub clock" bitfld.byte 0x00 6. " LCEN ,PSS timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled" bitfld.byte 0x00 5. " VSEL ,LCD drive power control" "Disconnected,Connected" bitfld.byte 0x00 4. " BK ,Blanking selection" "Displayed,Not displayed" bitfld.byte 0x00 2.--3. " MS ,Display mode selection" "Stop,1/2 duty,1/3 duty,1/4 duty" bitfld.byte 0x00 0.--1. " FP ,Frame cycle" "(2^3*N)/Fcl,(2^4*N)/Fcl,(2^5*N)/Fcl,(2^6*N)/Fcl" endif else group.byte 0x01++0x00 line.byte 0x00 "LCR0,LCD Control Register 0" bitfld.byte 0x00 7. " CSS ,Clock selection bit" "Main clock,Sub clock" bitfld.byte 0x00 6. " LCEN ,PSS timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled" bitfld.byte 0x00 5. " VSEL ,LCD drive power control" "Disconnected,Connected" bitfld.byte 0x00 4. " BK ,Blanking selection" "Displayed,Not displayed" bitfld.byte 0x00 2.--3. " MS ,Display mode selection" "Stop,1/2 duty,1/3 duty,1/4 duty" bitfld.byte 0x00 0.--1. " FP ,Frame cycle" "00,01,10,11" endif group.byte 0x4++0x00 line.byte 0x00 "VRAM3,Data Memory For Display" group.byte 0x5++0x00 line.byte 0x00 "VRAM2,Data Memory For Display" group.byte 0x6++0x00 line.byte 0x00 "VRAM1,Data Memory For Display" group.byte 0x7++0x00 line.byte 0x00 "VRAM0,Data Memory For Display" group.byte 0x8++0x00 line.byte 0x00 "VRAM7,Data Memory For Display" group.byte 0x9++0x00 line.byte 0x00 "VRAM6,Data Memory For Display" group.byte 0xA++0x00 line.byte 0x00 "VRAM5,Data Memory For Display" group.byte 0xB++0x00 line.byte 0x00 "VRAM4,Data Memory For Display" group.byte 0xC++0x00 line.byte 0x00 "VRAM11,Data Memory For Display" group.byte 0xD++0x00 line.byte 0x00 "VRAM10,Data Memory For Display" group.byte 0xE++0x00 line.byte 0x00 "VRAM9,Data Memory For Display" group.byte 0xF++0x00 line.byte 0x00 "VRAM8,Data Memory For Display" group.byte 0x10++0x00 line.byte 0x00 "VRAM15,Data Memory For Display" group.byte 0x11++0x00 line.byte 0x00 "VRAM14,Data Memory For Display" group.byte 0x12++0x00 line.byte 0x00 "VRAM13,Data Memory For Display" group.byte 0x13++0x00 line.byte 0x00 "VRAM12,Data Memory For Display" sif !cpuis("s6j336*")&&!cpuis("s6j337*") hgroup.byte 0x00++0x00 hide.byte 0x00 "LCR1,LCDC Control Register 1" endif group.byte 0x03++0x00 line.byte 0x00 "LCDCMR,Common Pin Switching Register" bitfld.byte 0x00 7. " DTCH ,Bias selection" "1/3,1/2" sif cpuis("s6j336*")||cpuis("s6j337*") if (((per.b(ad:0xB48C5C00+0x02))&0x80)==0x00) group.byte 0x02++0x00 line.byte 0x00 "LCRS,LCDC Static Control Register" bitfld.byte 0x00 7. " SCSS ,Frame cycle generation clock for static drive selection bit" "Main clock,Sub clock" bitfld.byte 0x00 6. " LCSEN ,PSS timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled" bitfld.byte 0x00 2.--5. " LCS ,Static drive selection" "Off,ST0 to ST1,ST0 to ST2,ST0 to ST3,ST0 to ST4,ST0 to ST5,ST0 to ST6,ST0 to ST7,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8" bitfld.byte 0x00 0.--1. " FPS1 ,Frame cycle" "(2^11*N)/Fcl,(2^12*N)/Fcl,(2^13*N)/Fcl,(2^14*N)/Fcl" else group.byte 0x02++0x00 line.byte 0x00 "LCRS,LCDC Static Control Register" bitfld.byte 0x00 7. " SCSS ,Frame cycle generation clock for static drive selection bit" "Main clock,Sub clock" bitfld.byte 0x00 6. " LCSEN ,PSS timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled" bitfld.byte 0x00 2.--5. " LCS ,Static drive selection" "Off,ST0 to ST1,ST0 to ST2,ST0 to ST3,ST0 to ST4,ST0 to ST5,ST0 to ST6,ST0 to ST7,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8" bitfld.byte 0x00 0.--1. " FPS1 ,Frame cycle" "(2^3*N)/Fcl,(2^4*N)/Fcl,(2^5*N)/Fcl,(2^6*N)/Fcl" endif else group.byte 0x02++0x00 line.byte 0x00 "LCRS,LCDC Static Control Register" bitfld.byte 0x00 7. " SCSS ,Frame cycle generation clock for static drive selection bit" "Main clock,Sub clock" bitfld.byte 0x00 6. " LCSEN ,PSS timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled" bitfld.byte 0x00 2.--5. " LCS3 ,Static drive selection" "Off,ST0 to ST1,ST0 to ST2,ST0 to ST3,ST0 to ST4,ST0 to ST5,ST0 to ST6,ST0 to ST7,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,?..." bitfld.byte 0x00 0.--1. " FPS1 ,Frame cycle" "00,01,10,11" endif newline sif (cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")) group.word 0x16++0x01 line.word 0x00 "LDR,Static LCD Display Data Register" bitfld.word 0x00 8. " ST8 ,ST8 static output data" "0,1" bitfld.word 0x00 7. " ST7 ,ST7 static output data" "0,1" bitfld.word 0x00 6. " ST6 ,ST6 static output data" "0,1" bitfld.word 0x00 5. " ST5 ,ST5 static output data" "0,1" bitfld.word 0x00 4. " ST4 ,ST4 static output data" "0,1" bitfld.word 0x00 3. " ST3 ,ST3 static output data" "0,1" newline bitfld.word 0x00 2. " ST2 ,ST2 static output data" "0,1" bitfld.word 0x00 1. " ST1 ,ST1 static output data" "0,1" bitfld.word 0x00 0. " ST0 ,ST0 static output data" "0,1" else group.word 0x14++0x01 line.word 0x00 "LDR,Static LCD Display Data Register" bitfld.word 0x00 8. " ST8 ,Static output data" "0,1" hexmask.word.byte 0x00 0.--7. 1. " ST[0-7] ,Static output data" endif base ad:0xB0641000 width 17. tree "LCDE" sif cpuis("s6j336*")||cpuis("s6j337*") group.long 0x00++0x03 line.long 0x00 "LCDE_LCD_KEYCDR,Key Code Register" bitfld.long 0x00 30.--31. " KEY ,Key code setting bits" "1st,2nd,3rd,4th" bitfld.long 0x00 28.--29. " SIZE ,Access size setting bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x00 0.--11. 0x01 " ADR ,Address specification bits" else wgroup.long 0x00++0x03 line.long 0x00 "LCDE_LCD_KEYCDR,Key Code Register" bitfld.long 0x00 30.--31. " KEY ,Key code setting bits" "1st,2nd,3rd,4th" bitfld.long 0x00 28.--29. " SIZE ,Access size setting bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x00 0.--11. 0x01 " ADR ,Address specification bits" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*") group.long 0x04++0x03 line.long 0x00 "LCDE_SEGER,Segment Output Register" bitfld.long 0x00 31. " SEGE_[7] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 30. " [6] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 29. " [5] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 28. " [4] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 27. " [3] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 26. " [2] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 25. " [1] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 24. " [0] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 23. " [15] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 22. " [14] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 21. " [13] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 20. " [12] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 19. " [11] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 18. " [10] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 17. " [9] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 16. " [8] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 15. " [23] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 14. " [22] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 13. " [21] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 12. " [20] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 11. " [19] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 10. " [18] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 9. " [17] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 8. " [16] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 7. " [31] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 6. " [30] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 5. " [29] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 4. " [28] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 3. " [27] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 2. " [26] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 1. " [25] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 0. " [24] ,LCDC segment output" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "LCDE_SEGER,Segment Output Register" bitfld.long 0x00 31. " SEGE_[31] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 23. " [26] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,LCDC segment output" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,LCDC segment output" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,LCDC segment output" "Disabled,Enabled" endif group.long 0x08++0x03 line.long 0x00 "LCDE_COMVER,Common Output V Pin Control Register" bitfld.long 0x00 31. " VE3 ,Use V3 pin as the LCDC V3 reference voltage input" "VCC,V3" bitfld.long 0x00 30. " VE2 ,Enable LCDC reference voltage input" "Disabled,Enabled" bitfld.long 0x00 29. " VE1 ,Enable LCDC reference voltage input" "Disabled,Enabled" bitfld.long 0x00 28. " VE0 ,Enable LCDC reference voltage input" "Disabled,Enabled" bitfld.long 0x00 27. " COME3 ,Enable LCDC common output" "Disabled,Enabled" bitfld.long 0x00 26. " COME2 ,Enable LCDC common output" "Disabled,Enabled" newline bitfld.long 0x00 25. " COME1 ,Enable LCDC common output" "Disabled,Enabled" bitfld.long 0x00 24. " COME0 ,Enable LCDC common output" "Disabled,Enabled" tree.end width 0x0B tree.end endif tree "INDPWM (INCICATOR PWM)" base ad:0xB0640000 width 15. group.long 0x00++0x07 line.long 0x00 "INDPWM_IPCSR,PWM Cycle Setting Register" hexmask.long.word 0x00 0.--15. 1. " IPCSR ,PWM cycle setting register" line.long 0x04 "INDPWM_IPDUT,PWM Duty Setting Register" hexmask.long.word 0x04 0.--15. 1. " IPDUT ,PWM duty setting register" if (((per.l(ad:0xB0640000+0x0C))&0x08)==0x00) group.long 0x0C++0x03 line.long 0x00 "INDPWM_ITMCR,Timer Control Register" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 24.--25. " CSST ,Source clock selection status bits" "Processing,Main clock,Sub clock,?..." bitfld.long 0x00 16. " CKSEL , Source clock selection bit" "Main clock,Sub clock" newline endif bitfld.long 0x00 12.--14. " CKS ,Count clock selection bits" "Main clock,/16,/64,/256,/1024,/2048,Main clock,Main clock" bitfld.long 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L" bitfld.long 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inversed" else group.long 0x0C++0x03 line.long 0x00 "INDPWM_ITMCR,Timer Control Register" sif cpuis("S6J336*")||cpuis("S6J337*") bitfld.long 0x00 24.--25. " CSST ,Source clock selection status bits" "Processing,Main clock,Sub clock,?..." bitfld.long 0x00 16. " CKSEL ,Source clock selection bit" "Main clock,Sub clock" newline endif bitfld.long 0x00 12.--14. " CKS ,Count clock selection bits" "Main clock,/16,/64,/256,/1024,/2048,Main clock,Main clock" bitfld.long 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H" bitfld.long 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inversed" endif sif (cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("S6J335*")||cpuis("S6J336*")||cpuis("S6J337*")) group.long 0x10++0x03 line.long 0x00 "INDPWM_ICNTCR,Count Control Register" rbitfld.long 0x00 7. " DOP ,Count status bit" "Stopped,In progress" bitfld.long 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "INDPWM_ICNTCR,Count Control Register" bitfld.long 0x00 7. " DOP ,Count status bit" "Stopped,In progress" bitfld.long 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "INDPWM_ISTC,Status Control Register" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable bit" "Disabled,Enabled" rbitfld.long 0x00 1. " DTIR ,Duty match interrupt request bit" "No interrupt,Interrupt" newline rbitfld.long 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt" wgroup.long 0x18++0x03 line.long 0x00 "INDPWM_ISTCC,Status Control Clear Register" bitfld.long 0x00 1. " DTIRC ,Duty match interrupt request clear bit" "Disabled,Cleared" bitfld.long 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "Disabled,Cleared" width 0x0B tree.end sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "MPUX (MEMORY PROTECTION UNIT FOR AXI)" base ad:0xB8000800 width 14. sif !cpuis("S6J336*")&&!cpuis("S6J337*") group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" bitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" else if (((per.l(ad:0xB8000800))&0x11000)==0x11000) group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" rbitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" elif (((per.l(ad:0xB8000800))&0x11000)==0x10000) group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" rbitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" elif (((per.l(ad:0xB8000800))&0x11000)==0x01000) group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" bitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" else group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" bitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" endif endif group.long 0x04++0x03 line.long 0x00 "MPUX0_NMIEN,MPU AXI NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" rgroup.long 0x08++0x0F line.long 0x00 "MPUX0_WERRC,MPU AXI Write Error Control Register" bitfld.long 0x00 8.--10. " AWSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " AWBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x00 2.--5. " AWLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " AWPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x00 0. " AWMPV ,AXI write memory protection violation" "0,1" line.long 0x04 "MPUX0_WERRA,MPU AXI Write Error Address Register" line.long 0x08 "MPUX0_RERRC,MPU AXI Read Error Control Register" bitfld.long 0x08 8.--10. " ARSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 6.--7. " ARBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x08 2.--5. " ARLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 1. " ARPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x08 0. " AWMPV ,AXI read memory protection violation" "0,1" line.long 0x0C "MPUX0_RERRA,MPU AXI Read Error Address Register" sif !cpuis("S6J336*")&&!cpuis("S6J337*") group.long 0x18++0x03 line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "MPUX0_SADDR1,MPU AXI Start Address Register 1" group.long 0x28++0x03 line.long 0x00 "MPUX0_SADDR2,MPU AXI Start Address Register 2" group.long 0x34++0x03 line.long 0x00 "MPUX0_SADDR3,MPU AXI Start Address Register 3" group.long 0x40++0x03 line.long 0x00 "MPUX0_SADDR4,MPU AXI Start Address Register 4" group.long 0x4C++0x03 line.long 0x00 "MPUX0_SADDR5,MPU AXI Start Address Register 5" group.long 0x58++0x03 line.long 0x00 "MPUX0_SADDR6,MPU AXI Start Address Register 6" group.long 0x64++0x03 line.long 0x00 "MPUX0_SADDR7,MPU AXI Start Address Register 7" group.long 0x70++0x03 line.long 0x00 "MPUX0_SADDR8,MPU AXI Start Address Register 8" group.long 0x20++0x03 line.long 0x00 "MPUX0_EADDR1,MPU AXI End Address Register 1" group.long 0x2C++0x03 line.long 0x00 "MPUX0_EADDR2,MPU AXI End Address Register 2" group.long 0x38++0x03 line.long 0x00 "MPUX0_EADDR3,MPU AXI End Address Register 3" group.long 0x44++0x03 line.long 0x00 "MPUX0_EADDR4,MPU AXI End Address Register 4" group.long 0x50++0x03 line.long 0x00 "MPUX0_EADDR5,MPU AXI End Address Register 5" group.long 0x5C++0x03 line.long 0x00 "MPUX0_EADDR6,MPU AXI End Address Register 6" group.long 0x68++0x03 line.long 0x00 "MPUX0_EADDR7,MPU AXI End Address Register 7" group.long 0x74++0x03 line.long 0x00 "MPUX0_EADDR8,MPU AXI End Address Register 8" else if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x18))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x18++0x03 line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x18+0x4)++0x03 line.long 0x00 "MPUX0_SADDR1,MPU AXI Start Address Register 1" rgroup.long (0x18+0x8)++0x03 line.long 0x00 "MPUX0_EADDR1,MPU AXI End Address Register 1" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x18))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x18++0x03 line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x18+0x4)++0x03 line.long 0x00 "MPUX0_SADDR1,MPU AXI Start Address Register 1" rgroup.long (0x18+0x8)++0x03 line.long 0x00 "MPUX0_EADDR1,MPU AXI End Address Register 1" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x18))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x18++0x0B line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR1,MPU AXI Start Address Register 1" line.long 0x08 "MPUX0_EADDR1,MPU AXI End Address Register 1" else group.long 0x18++0x0B line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR1,MPU AXI Start Address Register 1" line.long 0x08 "MPUX0_EADDR1,MPU AXI End Address Register 1" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x24))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x24++0x03 line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x24+0x4)++0x03 line.long 0x00 "MPUX0_SADDR2,MPU AXI Start Address Register 2" rgroup.long (0x24+0x8)++0x03 line.long 0x00 "MPUX0_EADDR2,MPU AXI End Address Register 2" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x24))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x24++0x03 line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x24+0x4)++0x03 line.long 0x00 "MPUX0_SADDR2,MPU AXI Start Address Register 2" rgroup.long (0x24+0x8)++0x03 line.long 0x00 "MPUX0_EADDR2,MPU AXI End Address Register 2" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x24))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x24++0x0B line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR2,MPU AXI Start Address Register 2" line.long 0x08 "MPUX0_EADDR2,MPU AXI End Address Register 2" else group.long 0x24++0x0B line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR2,MPU AXI Start Address Register 2" line.long 0x08 "MPUX0_EADDR2,MPU AXI End Address Register 2" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x30))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x30++0x03 line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x30+0x4)++0x03 line.long 0x00 "MPUX0_SADDR3,MPU AXI Start Address Register 3" rgroup.long (0x30+0x8)++0x03 line.long 0x00 "MPUX0_EADDR3,MPU AXI End Address Register 3" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x30))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x30++0x03 line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x30+0x4)++0x03 line.long 0x00 "MPUX0_SADDR3,MPU AXI Start Address Register 3" rgroup.long (0x30+0x8)++0x03 line.long 0x00 "MPUX0_EADDR3,MPU AXI End Address Register 3" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x30))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x30++0x0B line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR3,MPU AXI Start Address Register 3" line.long 0x08 "MPUX0_EADDR3,MPU AXI End Address Register 3" else group.long 0x30++0x0B line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR3,MPU AXI Start Address Register 3" line.long 0x08 "MPUX0_EADDR3,MPU AXI End Address Register 3" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x3C))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x3C++0x03 line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x3C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR4,MPU AXI Start Address Register 4" rgroup.long (0x3C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR4,MPU AXI End Address Register 4" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x3C))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x3C++0x03 line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x3C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR4,MPU AXI Start Address Register 4" rgroup.long (0x3C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR4,MPU AXI End Address Register 4" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x3C))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x3C++0x0B line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR4,MPU AXI Start Address Register 4" line.long 0x08 "MPUX0_EADDR4,MPU AXI End Address Register 4" else group.long 0x3C++0x0B line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR4,MPU AXI Start Address Register 4" line.long 0x08 "MPUX0_EADDR4,MPU AXI End Address Register 4" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x48))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x48++0x03 line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x48+0x4)++0x03 line.long 0x00 "MPUX0_SADDR5,MPU AXI Start Address Register 5" rgroup.long (0x48+0x8)++0x03 line.long 0x00 "MPUX0_EADDR5,MPU AXI End Address Register 5" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x48))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x48++0x03 line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x48+0x4)++0x03 line.long 0x00 "MPUX0_SADDR5,MPU AXI Start Address Register 5" rgroup.long (0x48+0x8)++0x03 line.long 0x00 "MPUX0_EADDR5,MPU AXI End Address Register 5" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x48))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x48++0x0B line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR5,MPU AXI Start Address Register 5" line.long 0x08 "MPUX0_EADDR5,MPU AXI End Address Register 5" else group.long 0x48++0x0B line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR5,MPU AXI Start Address Register 5" line.long 0x08 "MPUX0_EADDR5,MPU AXI End Address Register 5" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x54))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x54++0x03 line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x54+0x4)++0x03 line.long 0x00 "MPUX0_SADDR6,MPU AXI Start Address Register 6" rgroup.long (0x54+0x8)++0x03 line.long 0x00 "MPUX0_EADDR6,MPU AXI End Address Register 6" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x54))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x54++0x03 line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x54+0x4)++0x03 line.long 0x00 "MPUX0_SADDR6,MPU AXI Start Address Register 6" rgroup.long (0x54+0x8)++0x03 line.long 0x00 "MPUX0_EADDR6,MPU AXI End Address Register 6" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x54))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x54++0x0B line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR6,MPU AXI Start Address Register 6" line.long 0x08 "MPUX0_EADDR6,MPU AXI End Address Register 6" else group.long 0x54++0x0B line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR6,MPU AXI Start Address Register 6" line.long 0x08 "MPUX0_EADDR6,MPU AXI End Address Register 6" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x60))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x60++0x03 line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x60+0x4)++0x03 line.long 0x00 "MPUX0_SADDR7,MPU AXI Start Address Register 7" rgroup.long (0x60+0x8)++0x03 line.long 0x00 "MPUX0_EADDR7,MPU AXI End Address Register 7" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x60))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x60++0x03 line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x60+0x4)++0x03 line.long 0x00 "MPUX0_SADDR7,MPU AXI Start Address Register 7" rgroup.long (0x60+0x8)++0x03 line.long 0x00 "MPUX0_EADDR7,MPU AXI End Address Register 7" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x60))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x60++0x0B line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR7,MPU AXI Start Address Register 7" line.long 0x08 "MPUX0_EADDR7,MPU AXI End Address Register 7" else group.long 0x60++0x0B line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR7,MPU AXI Start Address Register 7" line.long 0x08 "MPUX0_EADDR7,MPU AXI End Address Register 7" endif if (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x6C))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x6C++0x03 line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x6C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR8,MPU AXI Start Address Register 8" rgroup.long (0x6C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR8,MPU AXI End Address Register 8" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x00)||(((per.l(ad:0xB8000800+0x6C))&0x01)!=0x00))&&(((per.l(ad:0xB8000800))&0x1000)==0x00)) group.long 0x6C++0x03 line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x6C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR8,MPU AXI Start Address Register 8" rgroup.long (0x6C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR8,MPU AXI End Address Register 8" elif (((((per.l(ad:0xB8000800))&0x10000)!=0x10000)||(((per.l(ad:0xB8000800+0x6C))&0x01)!=0x01))&&(((per.l(ad:0xB8000800))&0x1000)==0x1000)) group.long 0x6C++0x0B line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR8,MPU AXI Start Address Register 8" line.long 0x08 "MPUX0_EADDR8,MPU AXI End Address Register 8" else group.long 0x6C++0x0B line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR8,MPU AXI Start Address Register 8" line.long 0x08 "MPUX0_EADDR8,MPU AXI End Address Register 8" endif endif group.long 0x78++0x03 line.long 0x00 "MPUX0_UNLOCK,MPU AXI Unlock Register" rgroup.long 0x7C++0x03 line.long 0x00 "MPUX0_MID,MPU AXI Module ID Register" width 0x0B tree.end else tree "MPUX (MEMORY PROTECTION UNIT FOR AXI)" base ad:0xB8040800 width 14. sif !cpuis("S6J336*")&&!cpuis("S6J337*") group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" bitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" else if (((per.l(ad:0xB8040800))&0x11000)==0x11000) group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" rbitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" elif (((per.l(ad:0xB8040800))&0x11000)==0x10000) group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" rbitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" elif (((per.l(ad:0xB8040800))&0x11000)==0x01000) group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" bitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" else group.long 0x00++0x03 line.long 0x00 "MPUX0_CTRL0,MPU AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 17. " MPUENC ,MPU AXI enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AXI enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privilege attribute" "Non-privilege mode,Privilege mode" bitfld.long 0x00 11. " POEN ,Privilege mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" endif endif group.long 0x04++0x03 line.long 0x00 "MPUX0_NMIEN,MPU AXI NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" rgroup.long 0x08++0x0F line.long 0x00 "MPUX0_WERRC,MPU AXI Write Error Control Register" bitfld.long 0x00 8.--10. " AWSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " AWBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x00 2.--5. " AWLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " AWPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x00 0. " AWMPV ,AXI write memory protection violation" "0,1" line.long 0x04 "MPUX0_WERRA,MPU AXI Write Error Address Register" line.long 0x08 "MPUX0_RERRC,MPU AXI Read Error Control Register" bitfld.long 0x08 8.--10. " ARSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 6.--7. " ARBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x08 2.--5. " ARLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 1. " ARPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x08 0. " AWMPV ,AXI read memory protection violation" "0,1" line.long 0x0C "MPUX0_RERRA,MPU AXI Read Error Address Register" sif !cpuis("S6J336*")&&!cpuis("S6J337*") group.long 0x18++0x03 line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "MPUX0_SADDR1,MPU AXI Start Address Register 1" group.long 0x28++0x03 line.long 0x00 "MPUX0_SADDR2,MPU AXI Start Address Register 2" group.long 0x34++0x03 line.long 0x00 "MPUX0_SADDR3,MPU AXI Start Address Register 3" group.long 0x40++0x03 line.long 0x00 "MPUX0_SADDR4,MPU AXI Start Address Register 4" group.long 0x4C++0x03 line.long 0x00 "MPUX0_SADDR5,MPU AXI Start Address Register 5" group.long 0x58++0x03 line.long 0x00 "MPUX0_SADDR6,MPU AXI Start Address Register 6" group.long 0x64++0x03 line.long 0x00 "MPUX0_SADDR7,MPU AXI Start Address Register 7" group.long 0x70++0x03 line.long 0x00 "MPUX0_SADDR8,MPU AXI Start Address Register 8" group.long 0x20++0x03 line.long 0x00 "MPUX0_EADDR1,MPU AXI End Address Register 1" group.long 0x2C++0x03 line.long 0x00 "MPUX0_EADDR2,MPU AXI End Address Register 2" group.long 0x38++0x03 line.long 0x00 "MPUX0_EADDR3,MPU AXI End Address Register 3" group.long 0x44++0x03 line.long 0x00 "MPUX0_EADDR4,MPU AXI End Address Register 4" group.long 0x50++0x03 line.long 0x00 "MPUX0_EADDR5,MPU AXI End Address Register 5" group.long 0x5C++0x03 line.long 0x00 "MPUX0_EADDR6,MPU AXI End Address Register 6" group.long 0x68++0x03 line.long 0x00 "MPUX0_EADDR7,MPU AXI End Address Register 7" group.long 0x74++0x03 line.long 0x00 "MPUX0_EADDR8,MPU AXI End Address Register 8" else if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x18))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x18++0x03 line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x18+0x4)++0x03 line.long 0x00 "MPUX0_SADDR1,MPU AXI Start Address Register 1" rgroup.long (0x18+0x8)++0x03 line.long 0x00 "MPUX0_EADDR1,MPU AXI End Address Register 1" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x18))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x18++0x03 line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x18+0x4)++0x03 line.long 0x00 "MPUX0_SADDR1,MPU AXI Start Address Register 1" rgroup.long (0x18+0x8)++0x03 line.long 0x00 "MPUX0_EADDR1,MPU AXI End Address Register 1" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x18))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x18++0x0B line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR1,MPU AXI Start Address Register 1" line.long 0x08 "MPUX0_EADDR1,MPU AXI End Address Register 1" else group.long 0x18++0x0B line.long 0x00 "MPUX0_CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR1,MPU AXI Start Address Register 1" line.long 0x08 "MPUX0_EADDR1,MPU AXI End Address Register 1" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x24))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x24++0x03 line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x24+0x4)++0x03 line.long 0x00 "MPUX0_SADDR2,MPU AXI Start Address Register 2" rgroup.long (0x24+0x8)++0x03 line.long 0x00 "MPUX0_EADDR2,MPU AXI End Address Register 2" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x24))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x24++0x03 line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x24+0x4)++0x03 line.long 0x00 "MPUX0_SADDR2,MPU AXI Start Address Register 2" rgroup.long (0x24+0x8)++0x03 line.long 0x00 "MPUX0_EADDR2,MPU AXI End Address Register 2" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x24))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x24++0x0B line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR2,MPU AXI Start Address Register 2" line.long 0x08 "MPUX0_EADDR2,MPU AXI End Address Register 2" else group.long 0x24++0x0B line.long 0x00 "MPUX0_CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR2,MPU AXI Start Address Register 2" line.long 0x08 "MPUX0_EADDR2,MPU AXI End Address Register 2" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x30))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x30++0x03 line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x30+0x4)++0x03 line.long 0x00 "MPUX0_SADDR3,MPU AXI Start Address Register 3" rgroup.long (0x30+0x8)++0x03 line.long 0x00 "MPUX0_EADDR3,MPU AXI End Address Register 3" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x30))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x30++0x03 line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x30+0x4)++0x03 line.long 0x00 "MPUX0_SADDR3,MPU AXI Start Address Register 3" rgroup.long (0x30+0x8)++0x03 line.long 0x00 "MPUX0_EADDR3,MPU AXI End Address Register 3" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x30))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x30++0x0B line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR3,MPU AXI Start Address Register 3" line.long 0x08 "MPUX0_EADDR3,MPU AXI End Address Register 3" else group.long 0x30++0x0B line.long 0x00 "MPUX0_CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR3,MPU AXI Start Address Register 3" line.long 0x08 "MPUX0_EADDR3,MPU AXI End Address Register 3" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x3C))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x3C++0x03 line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x3C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR4,MPU AXI Start Address Register 4" rgroup.long (0x3C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR4,MPU AXI End Address Register 4" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x3C))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x3C++0x03 line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x3C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR4,MPU AXI Start Address Register 4" rgroup.long (0x3C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR4,MPU AXI End Address Register 4" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x3C))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x3C++0x0B line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR4,MPU AXI Start Address Register 4" line.long 0x08 "MPUX0_EADDR4,MPU AXI End Address Register 4" else group.long 0x3C++0x0B line.long 0x00 "MPUX0_CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR4,MPU AXI Start Address Register 4" line.long 0x08 "MPUX0_EADDR4,MPU AXI End Address Register 4" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x48))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x48++0x03 line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x48+0x4)++0x03 line.long 0x00 "MPUX0_SADDR5,MPU AXI Start Address Register 5" rgroup.long (0x48+0x8)++0x03 line.long 0x00 "MPUX0_EADDR5,MPU AXI End Address Register 5" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x48))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x48++0x03 line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x48+0x4)++0x03 line.long 0x00 "MPUX0_SADDR5,MPU AXI Start Address Register 5" rgroup.long (0x48+0x8)++0x03 line.long 0x00 "MPUX0_EADDR5,MPU AXI End Address Register 5" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x48))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x48++0x0B line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR5,MPU AXI Start Address Register 5" line.long 0x08 "MPUX0_EADDR5,MPU AXI End Address Register 5" else group.long 0x48++0x0B line.long 0x00 "MPUX0_CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR5,MPU AXI Start Address Register 5" line.long 0x08 "MPUX0_EADDR5,MPU AXI End Address Register 5" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x54))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x54++0x03 line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x54+0x4)++0x03 line.long 0x00 "MPUX0_SADDR6,MPU AXI Start Address Register 6" rgroup.long (0x54+0x8)++0x03 line.long 0x00 "MPUX0_EADDR6,MPU AXI End Address Register 6" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x54))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x54++0x03 line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x54+0x4)++0x03 line.long 0x00 "MPUX0_SADDR6,MPU AXI Start Address Register 6" rgroup.long (0x54+0x8)++0x03 line.long 0x00 "MPUX0_EADDR6,MPU AXI End Address Register 6" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x54))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x54++0x0B line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR6,MPU AXI Start Address Register 6" line.long 0x08 "MPUX0_EADDR6,MPU AXI End Address Register 6" else group.long 0x54++0x0B line.long 0x00 "MPUX0_CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR6,MPU AXI Start Address Register 6" line.long 0x08 "MPUX0_EADDR6,MPU AXI End Address Register 6" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x60))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x60++0x03 line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x60+0x4)++0x03 line.long 0x00 "MPUX0_SADDR7,MPU AXI Start Address Register 7" rgroup.long (0x60+0x8)++0x03 line.long 0x00 "MPUX0_EADDR7,MPU AXI End Address Register 7" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x60))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x60++0x03 line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x60+0x4)++0x03 line.long 0x00 "MPUX0_SADDR7,MPU AXI Start Address Register 7" rgroup.long (0x60+0x8)++0x03 line.long 0x00 "MPUX0_EADDR7,MPU AXI End Address Register 7" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x60))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x60++0x0B line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR7,MPU AXI Start Address Register 7" line.long 0x08 "MPUX0_EADDR7,MPU AXI End Address Register 7" else group.long 0x60++0x0B line.long 0x00 "MPUX0_CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR7,MPU AXI Start Address Register 7" line.long 0x08 "MPUX0_EADDR7,MPU AXI End Address Register 7" endif if (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x6C))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x6C++0x03 line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x6C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR8,MPU AXI Start Address Register 8" rgroup.long (0x6C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR8,MPU AXI End Address Register 8" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x00)||(((per.l(ad:0xB8040800+0x6C))&0x01)!=0x00))&&(((per.l(ad:0xB8040800))&0x1000)==0x00)) group.long 0x6C++0x03 line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" rbitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" rgroup.long (0x6C+0x4)++0x03 line.long 0x00 "MPUX0_SADDR8,MPU AXI Start Address Register 8" rgroup.long (0x6C+0x8)++0x03 line.long 0x00 "MPUX0_EADDR8,MPU AXI End Address Register 8" elif (((((per.l(ad:0xB8040800))&0x10000)!=0x10000)||(((per.l(ad:0xB8040800+0x6C))&0x01)!=0x01))&&(((per.l(ad:0xB8040800))&0x1000)==0x1000)) group.long 0x6C++0x0B line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,R/W,R/W,R/W,No access,RO,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR8,MPU AXI Start Address Register 8" line.long 0x08 "MPUX0_EADDR8,MPU AXI End Address Register 8" else group.long 0x6C++0x0B line.long 0x00 "MPUX0_CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "No access,No access,RO,R/W,No access,No access,RO,R/W" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" line.long 0x04 "MPUX0_SADDR8,MPU AXI Start Address Register 8" line.long 0x08 "MPUX0_EADDR8,MPU AXI End Address Register 8" endif endif group.long 0x78++0x03 line.long 0x00 "MPUX0_UNLOCK,MPU AXI Unlock Register" rgroup.long 0x7C++0x03 line.long 0x00 "MPUX0_MID,MPU AXI Module ID Register" width 0x0B tree.end endif sif (!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "MPUAHB (MEMORY PROTECTION UNIT FOR AHB)" base ad:0xB8008400 width 14. group.long 0x00++0x03 line.long 0x00 "MPUH1_CTRL0,MPU AHB Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged mode,Privileged mode" bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU STOP feature" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" textline " " rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" group.long 0x04++0x03 line.long 0x00 "MPUH1_NMIEN,MPU AHB NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" rgroup.long 0x08++0x03 line.long 0x00 "MPUH1_MERRC,MPU AHB Memory Error Control Register" bitfld.long 0x00 1. " HPROT ,AHB transfer privileged mode" "0,1" bitfld.long 0x00 0. " HWRITE ,AHB transfer mode" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "MPUH1_MERRA,MPU AHB Memory Error Address Register" group.long 0x10++0x03 line.long 0x00 "MPUH1_CTRL1,MPU AHB Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "MPUH1_CTRL2,MPU AHB Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "MPUH1_CTRL3,MPU AHB Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "MPUH1_CTRL4,MPU AHB Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x40++0x03 line.long 0x00 "MPUH1_CTRL5,MPU AHB Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x4C++0x03 line.long 0x00 "MPUH1_CTRL6,MPU AHB Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "MPUH1_CTRL7,MPU AHB Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x64++0x03 line.long 0x00 "MPUH1_CTRL8,MPU AHB Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "MPUH1_SADDR1,MPU AHB Start Address Register 1" group.long 0x20++0x03 line.long 0x00 "MPUH1_SADDR2,MPU AHB Start Address Register 2" group.long 0x2C++0x03 line.long 0x00 "MPUH1_SADDR3,MPU AHB Start Address Register 3" group.long 0x38++0x03 line.long 0x00 "MPUH1_SADDR4,MPU AHB Start Address Register 4" group.long 0x44++0x03 line.long 0x00 "MPUH1_SADDR5,MPU AHB Start Address Register 5" group.long 0x50++0x03 line.long 0x00 "MPUH1_SADDR6,MPU AHB Start Address Register 6" group.long 0x5C++0x03 line.long 0x00 "MPUH1_SADDR7,MPU AHB Start Address Register 7" group.long 0x68++0x03 line.long 0x00 "MPUH1_SADDR8,MPU AHB Start Address Register 8" group.long 0x18++0x03 line.long 0x00 "MPUH1_EADDR1,MPU AHB End Address Register 1" group.long 0x24++0x03 line.long 0x00 "MPUH1_EADDR2,MPU AHB End Address Register 2" group.long 0x30++0x03 line.long 0x00 "MPUH1_EADDR3,MPU AHB End Address Register 3" group.long 0x3C++0x03 line.long 0x00 "MPUH1_EADDR4,MPU AHB End Address Register 4" group.long 0x48++0x03 line.long 0x00 "MPUH1_EADDR5,MPU AHB End Address Register 5" group.long 0x54++0x03 line.long 0x00 "MPUH1_EADDR6,MPU AHB End Address Register 6" group.long 0x60++0x03 line.long 0x00 "MPUH1_EADDR7,MPU AHB End Address Register 7" group.long 0x6C++0x03 line.long 0x00 "MPUH1_EADDR8,MPU AHB End Address Register 8" wgroup.long 0x70++0x03 line.long 0x00 "MPUH1_UNLOCK,MPU AHB Unlock Register" rgroup.long 0x74++0x03 line.long 0x00 "MPUH1_MID,MPU AHB Module ID Register" width 0x0B tree.end endif sif (cpuis("S6J331*")) tree "ARH (Automotive Remote Handler)" base ad:0xB8030000 width 11. group.long 0x00++0x03 line.long 0x00 "RHCTRL,ARH Remote Handler Control Register" bitfld.long 0x00 31. " UNLOCK ,Transaction buffer unlock request" "Not requested,Requested" bitfld.long 0x00 30. " CANCEL ,Transaction buffer cancel request" "Not requested,Requested" bitfld.long 0x00 24.--27. " TBNO ,Transaction buffer number trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " WDG1 ,Watch dog timer 1 interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x00 14. " WDG0 ,Watch dog timer 0 interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 13. " FAT1 ,Fatal interrupt status from channel 1" "No interrupt,Interrupt" rbitfld.long 0x00 12. " FAT0 ,Fatal interrupt status from channel 0" "No interrupt,Interrupt" rbitfld.long 0x00 10. " LV ,Level interrupt status" "No interrupt,Interrupt" newline rbitfld.long 0x00 9. " OFL ,Event overflow interrupt status" "No interrupt,Interrupt" rbitfld.long 0x00 8. " EV ,Event interrupt status" "No interrupt,Interrupt" rbitfld.long 0x00 0. " LST ,ARH lock status" "Unlocked,Locked" if ((per.l(ad:0xB8030000)&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "CHCTRL0,ARH Channel Control Register" bitfld.long 0x00 31. " BYPASS ,BYPASS mode" "No bypass,Bypass" bitfld.long 0x00 30. " FATEIN ,FATAL interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " PHYPLLRST ,Reset for PLL" "No reset,Reset" bitfld.long 0x00 26. " TXCFG ,A-Shell configuration" "Disabled,Enabled" newline bitfld.long 0x00 25. " RSTRTA ,A-Shell restart" "Normal,Restart" bitfld.long 0x00 24. " INITRH ,Remote handler initialization" "No initialization,Initialization" rbitfld.long 0x00 22. " PHYPLLGOOD ,APIX PHY PLL lock status" "Unlocked,Locked" rbitfld.long 0x00 21. " PLLGOOD ,APIX PHY PLL lock status" "Unlocked,Locked" newline rbitfld.long 0x00 20. " UPHSK ,Upstream handshake" "Not performed,Performed" rbitfld.long 0x00 19. " DNHSK ,Downstream handshake" "Not performed,Performed" rbitfld.long 0x00 18. " FATAL ,Fatal from A-Shell" "Not occurred,Occurred" rbitfld.long 0x00 17. " UPRDY ,Upstream serial channel operation" "Not operational,Operational" newline rbitfld.long 0x00 16. " CONNECTED ,Connection established" "Not connected,Connected" rbitfld.long 0x00 15. " UPVALID ,Upstream data valid status" "Not valid,Valid" rbitfld.long 0x00 14. " DNVALID ,Downstream data valid status" "Not valid,Valid" rbitfld.long 0x00 13. " FATIRQ ,Fatal interrupt status" "No interrupt,Interrupt" newline rbitfld.long 0x00 12. " CRCERR ,CRC error status in upstream data" "No error,Error" rbitfld.long 0x00 11. " CRCTOUT ,CRC timeout status in upstream data" "Not occurred,Occurred" rbitfld.long 0x00 10. " PERROR ,Protocol error status" "No error,Error" rbitfld.long 0x00 9. " READY ,A-Shell ready status" "Not ready,Ready" newline rbitfld.long 0x00 8. " REMOTERST ,Remote A-Shell restart status" "Not occurred,Occurred" bitfld.long 0x00 7. " UPVALIDCL ,Clear upstream data valid status" "No effect,Cleared" bitfld.long 0x00 6. " DNVALIDST ,Set downstream data valid status" "No effect,Set" bitfld.long 0x00 5. " FATIRQCL ,Clear fatal IRQ interrupt status" "No effect,Cleared" newline bitfld.long 0x00 4. " CRCERRCL ,Clear CRC error in upstream data status" "No effect,Cleared" bitfld.long 0x00 3. " CRCTOUTCL ,Clear CRC timeout in upstream data status" "No effect,Cleared" bitfld.long 0x00 2. " PERRORCL ,Clear protocol error status" "No error,Error" bitfld.long 0x00 1. " READYCL ,Clear A-Shell ready status" "No effect,Cleared" newline bitfld.long 0x00 0. " REMOTERSTCL ,Clear remote A-Shell restart status" "No effect,Cleared" group.long 0x14++0x03 line.long 0x00 "CHCTRL1,ARH Channel Control Register" bitfld.long 0x00 31. " BYPASS ,BYPASS mode" "No bypass,Bypass" bitfld.long 0x00 30. " FATEIN ,FATAL interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TXCFG ,A-Shell configuration" "Disabled,Enabled" bitfld.long 0x00 25. " RSTRTA ,A-Shell restart" "Normal,Restart" newline bitfld.long 0x00 24. " INITRH ,Remote handler initialization" "No initialization,Initialization" rbitfld.long 0x00 21. " PLLGOOD ,APIX PHY PLL lock status" "Unlocked,Locked" rbitfld.long 0x00 20. " UPHSK ,Upstream handshake" "Not performed,Performed" rbitfld.long 0x00 19. " DNHSK ,Downstream handshake" "Not performed,Performed" newline rbitfld.long 0x00 18. " FATAL ,Fatal from A-Shell" "Not occurred,Occurred" rbitfld.long 0x00 17. " UPRDY ,Upstream serial channel operation" "Not operational,Operational" rbitfld.long 0x00 16. " CONNECTED ,Connection established" "Not connected,Connected" rbitfld.long 0x00 15. " UPVALID ,Upstream data valid status" "Not valid,Valid" newline rbitfld.long 0x00 14. " DNVALID ,Downstream data valid status" "Not valid,Valid" rbitfld.long 0x00 13. " FATIRQ ,Fatal interrupt status" "No interrupt,Interrupt" rbitfld.long 0x00 12. " CRCERR ,CRC error status in upstream data" "No error,Error" rbitfld.long 0x00 11. " CRCTOUT ,CRC timeout status in upstream data" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " PERROR ,Protocol error status" "No error,Error" rbitfld.long 0x00 9. " READY ,A-Shell ready status" "Not ready,Ready" rbitfld.long 0x00 8. " REMOTERST ,Remote A-Shell restart status" "Not occurred,Occurred" bitfld.long 0x00 7. " UPVALIDCL ,Clear upstream data valid status" "No effect,Cleared" newline bitfld.long 0x00 6. " DNVALIDST ,Set downstream data valid status" "No effect,Set" bitfld.long 0x00 5. " FATIRQCL ,Clear fatal IRQ interrupt status" "No effect,Cleared" bitfld.long 0x00 4. " CRCERRCL ,Clear CRC error in upstream data status" "No effect,Cleared" bitfld.long 0x00 3. " CRCTOUTCL ,Clear CRC timeout in upstream data status" "No effect,Cleared" newline bitfld.long 0x00 2. " PERRORCL ,Clear protocol error status" "No error,Error" bitfld.long 0x00 1. " READYCL ,Clear A-Shell ready status" "No effect,Cleared" bitfld.long 0x00 0. " REMOTERSTCL ,Clear remote A-Shell restart status" "No effect,Cleared" else rgroup.long 0x04++0x03 line.long 0x00 "CHCTRL0,ARH Channel Control Register" bitfld.long 0x00 31. " BYPASS ,BYPASS mode" "No bypass,Bypass" bitfld.long 0x00 30. " FATEIN ,FATAL interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " PHYPLLRST ,Reset for PLL" "No reset,Reset" bitfld.long 0x00 26. " TXCFG ,A-Shell configuration" "Disabled,Enabled" newline bitfld.long 0x00 25. " RSTRTA ,A-Shell restart" "Normal,Restart" bitfld.long 0x00 24. " INITRH ,Remote handler initialization" "No initialization,Initialization" bitfld.long 0x00 22. " PHYPLLGOOD ,APIX PHY PLL lock status" "Unlocked,Locked" bitfld.long 0x00 21. " PLLGOOD ,APIX PHY PLL lock status" "Unlocked,Locked" newline bitfld.long 0x00 20. " UPHSK ,Upstream handshake" "Not performed,Performed" bitfld.long 0x00 19. " DNHSK ,Downstream handshake" "Not performed,Performed" bitfld.long 0x00 18. " FATAL ,Fatal from A-Shell" "Not occurred,Occurred" bitfld.long 0x00 17. " UPRDY ,Upstream serial channel operation" "Not operational,Operational" newline bitfld.long 0x00 16. " CONNECTED ,Connection established" "Not connected,Connected" bitfld.long 0x00 15. " UPVALID ,Upstream data valid status" "Not valid,Valid" bitfld.long 0x00 14. " DNVALID ,Downstream data valid status" "Not valid,Valid" bitfld.long 0x00 13. " FATIRQ ,Fatal interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " CRCERR ,CRC error status in upstream data" "No error,Error" bitfld.long 0x00 11. " CRCTOUT ,CRC timeout status in upstream data" "Not occurred,Occurred" bitfld.long 0x00 10. " PERROR ,Protocol error status" "No error,Error" bitfld.long 0x00 9. " READY ,A-Shell ready status" "Not ready,Ready" newline bitfld.long 0x00 8. " REMOTERST ,Remote A-Shell restart status" "Not occurred,Occurred" bitfld.long 0x00 7. " UPVALIDCL ,Clear upstream data valid status" "No effect,Cleared" bitfld.long 0x00 6. " DNVALIDST ,Set downstream data valid status" "No effect,Set" bitfld.long 0x00 5. " FATIRQCL ,Clear fatal IRQ interrupt status" "No effect,Cleared" newline bitfld.long 0x00 4. " CRCERRCL ,Clear CRC error in upstream data status" "No effect,Cleared" bitfld.long 0x00 3. " CRCTOUTCL ,Clear CRC timeout in upstream data status" "No effect,Cleared" bitfld.long 0x00 2. " PERRORCL ,Clear protocol error status" "No error,Error" bitfld.long 0x00 1. " READYCL ,Clear A-Shell ready status" "No effect,Cleared" newline bitfld.long 0x00 0. " REMOTERSTCL ,Clear remote A-Shell restart status" "No effect,Cleared" rgroup.long 0x14++0x03 line.long 0x00 "CHCTRL1,ARH Channel Control Register" bitfld.long 0x00 31. " BYPASS ,BYPASS mode" "No bypass,Bypass" bitfld.long 0x00 30. " FATEIN ,FATAL interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TXCFG ,A-Shell configuration" "Disabled,Enabled" bitfld.long 0x00 25. " RSTRTA ,A-Shell restart" "Normal,Restart" newline bitfld.long 0x00 24. " INITRH ,Remote handler initialization" "No initialization,Initialization" bitfld.long 0x00 21. " PLLGOOD ,APIX PHY PLL lock status" "Unlocked,Locked" bitfld.long 0x00 20. " UPHSK ,Upstream handshake" "Not performed,Performed" bitfld.long 0x00 19. " DNHSK ,Downstream handshake" "Not performed,Performed" newline bitfld.long 0x00 18. " FATAL ,Fatal from A-Shell" "Not occurred,Occurred" bitfld.long 0x00 17. " UPRDY ,Upstream serial channel operation" "Not operational,Operational" bitfld.long 0x00 16. " CONNECTED ,Connection established" "Not connected,Connected" bitfld.long 0x00 15. " UPVALID ,Upstream data valid status" "Not valid,Valid" newline bitfld.long 0x00 14. " DNVALID ,Downstream data valid status" "Not valid,Valid" bitfld.long 0x00 13. " FATIRQ ,Fatal interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 12. " CRCERR ,CRC error status in upstream data" "No error,Error" bitfld.long 0x00 11. " CRCTOUT ,CRC timeout status in upstream data" "Not occurred,Occurred" newline bitfld.long 0x00 10. " PERROR ,Protocol error status" "No error,Error" bitfld.long 0x00 9. " READY ,A-Shell ready status" "Not ready,Ready" bitfld.long 0x00 8. " REMOTERST ,Remote A-Shell restart status" "Not occurred,Occurred" bitfld.long 0x00 7. " UPVALIDCL ,Clear upstream data valid status" "No effect,Cleared" newline bitfld.long 0x00 6. " DNVALIDST ,Set downstream data valid status" "No effect,Set" bitfld.long 0x00 5. " FATIRQCL ,Clear fatal IRQ interrupt status" "No effect,Cleared" bitfld.long 0x00 4. " CRCERRCL ,Clear CRC error in upstream data status" "No effect,Cleared" bitfld.long 0x00 3. " CRCTOUTCL ,Clear CRC timeout in upstream data status" "No effect,Cleared" newline bitfld.long 0x00 2. " PERRORCL ,Clear protocol error status" "No error,Error" bitfld.long 0x00 1. " READYCL ,Clear A-Shell ready status" "No effect,Cleared" bitfld.long 0x00 0. " REMOTERSTCL ,Clear remote A-Shell restart status" "No effect,Cleared" endif rgroup.long 0x08++0x03 line.long 0x00 "CHSTAT0,ARH Channel Status Register" hexmask.long.byte 0x00 24.--31. 1. " UPCRC ,CRC errors" hexmask.long.byte 0x00 8.--15. 1. " UPSYNC ,Synchronization lost" hexmask.long.byte 0x00 0.--7. 1. " PLLBAD ,PLL synchronization lost" rgroup.long 0x18++0x03 line.long 0x00 "CHSTAT1,ARH Channel Status Register" hexmask.long.byte 0x00 24.--31. 1. " UPCRC ,CRC errors" hexmask.long.byte 0x00 8.--15. 1. " UPSYNC ,Synchronization lost" hexmask.long.byte 0x00 0.--7. 1. " PLLBAD ,PLL synchronization lost" group.long 0x0C++0x03 line.long 0x00 "CHWDGCTL0,ARH Channel Watchdog Control Register" bitfld.long 0x00 31. " WDTXIEN ,TX watchdog timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " WDRXIEN ,RX watchdog timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " WTTX ,TX watchdog timer select" "WDTXIRQ0,WDTXIRQ1,WDTXIRQ2,WDTXIRQ3" bitfld.long 0x00 24.--25. " WTRX ,RX watchdog timer select" "WDRXIRQ0,WDRXIRQ1,WDRXIRQ2,WDRXIRQ3" newline rbitfld.long 0x00 15. " WDTXIRQ3 ,TX watchdog interrupt 3" "No interrupt,Interrupt" rbitfld.long 0x00 14. " WDTXIRQ2 ,TX watchdog interrupt 2" "No interrupt,Interrupt" rbitfld.long 0x00 13. " WDTXIRQ1 ,TX watchdog interrupt 1" "No interrupt,Interrupt" rbitfld.long 0x00 12. " WDTXIRQ0 ,TX watchdog interrupt 0" "No interrupt,Interrupt" newline rbitfld.long 0x00 11. " WDRXIRQ3 ,RX watchdog interrupt 3" "No interrupt,Interrupt" rbitfld.long 0x00 10. " WDRXIRQ2 ,RX watchdog interrupt 2" "No interrupt,Interrupt" rbitfld.long 0x00 9. " WDRXIRQ1 ,RX watchdog interrupt 1" "No interrupt,Interrupt" rbitfld.long 0x00 8. " WDRXIRQ0 ,RX watchdog interrupt 0" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " WDTXIRQ3CL ,Clear WDTXIRQ3" "No effect,Cleared" bitfld.long 0x00 6. " WDTXIRQ2CL ,Clear WDTXIRQ2" "No effect,Cleared" bitfld.long 0x00 5. " WDTXIRQ1CL ,Clear WDTXIRQ1" "No effect,Cleared" bitfld.long 0x00 4. " WDTXIRQ0CL ,Clear WDTXIRQ0" "No effect,Cleared" newline bitfld.long 0x00 3. " WDRXIRQ3CL ,Clear WDRXIRQ3" "No effect,Cleared" bitfld.long 0x00 2. " WDRXIRQ2CL ,Clear WDRXIRQ2" "No effect,Cleared" bitfld.long 0x00 1. " WDRXIRQ1CL ,Clear WDRXIRQ1" "No effect,Cleared" bitfld.long 0x00 0. " WDRXIRQ0CL ,Clear WDRXIRQ0" "No effect,Cleared" group.long 0x1C++0x03 line.long 0x00 "CHWDGCTL1,ARH Channel Watchdog Control Register" bitfld.long 0x00 31. " WDTXIEN ,TX watchdog timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " WDRXIEN ,RX watchdog timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " WTTX ,TX watchdog timer select" "WDTXIRQ0,WDTXIRQ1,WDTXIRQ2,WDTXIRQ3" bitfld.long 0x00 24.--25. " WTRX ,RX watchdog timer select" "WDRXIRQ0,WDRXIRQ1,WDRXIRQ2,WDRXIRQ3" newline rbitfld.long 0x00 15. " WDTXIRQ3 ,TX watchdog interrupt 3" "No interrupt,Interrupt" rbitfld.long 0x00 14. " WDTXIRQ2 ,TX watchdog interrupt 2" "No interrupt,Interrupt" rbitfld.long 0x00 13. " WDTXIRQ1 ,TX watchdog interrupt 1" "No interrupt,Interrupt" rbitfld.long 0x00 12. " WDTXIRQ0 ,TX watchdog interrupt 0" "No interrupt,Interrupt" newline rbitfld.long 0x00 11. " WDRXIRQ3 ,RX watchdog interrupt 3" "No interrupt,Interrupt" rbitfld.long 0x00 10. " WDRXIRQ2 ,RX watchdog interrupt 2" "No interrupt,Interrupt" rbitfld.long 0x00 9. " WDRXIRQ1 ,RX watchdog interrupt 1" "No interrupt,Interrupt" rbitfld.long 0x00 8. " WDRXIRQ0 ,RX watchdog interrupt 0" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " WDTXIRQ3CL ,Clear WDTXIRQ3" "No effect,Cleared" bitfld.long 0x00 6. " WDTXIRQ2CL ,Clear WDTXIRQ2" "No effect,Cleared" bitfld.long 0x00 5. " WDTXIRQ1CL ,Clear WDTXIRQ1" "No effect,Cleared" bitfld.long 0x00 4. " WDTXIRQ0CL ,Clear WDTXIRQ0" "No effect,Cleared" newline bitfld.long 0x00 3. " WDRXIRQ3CL ,Clear WDRXIRQ3" "No effect,Cleared" bitfld.long 0x00 2. " WDRXIRQ2CL ,Clear WDRXIRQ2" "No effect,Cleared" bitfld.long 0x00 1. " WDRXIRQ1CL ,Clear WDRXIRQ1" "No effect,Cleared" bitfld.long 0x00 0. " WDRXIRQ0CL ,Clear WDRXIRQ0" "No effect,Cleared" rgroup.long 0x10++0x03 line.long 0x00 "CHWDGCNT0,ARH Watchdog Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,Free running timer" rgroup.long 0x20++0x03 line.long 0x00 "CHWDGCNT1,ARH Watchdog Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,Free running timer" newline if ((per.l(ad:0xB8030000+0x24)&0x2600)==0x00) group.long 0x24++0x03 line.long 0x00 "TBCTRL0,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x24++0x03 line.long 0x00 "TBCTRL0,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x28)&0x2600)==0x00) group.long 0x28++0x03 line.long 0x00 "TBCTRL1,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x28++0x03 line.long 0x00 "TBCTRL1,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x2C)&0x2600)==0x00) group.long 0x2C++0x03 line.long 0x00 "TBCTRL2,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x2C++0x03 line.long 0x00 "TBCTRL2,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x30)&0x2600)==0x00) group.long 0x30++0x03 line.long 0x00 "TBCTRL3,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x30++0x03 line.long 0x00 "TBCTRL3,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x34)&0x2600)==0x00) group.long 0x34++0x03 line.long 0x00 "TBCTRL4,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x34++0x03 line.long 0x00 "TBCTRL4,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x38)&0x2600)==0x00) group.long 0x38++0x03 line.long 0x00 "TBCTRL5,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x38++0x03 line.long 0x00 "TBCTRL5,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x3C)&0x2600)==0x00) group.long 0x3C++0x03 line.long 0x00 "TBCTRL6,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x3C++0x03 line.long 0x00 "TBCTRL6,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x40)&0x2600)==0x00) group.long 0x40++0x03 line.long 0x00 "TBCTRL7,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x40++0x03 line.long 0x00 "TBCTRL7,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x44)&0x2600)==0x00) group.long 0x44++0x03 line.long 0x00 "TBCTRL8,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x44++0x03 line.long 0x00 "TBCTRL8,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x48)&0x2600)==0x00) group.long 0x48++0x03 line.long 0x00 "TBCTRL9,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x48++0x03 line.long 0x00 "TBCTRL9,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x4C)&0x2600)==0x00) group.long 0x4C++0x03 line.long 0x00 "TBCTRL10,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x4C++0x03 line.long 0x00 "TBCTRL10,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x50)&0x2600)==0x00) group.long 0x50++0x03 line.long 0x00 "TBCTRL11,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x50++0x03 line.long 0x00 "TBCTRL11,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x54)&0x2600)==0x00) group.long 0x54++0x03 line.long 0x00 "TBCTRL12,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x54++0x03 line.long 0x00 "TBCTRL12,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x58)&0x2600)==0x00) group.long 0x58++0x03 line.long 0x00 "TBCTRL13,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x58++0x03 line.long 0x00 "TBCTRL13,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x5C)&0x2600)==0x00) group.long 0x5C++0x03 line.long 0x00 "TBCTRL14,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x5C++0x03 line.long 0x00 "TBCTRL14,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif if ((per.l(ad:0xB8030000+0x60)&0x2600)==0x00) group.long 0x60++0x03 line.long 0x00 "TBCTRL15,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " ACTIVE ,Transaction buffer request active" "Not active,Active" rbitfld.long 0x00 12. " UNLOCKED ,Transaction buffer unlocked" "Locked,Unlocked" newline rbitfld.long 0x00 11. " CANCELED ,Transaction buffer request canceled" "Not canceled,Canceled" rbitfld.long 0x00 10. " WAITING ,Transaction buffer request waiting" "Not waiting,Waiting" rbitfld.long 0x00 9. " PENDING ,Transaction buffer request pending" "Not pending,Pending" rbitfld.long 0x00 8. " TBIRQ ,Transaction buffer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear transaction buffer unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear transaction buffer canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear transaction buffer interrupt" "No effect,Cleared" else rgroup.long 0x60++0x03 line.long 0x00 "TBCTRL15,ARH Transaction Buffer Control Register" bitfld.long 0x00 31. " TBCH ,Transaction buffer channel" "Channel 0,Channel 1" bitfld.long 0x00 30. " TBAINC ,Transaction buffer address increment" "Disabled,Enabled" bitfld.long 0x00 29. " TBACT ,Transaction buffer activated" "TBNO,TBNO/TFDATA" bitfld.long 0x00 28. " TBIMD ,Transaction buffer interrupt mode" "TB idle,TB valid" newline bitfld.long 0x00 17. " TBDEN ,Transaction buffer DMA Enable" "Disabled,Enabled" bitfld.long 0x00 16. " TBIEN ,Transaction Buffer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " ACTIVE ,Transaction Buffer Request Active" "Not active,Active" bitfld.long 0x00 12. " UNLOCKED ,Transaction Buffer Unlocked" "Locked,Unlocked" newline bitfld.long 0x00 11. " CANCELED ,Transaction Buffer Request Canceled" "Not canceled,Canceled" bitfld.long 0x00 10. " WAITING ,Transaction Buffer Request Waiting" "Not waiting,Waiting" bitfld.long 0x00 9. " PENDING ,Transaction Buffer Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " TBIRQ ,Transaction Buffer Interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " UNLOCKEDCL ,Clear Transaction Buffer Unlocked" "No effect,Cleared" bitfld.long 0x00 1. " CANCELEDCL ,Clear Transaction Buffer Canceled" "No effect,Cleared" bitfld.long 0x00 0. " TBIRQCL ,Clear Transaction Buffer Interrupt" "No effect,Cleared" endif newline rgroup.word 0x66++0x01 line.word 0x00 "TBIRQ,ARH Transaction Buffer Interrupt Register" bitfld.word 0x00 15. " TBIRQ[15] ,Transaction buffer 15 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 14. " TBIRQ[14] ,Transaction buffer 14 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 13. " TBIRQ[13] ,Transaction buffer 13 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 12. " TBIRQ[12] ,Transaction buffer 12 interrupt" "No interrupt,Interrupt" newline bitfld.word 0x00 11. " TBIRQ[11] ,Transaction buffer 11 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 10. " TBIRQ[10] ,Transaction buffer 10 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 9. " TBIRQ[9] ,Transaction buffer 9 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 8. " TBIRQ[8] ,Transaction buffer 8 interrupt" "No interrupt,Interrupt" newline bitfld.word 0x00 7. " TBIRQ[7] ,Transaction buffer 7 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 6. " TBIRQ[6] ,Transaction buffer 6 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 5. " TBIRQ[5] ,Transaction buffer 5 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 4. " TBIRQ[4] ,Transaction buffer 4 interrupt" "No interrupt,Interrupt" newline bitfld.word 0x00 3. " TBIRQ[3] ,Transaction buffer 3 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 2. " TBIRQ[2] ,Transaction buffer 2 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 1. " TBIRQ[1] ,Transaction buffer 1 interrupt" "No interrupt,Interrupt" bitfld.word 0x00 0. " TBIRQ[0] ,Transaction buffer 0 interrupt" "No interrupt,Interrupt" rgroup.byte 0x65++0x00 line.byte 0x00 "TBIDX0,ARH Transaction Buffer Index Register" bitfld.byte 0x00 0.--4. " TBIDX ,Transaction buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.byte 0x64++0x00 line.byte 0x00 "TBIDX1,ARH Transaction Buffer Index Register" bitfld.byte 0x00 0.--4. " TBIDX ,Transaction buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline if ((per.l(ad:0xB8030000+0x24)&0x2600)==0x00) group.byte 0x6B++0x00 line.byte 0x00 "TFCTRL0,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x6B++0x00 line.byte 0x00 "TFCTRL0,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x28)&0x2600)==0x00) group.byte 0x69++0x00 line.byte 0x00 "TFCTRL1,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x69++0x00 line.byte 0x00 "TFCTRL1,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x2C)&0x2600)==0x00) group.byte 0x6F++0x00 line.byte 0x00 "TFCTRL2,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x6F++0x00 line.byte 0x00 "TFCTRL2,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x30)&0x2600)==0x00) group.byte 0x6D++0x00 line.byte 0x00 "TFCTRL3,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x6D++0x00 line.byte 0x00 "TFCTRL3,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x34)&0x2600)==0x00) group.byte 0x73++0x00 line.byte 0x00 "TFCTRL4,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x73++0x00 line.byte 0x00 "TFCTRL4,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x38)&0x2600)==0x00) group.byte 0x71++0x00 line.byte 0x00 "TFCTRL5,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x71++0x00 line.byte 0x00 "TFCTRL5,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x3C)&0x2600)==0x00) group.byte 0x77++0x00 line.byte 0x00 "TFCTRL6,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x77++0x00 line.byte 0x00 "TFCTRL6,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x40)&0x2600)==0x00) group.byte 0x75++0x00 line.byte 0x00 "TFCTRL7,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x75++0x00 line.byte 0x00 "TFCTRL7,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x44)&0x2600)==0x00) group.byte 0x7B++0x00 line.byte 0x00 "TFCTRL8,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x7B++0x00 line.byte 0x00 "TFCTRL8,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x48)&0x2600)==0x00) group.byte 0x79++0x00 line.byte 0x00 "TFCTRL9,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x79++0x00 line.byte 0x00 "TFCTRL9,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x4C)&0x2600)==0x00) group.byte 0x7F++0x00 line.byte 0x00 "TFCTRL10,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x7F++0x00 line.byte 0x00 "TFCTRL10,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x50)&0x2600)==0x00) group.byte 0x7D++0x00 line.byte 0x00 "TFCTRL11,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x7D++0x00 line.byte 0x00 "TFCTRL11,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x54)&0x2600)==0x00) group.byte 0x83++0x00 line.byte 0x00 "TFCTRL12,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x83++0x00 line.byte 0x00 "TFCTRL12,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x58)&0x2600)==0x00) group.byte 0x81++0x00 line.byte 0x00 "TFCTRL13,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x81++0x00 line.byte 0x00 "TFCTRL13,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x5C)&0x2600)==0x00) group.byte 0x87++0x00 line.byte 0x00 "TFCTRL14,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x87++0x00 line.byte 0x00 "TFCTRL14,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x60)&0x2600)==0x00) group.byte 0x85++0x00 line.byte 0x00 "TFCTRL15,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" rbitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" else rgroup.byte 0x85++0x00 line.byte 0x00 "TFCTRL15,ARH Transaction Frame Control Register" bitfld.byte 0x00 7. " TFDASWP ,Transaction frame data swap" "Not swapped,Swapped" bitfld.byte 0x00 6. " TFAINV ,Transaction frame address inversion" "Not inverted,Inverted" bitfld.byte 0x00 4. " ERROR ,Remote handler RX error" "No error,Error" bitfld.byte 0x00 2.--3. " SZ ,Size" "Byte,Half word,Word," bitfld.byte 0x00 1. " OAEN ,Offset address enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RW ,Read or write" "Read,Write" endif if ((per.l(ad:0xB8030000+0x24)&0x2600)==0x00) group.byte 0x6A++0x00 line.byte 0x00 "TFIDX0,ARH Transaction Frame Index Register" else rgroup.byte 0x6A++0x00 line.byte 0x00 "TFIDX0,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x28)&0x2600)==0x00) group.byte 0x68++0x00 line.byte 0x00 "TFIDX1,ARH Transaction Frame Index Register" else rgroup.byte 0x68++0x00 line.byte 0x00 "TFIDX1,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x2C)&0x2600)==0x00) group.byte 0x6E++0x00 line.byte 0x00 "TFIDX2,ARH Transaction Frame Index Register" else rgroup.byte 0x6E++0x00 line.byte 0x00 "TFIDX2,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x30)&0x2600)==0x00) group.byte 0x6C++0x00 line.byte 0x00 "TFIDX3,ARH Transaction Frame Index Register" else rgroup.byte 0x6C++0x00 line.byte 0x00 "TFIDX3,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x34)&0x2600)==0x00) group.byte 0x73++0x00 line.byte 0x00 "TFIDX4,ARH Transaction Frame Index Register" else rgroup.byte 0x73++0x00 line.byte 0x00 "TFIDX4,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x38)&0x2600)==0x00) group.byte 0x70++0x00 line.byte 0x00 "TFIDX5,ARH Transaction Frame Index Register" else rgroup.byte 0x70++0x00 line.byte 0x00 "TFIDX5,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x3C)&0x2600)==0x00) group.byte 0x76++0x00 line.byte 0x00 "TFIDX6,ARH Transaction Frame Index Register" else rgroup.byte 0x76++0x00 line.byte 0x00 "TFIDX6,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x40)&0x2600)==0x00) group.byte 0x74++0x00 line.byte 0x00 "TFIDX7,ARH Transaction Frame Index Register" else rgroup.byte 0x74++0x00 line.byte 0x00 "TFIDX7,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x44)&0x2600)==0x00) group.byte 0x7A++0x00 line.byte 0x00 "TFIDX8,ARH Transaction Frame Index Register" else rgroup.byte 0x7A++0x00 line.byte 0x00 "TFIDX8,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x48)&0x2600)==0x00) group.byte 0x78++0x00 line.byte 0x00 "TFIDX9,ARH Transaction Frame Index Register" else rgroup.byte 0x78++0x00 line.byte 0x00 "TFIDX9,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x4C)&0x2600)==0x00) group.byte 0x7E++0x00 line.byte 0x00 "TFIDX10,ARH Transaction Frame Index Register" else rgroup.byte 0x7E++0x00 line.byte 0x00 "TFIDX10,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x50)&0x2600)==0x00) group.byte 0x7C++0x00 line.byte 0x00 "TFIDX11,ARH Transaction Frame Index Register" else rgroup.byte 0x7C++0x00 line.byte 0x00 "TFIDX11,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x54)&0x2600)==0x00) group.byte 0x82++0x00 line.byte 0x00 "TFIDX12,ARH Transaction Frame Index Register" else rgroup.byte 0x82++0x00 line.byte 0x00 "TFIDX12,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x58)&0x2600)==0x00) group.byte 0x80++0x00 line.byte 0x00 "TFIDX13,ARH Transaction Frame Index Register" else rgroup.byte 0x80++0x00 line.byte 0x00 "TFIDX13,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x5C)&0x2600)==0x00) group.byte 0x86++0x00 line.byte 0x00 "TFIDX14,ARH Transaction Frame Index Register" else rgroup.byte 0x86++0x00 line.byte 0x00 "TFIDX14,ARH Transaction Frame Index Register" endif if ((per.l(ad:0xB8030000+0x60)&0x2600)==0x00) group.byte 0x84++0x00 line.byte 0x00 "TFIDX15,ARH Transaction Frame Index Register" else rgroup.byte 0x84++0x00 line.byte 0x00 "TFIDX15,ARH Transaction Frame Index Register" endif newline if ((per.l(ad:0xB8030000+0x24)&0x2600)==0x00) group.long 0x88++0x03 line.long 0x00 "TFADDR0,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0x88++0x03 line.long 0x00 "TFADDR0,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x28)&0x2600)==0x00) group.long 0x8C++0x03 line.long 0x00 "TFADDR1,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0x8C++0x03 line.long 0x00 "TFADDR1,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x2C)&0x2600)==0x00) group.long 0x90++0x03 line.long 0x00 "TFADDR2,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0x90++0x03 line.long 0x00 "TFADDR2,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x30)&0x2600)==0x00) group.long 0x94++0x03 line.long 0x00 "TFADDR3,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0x94++0x03 line.long 0x00 "TFADDR3,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x34)&0x2600)==0x00) group.long 0x98++0x03 line.long 0x00 "TFADDR4,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0x98++0x03 line.long 0x00 "TFADDR4,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x38)&0x2600)==0x00) group.long 0x9C++0x03 line.long 0x00 "TFADDR5,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0x9C++0x03 line.long 0x00 "TFADDR5,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x3C)&0x2600)==0x00) group.long 0xA0++0x03 line.long 0x00 "TFADDR6,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xA0++0x03 line.long 0x00 "TFADDR6,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x40)&0x2600)==0x00) group.long 0xA4++0x03 line.long 0x00 "TFADDR7,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xA4++0x03 line.long 0x00 "TFADDR7,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x44)&0x2600)==0x00) group.long 0xA8++0x03 line.long 0x00 "TFADDR8,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xA8++0x03 line.long 0x00 "TFADDR8,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x48)&0x2600)==0x00) group.long 0xAC++0x03 line.long 0x00 "TFADDR9,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xAC++0x03 line.long 0x00 "TFADDR9,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x4C)&0x2600)==0x00) group.long 0xB0++0x03 line.long 0x00 "TFADDR10,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xB0++0x03 line.long 0x00 "TFADDR10,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x50)&0x2600)==0x00) group.long 0xB4++0x03 line.long 0x00 "TFADDR11,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xB4++0x03 line.long 0x00 "TFADDR11,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x54)&0x2600)==0x00) group.long 0xB8++0x03 line.long 0x00 "TFADDR12,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xB8++0x03 line.long 0x00 "TFADDR12,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x58)&0x2600)==0x00) group.long 0xBC++0x03 line.long 0x00 "TFADDR13,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xBC++0x03 line.long 0x00 "TFADDR13,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x5C)&0x2600)==0x00) group.long 0xC0++0x03 line.long 0x00 "TFADDR14,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xC0++0x03 line.long 0x00 "TFADDR14,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x60)&0x2600)==0x00) group.long 0xC4++0x03 line.long 0x00 "TFADDR15,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" else rgroup.long 0xC4++0x03 line.long 0x00 "TFADDR15,ARH Transaction Frame Address Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Transaction frame address" endif if ((per.l(ad:0xB8030000+0x24)&0x2600)==0x00) group.long 0xC8++0x03 line.long 0x00 "TFDATA0,ARH Transaction Frame Data Register" else rgroup.long 0xC8++0x03 line.long 0x00 "TFDATA0,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x28)&0x2600)==0x00) group.long 0xCC++0x03 line.long 0x00 "TFDATA1,ARH Transaction Frame Data Register" else rgroup.long 0xCC++0x03 line.long 0x00 "TFDATA1,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x2C)&0x2600)==0x00) group.long 0xD0++0x03 line.long 0x00 "TFDATA2,ARH Transaction Frame Data Register" else rgroup.long 0xD0++0x03 line.long 0x00 "TFDATA2,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x30)&0x2600)==0x00) group.long 0xD4++0x03 line.long 0x00 "TFDATA3,ARH Transaction Frame Data Register" else rgroup.long 0xD4++0x03 line.long 0x00 "TFDATA3,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x34)&0x2600)==0x00) group.long 0xD8++0x03 line.long 0x00 "TFDATA4,ARH Transaction Frame Data Register" else rgroup.long 0xD8++0x03 line.long 0x00 "TFDATA4,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x38)&0x2600)==0x00) group.long 0xDC++0x03 line.long 0x00 "TFDATA5,ARH Transaction Frame Data Register" else rgroup.long 0xDC++0x03 line.long 0x00 "TFDATA5,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x3C)&0x2600)==0x00) group.long 0xE0++0x03 line.long 0x00 "TFDATA6,ARH Transaction Frame Data Register" else rgroup.long 0xE0++0x03 line.long 0x00 "TFDATA6,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x40)&0x2600)==0x00) group.long 0xE4++0x03 line.long 0x00 "TFDATA7,ARH Transaction Frame Data Register" else rgroup.long 0xE4++0x03 line.long 0x00 "TFDATA7,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x44)&0x2600)==0x00) group.long 0xE8++0x03 line.long 0x00 "TFDATA8,ARH Transaction Frame Data Register" else rgroup.long 0xE8++0x03 line.long 0x00 "TFDATA8,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x48)&0x2600)==0x00) group.long 0xEC++0x03 line.long 0x00 "TFDATA9,ARH Transaction Frame Data Register" else rgroup.long 0xEC++0x03 line.long 0x00 "TFDATA9,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x4C)&0x2600)==0x00) group.long 0xF0++0x03 line.long 0x00 "TFDATA10,ARH Transaction Frame Data Register" else rgroup.long 0xF0++0x03 line.long 0x00 "TFDATA10,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x50)&0x2600)==0x00) group.long 0xF4++0x03 line.long 0x00 "TFDATA11,ARH Transaction Frame Data Register" else rgroup.long 0xF4++0x03 line.long 0x00 "TFDATA11,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x54)&0x2600)==0x00) group.long 0xF8++0x03 line.long 0x00 "TFDATA12,ARH Transaction Frame Data Register" else rgroup.long 0xF8++0x03 line.long 0x00 "TFDATA12,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x58)&0x2600)==0x00) group.long 0xFC++0x03 line.long 0x00 "TFDATA13,ARH Transaction Frame Data Register" else rgroup.long 0xFC++0x03 line.long 0x00 "TFDATA13,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x5C)&0x2600)==0x00) group.long 0x100++0x03 line.long 0x00 "TFDATA14,ARH Transaction Frame Data Register" else rgroup.long 0x100++0x03 line.long 0x00 "TFDATA14,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000+0x60)&0x2600)==0x00) group.long 0x104++0x03 line.long 0x00 "TFDATA15,ARH Transaction Frame Data Register" else rgroup.long 0x104++0x03 line.long 0x00 "TFDATA15,ARH Transaction Frame Data Register" endif if ((per.l(ad:0xB8030000)&0x01)==0x00) group.long 0x108++0x03 line.long 0x00 "EVCTRL,ARH Event Control Register" bitfld.long 0x00 31. " MODE ,FIFO mode" "Level,Ring" bitfld.long 0x00 30. " FRST ,FIFO reset" "No reset,Reset" hexmask.long.byte 0x00 8.--15. 1. " STATUS ,FIFO fill status" hexmask.long.byte 0x00 0.--7. 1. " LEVEL ,FIFO interrupt level" else rgroup.long 0x108++0x03 line.long 0x00 "EVCTRL,ARH Event Control Register" bitfld.long 0x00 31. " MODE ,FIFO mode" "Level,Ring" bitfld.long 0x00 30. " FRST ,FIFO reset" "No reset,Reset" hexmask.long.byte 0x00 8.--15. 1. " STATUS ,FIFO fill status" hexmask.long.byte 0x00 0.--7. 1. " LEVEL ,FIFO interrupt level" endif group.long 0x10C++0x03 line.long 0x00 "EVIRQC,ARH Event Interrupt Control Register" bitfld.long 0x00 31. " LVIEN ,Level interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " OFLIEN ,Event buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " EVIEN ,Event buffer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " LVIRQ ,Level irq" "No interrupt,Interrupt" newline rbitfld.long 0x00 22. " OFLIRQ ,Overflow IRQ" "No interrupt,Interrupt" rbitfld.long 0x00 21. " EVIRQ ,Event IRQ" "No interrupt,Interrupt" bitfld.long 0x00 15. " LVIRQCL ,Clear level IRQ" "No effect,Cleared" bitfld.long 0x00 14. " OFLIRQCL ,Clear event buffer overflow IRQ" "No effect,Cleared" newline bitfld.long 0x00 13. " EVIRQCL ,Clear event buffer Event IRQ" "No effect,Cleared" hgroup.long 0x110++0x03 hide.long 0x00 "EVBUF0,ARH Event Buffer Register" in group.long 0x114++0x03 line.long 0x00 "EVBUF1,ARH Event Buffer Register" newline if ((per.l(ad:0xB8030000+0x04)&0x4000000)==0x4000000) group.long 0x118++0x03 line.long 0x00 "APCFG00,ARH APIX Configuration Register" bitfld.long 0x00 31. " ENPLL ,PHY PLL enable" "Disabled,Enabled" bitfld.long 0x00 30. " OFFSETCOMP ,PHY offset compensation enable" "Disabled,Enabled" bitfld.long 0x00 29. " ENDOWNSTREAM ,PHY downstream enable" "Disabled,Enabled" bitfld.long 0x00 28. " ENUPSTREAM ,PHY upstream enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CPOCFILTER ,PHY charge pump offset correction filter enable" "Disabled,Enabled" bitfld.long 0x00 25. " DISABLECPOC ,PHY charge pump offset correction amplifier disable" "No,Yes" bitfld.long 0x00 24. " TXDEEMPH4NS ,PHY de-emphasis signal control" "2ns,4ns/2ns" bitfld.long 0x00 22.--23. " TXBWMODE ,PHY TX mode select" "125 Mbit/s,250 Mbit/s,500 Mbit/s,1000 Mbit/s" newline bitfld.long 0x00 21. " PXINCLKACTIVEEDGE ,A-Shell active clock edge configuration" "Falling,Rising" bitfld.long 0x00 20. " PXINJUMBLEEN ,A-Shell cyclic pixel data inversion configuration" "Disabled,Enabled" bitfld.long 0x00 18.--19. " PXINCTRLPIGGYBACK ,A-Shell pixel control data transmission configuration" "Never,,Even pixels,All pixels" bitfld.long 0x00 16.--17. " PXDATAWIDTH ,A-Shell pixel data width configuration" "10 bits,12 bits,18 bits,24 bits" newline bitfld.long 0x00 13.--14. " RXUPBWMODE ,PHY RX data receive rate" "62.50 MBit/s,41.67 MBit/s,20.83 MBit/s,31.25 MBit/s" bitfld.long 0x00 12. " UPLENIENTWINDOW ,A-Shell synchronization error tolerance configuration" "Disabled,Enabled" bitfld.long 0x00 8.--11. " RXUPSMPOFST ,PHY RX Bit alignment sampling point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " JUMBLERMASKEN ,A-Shell pixel data mask enable configuration" "Disabled,Enabled" newline bitfld.long 0x00 6. " SBUPSKIPSKIP ,A-Shell resynchronization in upstream channel configuration" "Enabled,Disabled" bitfld.long 0x00 5. " SBUPRESTARTONERR ,A-Shell restart on error in upstream channel configuration" "Disabled,Enabled" bitfld.long 0x00 4. " BOOTSUPPORTDIS ,A-Shell boot support disable configuration" "Rising edge,High level" bitfld.long 0x00 3. " TRACEFEEDEN ,A-Shell trace feed enable configuration" "Enabled,Disabled" newline bitfld.long 0x00 2. " CEB6DIS ,A-Shell consecutive 6 bits equivalence check configuration" "No,Yes" bitfld.long 0x00 1. " CEB4DIS ,A-Shell consecutive 4 bits equivalence check configuration" "No,Yes" bitfld.long 0x00 0. " IGNOREPLLGOOD ,PHY PLLGOOD output ignore configuration" "Ignored,Not ignored" else rgroup.long 0x118++0x03 line.long 0x00 "APCFG00,ARH APIX Configuration Register" bitfld.long 0x00 31. " ENPLL ,PHY PLL enable" "Disabled,Enabled" bitfld.long 0x00 30. " OFFSETCOMP ,PHY offset compensation enable" "Disabled,Enabled" bitfld.long 0x00 29. " ENDOWNSTREAM ,PHY downstream enable" "Disabled,Enabled" bitfld.long 0x00 28. " ENUPSTREAM ,PHY upstream enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CPOCFILTER ,PHY charge pump offset correction filter enable" "Disabled,Enabled" bitfld.long 0x00 25. " DISABLECPOC ,PHY charge pump offset correction amplifier disable" "No,Yes" bitfld.long 0x00 24. " TXDEEMPH4NS ,PHY de-emphasis signal control" "2ns,4ns/2ns" bitfld.long 0x00 22.--23. " TXBWMODE ,PHY TX mode select" "125 Mbit/s,250 Mbit/s,500 Mbit/s,1000 Mbit/s" newline bitfld.long 0x00 21. " PXINCLKACTIVEEDGE ,A-Shell active clock edge configuration" "Falling,Rising" bitfld.long 0x00 20. " PXINJUMBLEEN ,A-Shell cyclic pixel data inversion configuration" "Disabled,Enabled" bitfld.long 0x00 18.--19. " PXINCTRLPIGGYBACK ,A-Shell pixel control data transmission configuration" "Never,,Even pixels,All pixels" bitfld.long 0x00 16.--17. " PXDATAWIDTH ,A-Shell pixel data width configuration" "10 bits,12 bits,18 bits,24 bits" newline bitfld.long 0x00 13.--14. " RXUPBWMODE ,PHY RX data receive rate" "62.50 MBit/s,41.67 MBit/s,20.83 MBit/s,31.25 MBit/s" bitfld.long 0x00 12. " UPLENIENTWINDOW ,A-Shell synchronization error tolerance configuration" "Disabled,Enabled" bitfld.long 0x00 8.--11. " RXUPSMPOFST ,PHY RX bit alignment sampling point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " JUMBLERMASKEN ,A-Shell pixel data mask enable configuration" "Disabled,Enabled" newline bitfld.long 0x00 6. " SBUPSKIPSKIP ,A-Shell resynchronization in upstream channel configuration" "Enabled,Disabled" bitfld.long 0x00 5. " SBUPRESTARTONERR ,A-Shell restart on error in upstream channel configuration" "Disabled,Enabled" bitfld.long 0x00 4. " BOOTSUPPORTDIS ,A-Shell boot support disable configuration" "Rising edge,High level" bitfld.long 0x00 3. " TRACEFEEDEN ,A-Shell trace feed enable configuration" "Enabled,Disabled" newline bitfld.long 0x00 2. " CEB6DIS ,A-Shell consecutive 6 bits equivalence check configuration" "No,Yes" bitfld.long 0x00 1. " CEB4DIS ,A-Shell consecutive 4 bits equivalence check configuration" "No,Yes" bitfld.long 0x00 0. " IGNOREPLLGOOD ,PHY PLLGOOD output ignore configuration" "Ignored,Not ignored" endif if ((per.l(ad:0xB8030000+0x14)&0x4000000)==0x4000000) group.long 0x128++0x03 line.long 0x00 "APCFG10,ARH APIX Configuration Register" bitfld.long 0x00 21. " PXINCLKACTIVEEDGE ,A-Shell active clock edge configuration" "Falling,Rising" bitfld.long 0x00 20. " PXINJUMBLEEN ,A-Shell cyclic pixel data inversion configuration" "Disabled,Enabled" bitfld.long 0x00 18.--19. " PXINCTRLPIGGYBACK ,A-Shell pixel control data transmission configuration" "Never,,Even pixels,All pixels" bitfld.long 0x00 16.--17. " PXDATAWIDTH ,A-Shell pixel data width configuration" "10 bits,12 bits,18 bits,24 bits" newline bitfld.long 0x00 12. " UPLENIENTWINDOW ,A-Shell synchronization error tolerance configuration" "Disabled,Enabled" bitfld.long 0x00 7. " JUMBLERMASKEN ,A-Shell pixel data mask enable configuration" "Disabled,Enabled" bitfld.long 0x00 6. " SBUPSKIPSKIP ,A-Shell resynchronization in upstream channel configuration" "Enabled,Disabled" bitfld.long 0x00 5. " SBUPRESTARTONERR ,A-Shell restart on error in upstream channel configuration" "Disabled,Enabled" newline bitfld.long 0x00 4. " BOOTSUPPORTDIS ,A-Shell boot support disable configuration" "Rising edge,High level" bitfld.long 0x00 3. " TRACEFEEDEN ,A-Shell trace feed enable configuration" "Enabled,Disabled" bitfld.long 0x00 2. " CEB6DIS ,A-Shell consecutive 6 bits equivalence check configuration" "No,Yes" bitfld.long 0x00 1. " CEB4DIS ,A-Shell consecutive 4 bits equivalence check configuration" "No,Yes" newline bitfld.long 0x00 0. " IGNOREPLLGOOD ,PHY PLLGOOD output ignore configuration" "Ignored,Not ignored" else rgroup.long 0x128++0x03 line.long 0x00 "APCFG10,ARH APIX Configuration Register" bitfld.long 0x00 21. " PXINCLKACTIVEEDGE ,A-Shell active clock edge configuration" "Falling,Rising" bitfld.long 0x00 20. " PXINJUMBLEEN ,A-Shell cyclic pixel data inversion configuration" "Disabled,Enabled" bitfld.long 0x00 18.--19. " PXINCTRLPIGGYBACK ,A-Shell pixel control data transmission configuration" "Never,,Even pixels,All pixels" bitfld.long 0x00 16.--17. " PXDATAWIDTH ,A-Shell pixel data width configuration" "10 bits,12 bits,18 bits,24 bits" newline bitfld.long 0x00 12. " UPLENIENTWINDOW ,A-Shell synchronization error tolerance configuration" "Disabled,Enabled" bitfld.long 0x00 7. " JUMBLERMASKEN ,A-Shell pixel data mask enable configuration" "Disabled,Enabled" bitfld.long 0x00 6. " SBUPSKIPSKIP ,A-Shell resynchronization in upstream channel configuration" "Enabled,Disabled" bitfld.long 0x00 5. " SBUPRESTARTONERR ,A-Shell restart on error in upstream channel configuration" "Disabled,Enabled" newline bitfld.long 0x00 4. " BOOTSUPPORTDIS ,A-Shell boot support disable configuration" "Rising edge,High level" bitfld.long 0x00 3. " TRACEFEEDEN ,A-Shell trace feed enable configuration" "Enabled,Disabled" bitfld.long 0x00 2. " CEB6DIS ,A-Shell consecutive 6 bits equivalence check configuration" "No,Yes" bitfld.long 0x00 1. " CEB4DIS ,A-Shell consecutive 4 bits equivalence check configuration" "No,Yes" newline bitfld.long 0x00 0. " IGNOREPLLGOOD ,PHY PLLGOOD output ignore configuration" "Ignored,Not ignored" endif newline if ((per.l(ad:0xB8030000+0x04)&0x4000000)==0x4000000) group.long 0x11C++0x03 line.long 0x00 "APCFG01,ARH APIX Configuration Register" bitfld.long 0x00 31. " DDOWNEN ,A-Shell downstream data path configuration" "Pixel stream,Data" bitfld.long 0x00 30. " SBDOWNSMODE ,PHY downstream sideband data relation to core clock" "Asynchronous,Synchronous" bitfld.long 0x00 29. " CLKCORE1EN ,PHY core clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " CLKCORE2EN ,A-Shell1 core clock enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CLKCORE3EN ,A-Shell2 core clock enable" "Disabled,Enabled" bitfld.long 0x00 26. " MASKPLLGOOD ,PLLGOOD mask bit for APIX PHY" "No effect,Masked" bitfld.long 0x00 20.--23. " CRGPMPCTRL ,PHY charge pump current control" "5uA,10uA,15uA,20uA,25uA,30uA,35uA,40uA,45uA,50uA,55uA,60uA,65uA,70uA,75uA,80uA" bitfld.long 0x00 19. " PREDRVIINC ,PHY pre-driver output swing control" "Normal,High swing" newline bitfld.long 0x00 14.--17. " TXNOMSWING ,PHY transmit swing" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Max" bitfld.long 0x00 8.--10. " TXDEEMPH ,PHY transmit de-emphasis level" "Min,1,2,3,4,5,6,Max" hexmask.long.byte 0x00 1.--7. 1. " TRIGCYCLEN ,A-Shell sideband downstream trigger output pulse pattern cycle length configuration" else rgroup.long 0x11C++0x03 line.long 0x00 "APCFG01,ARH APIX Configuration Register" bitfld.long 0x00 31. " DDOWNEN ,A-Shell downstream data path configuration" "Pixel stream,Data" bitfld.long 0x00 30. " SBDOWNSMODE ,PHY downstream sideband data relation to core clock" "Asynchronous,Synchronous" bitfld.long 0x00 29. " CLKCORE1EN ,PHY core clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " CLKCORE2EN ,A-Shell1 core clock enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CLKCORE3EN ,A-Shell2 core clock enable" "Disabled,Enabled" bitfld.long 0x00 26. " MASKPLLGOOD ,PLLGOOD mask bit for APIX PHY" "No effect,Masked" bitfld.long 0x00 20.--23. " CRGPMPCTRL ,PHY charge pump current control" "5uA,10uA,15uA,20uA,25uA,30uA,35uA,40uA,45uA,50uA,55uA,60uA,65uA,70uA,75uA,80uA" bitfld.long 0x00 19. " PREDRVIINC ,PHY pre-driver output swing control" "Normal,High swing" newline bitfld.long 0x00 14.--17. " TXNOMSWING ,PHY transmit swing" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Max" bitfld.long 0x00 8.--10. " TXDEEMPH ,PHY transmit de-emphasis level" "Min,1,2,3,4,5,6,Max" hexmask.long.byte 0x00 1.--7. 1. " TRIGCYCLEN ,A-Shell sideband downstream trigger output pulse pattern cycle length configuration" endif if ((per.l(ad:0xB8030000+0x14)&0x4000000)==0x4000000) group.long 0x12C++0x03 line.long 0x00 "APCFG11,ARH APIX Configuration Register" bitfld.long 0x00 31. " DDOWNEN ,A-Shell downstream data path configuration" "Pixel stream,Data" bitfld.long 0x00 30. " SBDOWNSMODE ,PHY downstream sideband data relation to core clock" "Asynchronous,Synchronous" bitfld.long 0x00 29. " CLKCORE1EN ,PHY core clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " CLKCORE2EN ,A-Shell1 core clock enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CLKCORE3EN ,A-Shell2 core clock enable" "Disabled,Enabled" bitfld.long 0x00 26. " MASKPLLGOOD ,PLLGOOD mask bit for Apix PHY" "No effect,Masked" hexmask.long.byte 0x00 1.--7. 1. " TRIGCYCLEN ,A-Shell sideband downstream trigger output pulse pattern cycle length configuration" else rgroup.long 0x12C++0x03 line.long 0x00 "APCFG11,ARH APIX Configuration Register" bitfld.long 0x00 31. " DDOWNEN ,A-Shell downstream data path configuration" "Pixel stream,Data" bitfld.long 0x00 30. " SBDOWNSMODE ,PHY downstream sideband data relation to core clock" "Asynchronous,Synchronous" bitfld.long 0x00 29. " CLKCORE1EN ,PHY core clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " CLKCORE2EN ,A-Shell1 core clock enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CLKCORE3EN ,A-Shell2 core clock enable" "Disabled,Enabled" bitfld.long 0x00 26. " MASKPLLGOOD ,PLLGOOD mask bit for APIX PHY" "No effect,Masked" hexmask.long.byte 0x00 1.--7. 1. " TRIGCYCLEN ,A-Shell sideband downstream trigger output pulse pattern cycle length configuration" endif newline if ((per.l(ad:0xB8030000+0x04)&0x4000000)==0x4000000) group.long 0x120++0x03 line.long 0x00 "APCFG02,ARH APIX Configuration Register" hexmask.long.byte 0x00 25.--31. 1. " TRIGACTLEN ,A-Shell sideband downstream trigger output active length configuration" hexmask.long.byte 0x00 17.--23. 1. " TRIGOFF ,A-Shell sideband downstream trigger output offset configuration" bitfld.long 0x00 14.--15. " SBUPVALACTLEN ,A-Shell sideband upstream valid output active length configuration" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 7. " PLLMULT ,PHY PLL multiplier" "20 MHz,25 MHz" newline bitfld.long 0x00 6. " OSCFILTER ,PHY oscillator filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " TXINVERT ,PHY TX data invert enable" "Not inverted,Inverted" bitfld.long 0x00 4. " RXINVERT ,PHY RX data invert enable" "Not inverted,Inverted" bitfld.long 0x00 3. " PLLGOODSEL ,PLLGOOD status select" "Reset,Not reset" newline bitfld.long 0x00 0. " SCPREEN ,Sysclk prescalar enable" "Reset,Not reset" else rgroup.long 0x120++0x03 line.long 0x00 "APCFG02,ARH APIX Configuration Register" hexmask.long.byte 0x00 25.--31. 1. " TRIGACTLEN ,A-Shell sideband downstream trigger output active length configuration" hexmask.long.byte 0x00 17.--23. 1. " TRIGOFF ,A-Shell sideband downstream trigger output offset configuration" bitfld.long 0x00 14.--15. " SBUPVALACTLEN ,A-Shell sideband upstream valid output active length configuration" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 7. " PLLMULT ,PHY PLL multiplier" "20 MHz,25 MHz" newline bitfld.long 0x00 6. " OSCFILTER ,PHY oscillator filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " TXINVERT ,PHY TX data invert enable" "Not inverted,Inverted" bitfld.long 0x00 4. " RXINVERT ,PHY RX data invert enable" "Not inverted,Inverted" bitfld.long 0x00 3. " PLLGOODSEL ,PLLGOOD status select" "Reset,Not reset" newline bitfld.long 0x00 0. " SCPREEN ,Sysclk prescalar enable" "Reset,Not reset" endif if ((per.l(ad:0xB8030000+0x14)&0x4000000)==0x4000000) group.long 0x130++0x03 line.long 0x00 "APCFG12,ARH APIX Configuration Register" hexmask.long.byte 0x00 25.--31. 1. " TRIGACTLEN ,A-Shell sideband downstream trigger output active length configuration" hexmask.long.byte 0x00 17.--23. 1. " TRIGOFF ,A-Shell sideband downstream trigger output offset configuration" bitfld.long 0x00 14.--15. " SBUPVALACTLEN ,A-Shell sideband upstream valid output active length configuration" "1 cycle,2 cycles,3 cycles,4 cycles" else rgroup.long 0x130++0x03 line.long 0x00 "APCFG12,ARH APIX Configuration Register" hexmask.long.byte 0x00 25.--31. 1. " TRIGACTLEN ,A-Shell sideband downstream trigger output active length configuration" hexmask.long.byte 0x00 17.--23. 1. " TRIGOFF ,A-Shell sideband downstream trigger output offset configuration" bitfld.long 0x00 14.--15. " SBUPVALACTLEN ,A-Shell sideband upstream valid output active length configuration" "1 cycle,2 cycles,3 cycles,4 cycles" endif newline if ((per.l(ad:0xB8030000+0x04)&0x4000000)==0x4000000) group.long 0x124++0x03 line.long 0x00 "APCFG03,ARH APIX Configuration Register" bitfld.long 0x00 31. " SBDWNCLK ,Functional meaning of sideband downstream trigger" "Request,Strobe" hexmask.long.byte 0x00 24.--30. 1. " SBDWNDACLKCLENL ,Sideband downstream clock cycle time" bitfld.long 0x00 23. " SBUPDWIDTH ,Sideband upstream ports enable" "Data[0],Data[1:0]" bitfld.long 0x00 22. " SBUPDACLK ,Sideband Upstream Data Validation" "Data valid,Data[1]" newline bitfld.long 0x00 21. " SBDWNDWIDTH ,Sideband upstream data validation" "Data[0],Data[1:0]" bitfld.long 0x00 19.--20. " SBDWNDACLK ,Sideband downstream clock generate source" "Disabled,Sideband trigger,Internal counter,Disabled" bitfld.long 0x00 18. " EPHY ,Internal A-Shell to external APIX PHY connection control" "Disabled,Enabled" bitfld.long 0x00 17. " ESHELL ,Internal APIX PHY to external A-Shell connection control" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPIOVERSB ,SPI Over sideband control" "Disabled,Enabled" bitfld.long 0x00 14.--15. " CRCTIMEOUTVAL[2:3] ,CRC timeout value - Multiplier" "1,4,16,128" bitfld.long 0x00 12.--13. " CRCTIMEOUTVAL[0:1] ,CRC timeout value - Base" "2,4,6,10" bitfld.long 0x00 8.--11. " WINDOWSIZE ,Acknowledgment window size" ",1,2,3,4,5,6,7,8,9,10,11,12,?..." newline bitfld.long 0x00 6. " SUPPRESSITA ,Outbound idle transaction control" "Sent,Not sent" bitfld.long 0x00 0.--2. " SBDWNDACLKCLENU , Sideband downstream clock cycle time" "0,1,2,3,4,5,6,7" else rgroup.long 0x124++0x03 line.long 0x00 "APCFG03,ARH APIX Configuration Register" bitfld.long 0x00 31. " SBDWNCLK ,Functional meaning of sideband downstream trigger" "Request,Strobe" hexmask.long.byte 0x00 24.--30. 1. " SBDWNDACLKCLENL ,Sideband downstream clock cycle time" bitfld.long 0x00 23. " SBUPDWIDTH ,Sideband upstream ports enable" "Data[0],Data[1:0]" bitfld.long 0x00 22. " SBUPDACLK ,Sideband upstream data validation" "Data valid,Data[1]" newline bitfld.long 0x00 21. " SBDWNDWIDTH ,Sideband upstream data validation" "Data[0],Data[1:0]" bitfld.long 0x00 19.--20. " SBDWNDACLK ,Sideband downstream clock generate source" "Disabled,Sideband trigger,Internal counter,Disabled" bitfld.long 0x00 18. " EPHY ,Internal A-Shell to external APIX PHY connection control" "Disabled,Enabled" bitfld.long 0x00 17. " ESHELL ,Internal APIX PHY to external A-Shell connection control" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPIOVERSB ,SPI over sideband control" "Disabled,Enabled" bitfld.long 0x00 14.--15. " CRCTIMEOUTVAL[2:3] ,CRC timeout value - Multiplier" "1,4,16,128" bitfld.long 0x00 12.--13. " CRCTIMEOUTVAL[0:1] ,CRC timeout value - Base" "2,4,6,10" bitfld.long 0x00 8.--11. " WINDOWSIZE ,Acknowledgment window size" ",1,2,3,4,5,6,7,8,9,10,11,12,?..." newline bitfld.long 0x00 6. " SUPPRESSITA ,Outbound idle transaction control" "Sent,Not sent" bitfld.long 0x00 0.--2. " SBDWNDACLKCLENU , Sideband downstream clock cycle time" "0,1,2,3,4,5,6,7" endif if ((per.l(ad:0xB8030000+0x14)&0x4000000)==0x4000000) group.long 0x134++0x03 line.long 0x00 "APCFG13,ARH APIX Configuration Register" bitfld.long 0x00 31. " SBDWNCLK ,Functional meaning of sideband downstream trigger" "Request,Strobe" hexmask.long.byte 0x00 24.--30. 1. " SBDWNDACLKCLENL ,Sideband downstream clock cycle time" bitfld.long 0x00 23. " SBUPDWIDTH ,Sideband upstream ports enable" "Data[0],Data[1:0]" bitfld.long 0x00 22. " SBUPDACLK ,Sideband upstream data validation" "Data valid,Data[1]" newline bitfld.long 0x00 21. " SBDWNDWIDTH ,Sideband upstream data validation" "Data[0],Data[1:0]" bitfld.long 0x00 19.--20. " SBDWNDACLK ,Sideband downstream clock generate source" "Disabled,Sideband trigger,Internal counter,Disabled" bitfld.long 0x00 18. " EPHY ,Internal A-Shell to external APIX PHY connection control" "Disabled,Enabled" bitfld.long 0x00 17. " ESHELL ,Internal APIX PHY to external A-Shell connection control" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPIOVERSB ,SPI over sideband control" "Disabled,Enabled" bitfld.long 0x00 14.--15. " CRCTIMEOUTVAL[2:3] ,CRC timeout value - multiplier" "1,4,16,128" bitfld.long 0x00 12.--13. " CRCTIMEOUTVAL[0:1] ,CRC timeout value - Base" "2,4,6,10" bitfld.long 0x00 8.--11. " WINDOWSIZE ,Acknowledgment window size" ",1,2,3,4,5,6,7,8,9,10,11,12,?..." newline bitfld.long 0x00 6. " SUPPRESSITA ,Outbound idle transaction control" "Sent,Not sent" bitfld.long 0x00 0.--2. " SBDWNDACLKCLENU , Sideband downstream clock cycle time" "0,1,2,3,4,5,6,7" else rgroup.long 0x134++0x03 line.long 0x00 "APCFG13,ARH APIX Configuration Register" bitfld.long 0x00 31. " SBDWNCLK ,Functional meaning of sideband downstream trigger" "Request,Strobe" hexmask.long.byte 0x00 24.--30. 1. " SBDWNDACLKCLENL ,Sideband downstream clock cycle time" bitfld.long 0x00 23. " SBUPDWIDTH ,Sideband upstream ports enable" "Data[0],Data[1:0]" bitfld.long 0x00 22. " SBUPDACLK ,Sideband upstream data validation" "Data valid,Data[1]" newline bitfld.long 0x00 21. " SBDWNDWIDTH ,Sideband upstream data validation" "Data[0],Data[1:0]" bitfld.long 0x00 19.--20. " SBDWNDACLK ,Sideband downstream clock generate source" "Disabled,Sideband trigger,Internal counter,Disabled" bitfld.long 0x00 18. " EPHY ,Internal A-Shell to external APIX PHY connection control" "Disabled,Enabled" bitfld.long 0x00 17. " ESHELL ,Internal APIX PHY to external A-Shell connection control" "Disabled,Enabled" newline bitfld.long 0x00 16. " SPIOVERSB ,SPI over sideband control" "Disabled,Enabled" bitfld.long 0x00 14.--15. " CRCTIMEOUTVAL[2:3] ,CRC timeout value - multiplier" "1,4,16,128" bitfld.long 0x00 12.--13. " CRCTIMEOUTVAL[0:1] ,CRC timeout value - Base" "2,4,6,10" bitfld.long 0x00 8.--11. " WINDOWSIZE ,acknowledgment window size" ",1,2,3,4,5,6,7,8,9,10,11,12,?..." newline bitfld.long 0x00 6. " SUPPRESSITA ,Outbound idle transaction control" "Sent,Not sent" bitfld.long 0x00 0.--2. " SBDWNDACLKCLENU , Sideband downstream clock cycle time" "0,1,2,3,4,5,6,7" endif newline group.long 0x138++0x03 line.long 0x00 "TST,ARH Test Register" bitfld.long 0x00 9. " RW ,RW RAM mode" "Read,Write" bitfld.long 0x00 8. " TM ,TM Test mode" "FIFO,RAM" hexmask.long.byte 0x00 0.--6. 1. " ADDR ,Address" wgroup.long 0x13C++0x03 line.long 0x00 "UNLOCK,ARH Unlock Register" rgroup.long 0x140++0x03 line.long 0x00 "MID,ARH Module ID Register" newline if ((per.l(ad:0xB8030000+0x04)&0x4000000)==0x4000000) group.long 0x144++0x03 line.long 0x00 "APCFG04,ARH APIX Configuration Register" bitfld.long 0x00 31. " SYSCLKSEL ,A-Shell0 system clock source selector" "62.5 MHz,Bus clock" bitfld.long 0x00 14.--15. " AACCLKDATAOFST ,AIC2 clock data offset" "1 cycle,2 cycles,3 cycles,4 cycles" hexmask.long.word 0x00 2.--13. 1. " AACCLKFREQ ,AIC2 clock frequency" bitfld.long 0x00 1. " DATAPATHSEL ,Data path selection" "APIX PHY,AIC2" bitfld.long 0x00 0. " AACCLKMODE ,AIC2 clock mode" "Both edges,Rising edges" else rgroup.long 0x144++0x03 line.long 0x00 "APCFG04,ARH APIX Configuration Register" bitfld.long 0x00 31. " SYSCLKSEL ,A-Shell0 system clock source selector" "62.5 MHz,Bus clock" bitfld.long 0x00 14.--15. " AACCLKDATAOFST ,AIC2 clock data offset" "1 cycle,2 cycles,3 cycles,4 cycles" hexmask.long.word 0x00 2.--13. 1. " AACCLKFREQ ,AIC2 clock frequency" bitfld.long 0x00 1. " DATAPATHSEL ,Data path selection" "APIX PHY,AIC2" bitfld.long 0x00 0. " AACCLKMODE ,AIC2 clock mode" "Both edges,Rising edges" endif if ((per.l(ad:0xB8030000+0x14)&0x4000000)==0x4000000) group.long 0x148++0x03 line.long 0x00 "APCFG14,ARH APIX Configuration Register" bitfld.long 0x00 31. " SYSCLKSEL ,A-Shell0 system clock source selector" "62.5 MHz,Bus clock" bitfld.long 0x00 14.--15. " AACCLKDATAOFST ,AIC2 clock data offset" "1 cycle,2 cycles,3 cycles,4 cycles" hexmask.long.word 0x00 2.--13. 1. " AACCLKFREQ ,AIC2 clock frequency" bitfld.long 0x00 1. " DATAPATHSEL ,Data path selection" "APIX PHY,AIC2" bitfld.long 0x00 0. " AACCLKMODE ,AIC2 clock mode" "Both edges,Rising edges" else rgroup.long 0x148++0x03 line.long 0x00 "APCFG14,ARH APIX Configuration Register" bitfld.long 0x00 31. " SYSCLKSEL ,A-Shell0 system clock source selector" "62.5 MHz,Bus clock" bitfld.long 0x00 14.--15. " AACCLKDATAOFST ,AIC2 clock data offset" "1 cycle,2 cycles,3 cycles,4 cycles" hexmask.long.word 0x00 2.--13. 1. " AACCLKFREQ ,AIC2 clock frequency" bitfld.long 0x00 1. " DATAPATHSEL ,Data path selection" "APIX PHY,AIC2" bitfld.long 0x00 0. " AACCLKMODE ,AIC2 clock mode" "Both edges,Rising edges" endif group.long 0x14C++0x03 line.long 0x00 "EVAL0,APIX PHY Evaluation Transmitter Pattern Register" hexmask.long.word 0x00 0.--15. 1. " TXPATTERN ,TX pattern configuration" rgroup.long 0x150++0x03 line.long 0x00 "EVAL1,APIX PHY Evaluation Receiver Pattern Register" hexmask.long.word 0x00 0.--15. 1. " RXPATTERN ,RX pattern configuration" newline group.long 0x154++0x03 line.long 0x00 "EVAL2,APIX PHY Evaluation Receiver Pattern Register" bitfld.long 0x00 30.--31. " PATTERNGENEN ,Pattern generated and/or checked" "16-bit/invering,16-bit,10-bit PRBS,Preamble 55AA" bitfld.long 0x00 29. " RXEDGE ,Edge selector for sampling" "Rising edge,Falling edge" bitfld.long 0x00 28. " PATTERNRATE ,Pattern rate selector for generator and checker" "DWNBWMODE,62.5Mb/s" bitfld.long 0x00 27. " PATTCHKSOURCE ,pattern cCheck source" "Samplers,Rx Bit" newline bitfld.long 0x00 25.--26. " ERRORHOLD ,Hold time for EVAL2:RXEQTX on error" "16ns,256ns,Until EVAL3:RXTXLOCKED,Until EVAL2:PATTERNGENEN" bitfld.long 0x00 21.--23. " TXSOURCE ,Transmit data source" "Tx Data from core,Pattern generator,Sampled data,Rx Bit,500Mbps Toggle,250Mbps Toggle,125Mbps Toggle,62.5Mbps Toggle" bitfld.long 0x00 19.--20. " ENLOOPBCK ,Enable loopback" "Disabled,Disabled,From serializer output,From SDOUT" bitfld.long 0x00 18. " RXEPTRIGGER ,EVAL3:RXEDGEPOS[3] enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--15. " LOOPBCKSWING , Loopback swing control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " TESTPD ,Power down for test" "No effect,Power off" bitfld.long 0x00 4. " MASKPLLGOODSET ,A-Shell0 MASKPLLGOOD set" "No effect,Set" bitfld.long 0x00 3. " MASKPLLGOODCLR ,A-Shell0 MASKPLLGOOD clear" "No effect,Cleared" newline bitfld.long 0x00 2. " RXREALIGNSET ,A-Shell0 RXREALIGN set bit" "No effect,Set" bitfld.long 0x00 1. " RXREALIGNCLR ,A-Shell0 RXREALIGN clear bit" "No effect,Cleared" bitfld.long 0x00 0. " TESTENABLE ,Enable BIST" "Disabled,Enabled" newline rgroup.long 0x158++0x07 line.long 0x00 "EVAL3,APIX PHY Evaluation Receiver Status Register" bitfld.long 0x00 31. " RXTXLOCKED ,Preamble lock status" "Not detected,Detected" bitfld.long 0x00 30. " RXEQTX ,RX pattern status" "Not detected,Detected" hexmask.long.byte 0x00 24.--27. 1. " RXEDGEPOS ,Position of last edge in upstream data" line.long 0x04 "EVAL4,APIX PHY Evaluation Misc Test Enable Register" hexmask.long 0x04 6.--31. 1. " TESTMISC ,TESTMISC[25:0]" bitfld.long 0x04 5. " LOCK2PATTERN ,Lock pattern selection" "Preamble,Pattern" bitfld.long 0x04 0.--4. " TESTLENGTH ,Length of BIST test pattern" "2^0,2^1,2^2,2^3,2^4,2^5,2^6,2^7,2^8,2^9,2^10,2^11,2^12,2^13,2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29,No test,No test" group.long 0x164++0x03 line.long 0x00 "EVAL6,APIX PHY Evaluation Misc Test Configuration Register" rgroup.long 0x168++0x03 line.long 0x00 "EVAL7,APIX PHY Evaluation Misc Test Status Register" width 0x0B tree.end endif sif (!cpuis("S6J335*")&&!cpuis("S6J336*")&&!cpuis("S6J337*")) tree "GRAPHICS SUBSYSTEM" base ad:0x50200000 width 13. tree "2D Subsystem Control Address Block 0" wgroup.long 0x00++0x03 line.long 0x00 "LU,Lock Unlock" rgroup.long 0x04++0x03 line.long 0x00 "LS,Lock Status Register" bitfld.long 0x00 8. " FS ,Freeze status" "Inactive,Active" bitfld.long 0x00 4. " PS ,Privilege status" "Inactive,Active" bitfld.long 0x00 0. " LS ,Lock status" "Changeable,Not changeable" group.long 0x08++0x07 line.long 0x00 "IPID,ID Identifier Register" bitfld.long 0x00 28.--31. " IPF ,IP family" "Generation 2010,Generation 2012,Generation 2013,?..." bitfld.long 0x00 24.--27. " IPC ,IP configuration" "Core only,Core and subsystem,Subsystem/core/3d,?..." bitfld.long 0x00 20.--23. " IPA ,IP application" "Blit,Blitdisplay,Displaycapture,Blitdisplaycapt-draw,Display,Blitdisplay-draw,?..." newline bitfld.long 0x00 16.--19. " IPS ,IP feature set" "ECO,LIGHT,STANDARD,PLUS,EXTENSIVE,?..." bitfld.long 0x00 12.--15. " IPE ,IP evolution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DML ,Design maturity level" "Pre feasibility study,Feasibility study,Functionality complete,Verification complete,?..." newline bitfld.long 0x00 4.--7. " DDID ,Design delivery ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CCC,Configuration Clock Control Register" bitfld.long 0x04 0.--2. " CCS ,Configuration clock select" ",1,2,3,4,5,6,7" newline group.long 0x10++0x03 line.long 0x00 "LCDBINTEN,LCD Bus Interface Interrupt Enable Register" bitfld.long 0x00 4. " TEINTEN ,Tearing effect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " RXFIFOINTEN ,Rx Fifo interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " INSTFIFOINTEN ,Tx Fifo interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SEQSYNINTEN ,Sequencer sync interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " SEQERRINTEN ,Sequencer error interrupt enable" "Disabled,Enabled" wgroup.long 0x14++0x07 line.long 0x00 "LCDBINTPRES,LCD Bus Interface Interrupt Preset Register" bitfld.long 0x00 4. " TEINTPRES ,Tearing effect interrupt preset" "No effect,Interrupt" bitfld.long 0x00 3. " RXFIFOINTPRES ,Rx Fifo interrupt preset" "No effect,Interrupt" bitfld.long 0x00 2. " INSTFIFOINTPRES ,Tx Fifo interrupt preset" "No effect,Interrupt" newline bitfld.long 0x00 1. " SEQSYNINTPRES ,Sequencer sync interrupt preset" "No effect,Interrupt" bitfld.long 0x00 0. " SEQERRINTPRES ,Sequencer error interrupt preset" "No effect,Interrupt" line.long 0x04 "LCDBINTCLR,LCD Bus Interface Interrupt Clear Register" bitfld.long 0x04 4. " TEINTCLR ,Tearing effect interrupt clear" "No effect,Clear" bitfld.long 0x04 3. " RXFIFOINTCLR ,Rx Fifo interrupt clear" "No effect,Clear" bitfld.long 0x04 2. " INSTFIFOINTCLR ,Tx Fifo interrupt clear" "No effect,Clear" newline bitfld.long 0x04 1. " SEQSYNINTCLR ,Sequencer sync interrupt clear" "No effect,Clear" bitfld.long 0x04 0. " SEQERRINTCLR ,Sequencer error interrupt clear" "No effect,Clear" rgroup.long 0x1C++0x03 line.long 0x00 "LCDBINTSTAT,LCD Bus Interface Interrupt Status Register" bitfld.long 0x00 4. " TEINTSTAT ,Tearing effect interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " RXFIFOINTSTAT ,Rx Fifo interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " INSTFIFOINTSTAT ,Tx Fifo interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " SEQSYNINTSTAT ,Sequencer sync interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " SEQERRINTSTAT ,Sequencer error interrupt status" "No interrupt,Interrupt" tree.end width 9. tree "2D Subsystem Control Address Block 1" group.long 0x40++0x03 line.long 0x00 "DSP_LU,DSP Lock Unlock Register" rgroup.long 0x44++0x03 line.long 0x00 "DSP_LS,DSP Lock Status Register" bitfld.long 0x00 8. " DSP_FREEZESTATUS ,Display freeze status" "Inactive,Active" bitfld.long 0x00 4. " DSP_PRIVILEGESTATUS ,Display privilege status" "Inactive,Active" bitfld.long 0x00 0. " DSP_LOCKSTATUS ,Display lock status" "Changeable,Not changeable" group.long 0x48++0x07 line.long 0x00 "DSP0_CD,DSP0 Clock Divider Register" hexmask.long.word 0x00 8.--23. 1. " DSP0_CLKDIV ,Display0 clock divider" line.long 0x04 "DSP0_DC,DSP0 Domain Control Register" bitfld.long 0x04 16. " DSP0_SOFTWARERESET ,Display0 software reset" "Operational,Reset state" bitfld.long 0x04 0. " DSP0_CLOCKENABLE ,Display0 clock enable" "Disabled,Enabled" if (((per.l(ad:0x50200000+0x4C))&0x01)==0x01) rgroup.long 0x50++0x03 line.long 0x00 "DSP0_CS,DSP0 Clock Shift Register" hexmask.long.byte 0x00 16.--23. 1. " DSP0_CLOCKOFFSET ,Display0 clock offset" bitfld.long 0x00 0. " DSP0_CLOCKINVERT ,Display0 clock invert" "Not displayed,Displayed" else group.long 0x50++0x03 line.long 0x00 "DSP0_CS,DSP0 Clock Shift Register" hexmask.long.byte 0x00 16.--23. 1. " DSP0_CLOCKOFFSET ,Display0 clock offset" bitfld.long 0x00 0. " DSP0_CLOCKINVERT ,Display0 clock invert" "Not displayed,Displayed" endif tree.end width 16. tree "2D Subsystem Control Address Block 2" wgroup.long 0x300++0x03 line.long 0x00 "HPM_LOCKUNLOCK,HPM Lock Unlock Register" rgroup.long 0x304++0x03 line.long 0x00 "HPM_LOCKSTATUS,HPM Lock Status Register" bitfld.long 0x00 8. " HPM_FREEZESTATUS ,High performance bus matrix registers freeze status" "Inactive,Active" bitfld.long 0x00 4. " HPM_PRIVILEGESTATUS ,High performance bus matrix registers privilege status" "Inactive,Active" bitfld.long 0x00 0. " HPM_LOCKSTATUS ,High performance bus matrix registers lock status" "Changeable status,Not changeable status" tree.end base ad:0x50400000 width 23. tree "AXI Interconnect - Network Interconnect" group.long 0x5044++0x03 line.long 0x00 "AHB_CTRL_AHB_CNTL,AHB_CTRL_AHB_CNTL Register" bitfld.long 0x00 0. " AHB_CTRL_DECERR_EN ,Enable decode error generation upon the unaligned transfer occuring" "Disabled,Enabled" group.long 0x42100++0x07 line.long 0x00 "MSM_READ_QOS,MSM Read QoS Register" bitfld.long 0x00 0.--3. " MSM_AR_QOS ,Read channel QoS value" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" line.long 0x04 "MSM_WRITE_QOS,MSM Write QoS Register" bitfld.long 0x04 0.--3. " MSM_AW_QOS ,Write channel QoS value" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.long 0x49100++0x03 line.long 0x00 "FETCHDECODE0_READ_QOS,Fetchdecode0 Read QoS Register" bitfld.long 0x00 0.--3. " FDEC0_AR_QOS ,Fetchdecode0 read channel QoS value" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.long 0x4A100++0x03 line.long 0x00 "FETCHLAYER0_READ_QOS,Fetchlayer0 Read QoS Register" bitfld.long 0x00 0.--3. " FL0_AR_QOS ,Fetchdecode0 read channel QoS value" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" tree.end base ad:0x50214000 width 24. tree "AXI Interconnect - Performance Measurement Unit" group.long 0x00++0x17 line.long 0x00 "CONTROL,Control Register" bitfld.long 0x00 31. " OTCDISABLE ,OTC counters disable" "No,Yes" bitfld.long 0x00 1. " MODE ,Measurement mode" "Manual,Timer" bitfld.long 0x00 0. " ENABLE ,Measurement enable" "Disabled,Enabled" line.long 0x04 "TIMER,Timer Control Register" bitfld.long 0x04 28.--31. " DIVIDER ,Predivider value of timer" ",/1,/3,/7,/15,/31,/63,/127,/255,/511,/1023,/2047,/4095,/8191,/16383,/32767" hexmask.long 0x04 0.--27. 1. " LOAD ,Timer preset value" line.long 0x08 "ID_MASK,ID Mask Register" hexmask.long.byte 0x08 0.--7. 1. " MASK ,ID mask" line.long 0x0C "ID_VALUE,ID Mask Register" hexmask.long.byte 0x0C 0.--7. 1. " VALUE ,ID value" line.long 0x10 "SW_TAG,Software Tag Register" line.long 0x14 "MEASUREMENTTIMECONTROL,Measurement Time Control Register" bitfld.long 0x14 31. " MTENABLE ,Enable measurement time" "Disabled,Enabled" hexmask.long.tbyte 0x14 0.--19. 1. " MTDIVIDER ,Predivider for measurement time" rgroup.long 0x18++0x07 line.long 0x00 "MEASUREMENTTIME,Measurement Time Register" line.long 0x04 "GLOBALCOUNTER,Global Counter Register" newline group.long 0x20++0x03 line.long 0x00 "MU0_SWITCH,MU0 Source Select Register" bitfld.long 0x00 0.--2. " MU0_SWITCH ,Source select for measurement unit 0" "Msm read,Msm write,Fetchdecode0 read,Fetchdecode0 write,?..." rgroup.long (0x20+0x04)++0x13 line.long 0x00 "MU0_DATACOUNTER,MU0 Data Counter Register" line.long 0x04 "MU0_BUSYCOUNTER,MU0 Busy Counter Register" line.long 0x08 "MU0_TRANSFERCOUNTER,MU0 Transfer Counter Register" line.long 0x0C "MU0_ADDRBUSYCOUNTER,MU0 Address Busy Counter Register" line.long 0x10 "MU0_LATENCYCOUNTER,MU0 Latency Counter Register" group.long 0x38++0x03 line.long 0x00 "MU1_SWITCH,MU1 Source Select Register" bitfld.long 0x00 0.--2. " MU1_SWITCH ,Source select for measurement unit 1" "Msm read,Msm write,Fetchdecode0 read,Fetchdecode0 write,?..." rgroup.long (0x38+0x04)++0x13 line.long 0x00 "MU1_DATACOUNTER,MU1 Data Counter Register" line.long 0x04 "MU1_BUSYCOUNTER,MU1 Busy Counter Register" line.long 0x08 "MU1_TRANSFERCOUNTER,MU1 Transfer Counter Register" line.long 0x0C "MU1_ADDRBUSYCOUNTER,MU1 Address Busy Counter Register" line.long 0x10 "MU1_LATENCYCOUNTER,MU1 Latency Counter Register" tree.end width 24. tree "AXI Interconnect - Error Monitor" group.long 0x400++0x07 line.long 0x00 "MONITORDISABLE,Interconnect Error Monitor Disable Register" bitfld.long 0x00 2. " FETCHLAYER0 ,Master fetchlayer0 monitor disable" "No,Yes" bitfld.long 0x00 1. " FETCHDECODE0 ,Master fetchdecode0 monitor disable" "No,Yes" bitfld.long 0x00 0. " MSM ,Master msm monitor disable" "No,Yes" line.long 0x04 "MONITORINTERRUPTENABLE,Interconnect Error Monitor Non-maskable Interrupt Enable Register" bitfld.long 0x04 0. " MONINTEN ,Monitor interrupt enable" "Disabled,Enabled" wgroup.long 0x408++0x03 line.long 0x00 "MONITORINTERRUPTCLEAR,Interconnect Error Monitor Non-maskable Interrupt Clear Register" bitfld.long 0x00 0. " MONINTCLR ,Monitor interrupt clear" "No effect,Clear" newline rgroup.long 0x40C++0x03 line.long 0x00 "MONITORSTATUS,Interconnect Error Monitor Status Register" hexmask.long.byte 0x00 16.--23. 1. " ERRORSUBID ,ID that caused the erronous request" bitfld.long 0x00 8.--10. " ERRORID ,ID of master that did erronous request" "Msm,Fetchdecode0,Fetchlayer0,,,,,No error" bitfld.long 0x00 0.--1. " ERRORTYPE ,Type of detected error" "No error,,Slave error,Decoder error" tree.end width 0x0B tree.end endif newline